the following patch was just integrated into master:
commit c5e040bd238af5a5ded58fc715e464bbd85b275a
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Mon Aug 18 23:54:54 2014 +0200
lenovo/x201: Fix dock recognition
Change-Id: I8b210786f660e2b2bae0d9ddd594386fd107cbe4
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6706
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6706 for details.
-gerrit
the following patch was just integrated into master:
commit f319ae40d702b3012429d09a05633eadd18ea4c2
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Tue Aug 19 00:48:39 2014 +0200
lenovo/x201: Unpower USB on undocking
Change-Id: I9b496e8ff92ee575d0b780eab0cb45ea05506d30
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6708
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/6708 for details.
-gerrit
the following patch was just integrated into master:
commit dc9cfa431e46d6083ebb83fff5be22de7969bb26
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Mon Aug 18 23:52:53 2014 +0200
lenovo/x200: Dock support
Change-Id: I4e25630ae82e8030a9d6bfccb60844c301b1d635
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6705
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6705 for details.
-gerrit
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6714
-gerrit
commit c1603c670bb0abf92b922849ce766344b65e0baf
Author: Gabe Black <gabeblack(a)google.com>
Date: Thu Sep 26 23:21:57 2013 -0700
arm: Get rid of the INTERMEDIATE variable used on exynos.
The INTERMEDIATE variable was used to hook dd-ing the BL1 into the image for
Exynos SOCs, but we can do that directly without having a special hook.
Change-Id: I434506b52ca4ea1d01e25a785cbfe66dfdea21c4
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/170921
Reviewed-by: Hung-Te Lin <hungte(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 8db03c387ad654227d064e2a7fa5ecf09d07e3c5)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/cpu/samsung/exynos5250/Makefile.inc | 10 +++++-----
src/cpu/samsung/exynos5420/Makefile.inc | 10 +++++-----
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc
index 4b967b0..762b940 100644
--- a/src/cpu/samsung/exynos5250/Makefile.inc
+++ b/src/cpu/samsung/exynos5250/Makefile.inc
@@ -1,8 +1,3 @@
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE += exynos5250_add_bl1
-
bootblock-y += spi.c alternate_cbfs.c
bootblock-y += pinmux.c mct.c power.c
# Clock is required for UART
@@ -54,6 +49,11 @@ ramstage-y += fb.c
ramstage-y += usb.c
ramstage-y += cbmem.c
+# Run an intermediate step when producing coreboot.rom
+# that adds additional components to the final firmware
+# image outside of CBFS
+.PHONY: exynos5250_add_bl1
+$(obj)/coreboot.rom: exynos5250_add_bl1
exynos5250_add_bl1: $(obj)/coreboot.pre
printf " DD Adding Samsung Exynos5250 BL1\n"
dd if=3rdparty/cpu/samsung/exynos5250/bl1.bin \
diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc
index 897944c..cbf9882 100644
--- a/src/cpu/samsung/exynos5420/Makefile.inc
+++ b/src/cpu/samsung/exynos5420/Makefile.inc
@@ -1,8 +1,3 @@
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-INTERMEDIATE += exynos5420_add_bl1
-
bootblock-y += spi.c alternate_cbfs.c
bootblock-y += pinmux.c mct.c power.c
# Clock is required for UART
@@ -54,6 +49,11 @@ ramstage-y += dp.c dp_lowlevel.c fimd.c
ramstage-y += usb.c
ramstage-y += cbmem.c
+# Run an intermediate step when producing coreboot.rom
+# that adds additional components to the final firmware
+# image outside of CBFS
+.PHONY: exynos5420_add_bl1
+$(obj)/coreboot.rom: exynos5420_add_bl1
exynos5420_add_bl1: $(obj)/coreboot.pre
printf " DD Adding Samsung Exynos5420 BL1\n"
dd if=3rdparty/cpu/samsung/exynos5420/bl1.bin \
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6713
-gerrit
commit ec4e33770285816074d13d868fa0be7607d2978b
Author: Gabe Black <gabeblack(a)google.com>
Date: Sun Sep 29 06:32:27 2013 -0700
tegra124: Add a custom bootblock implementation.
This implementation is the same as the general one except that it removes all
the things that don't work on an ARMv4.
Change-Id: I1108a79cc656b26f7d48df20aef3016cf5ae3182
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/171019
Reviewed-by: Ronald Minnich <rminnich(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit d1436288d3b025af27a8d28ba94b589940ead504)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/soc/nvidia/tegra124/Kconfig | 2 +-
src/soc/nvidia/tegra124/Makefile.inc | 4 ++
src/soc/nvidia/tegra124/bootblock.c | 16 +++++-
src/soc/nvidia/tegra124/bootblock_asm.S | 98 +++++++++++++++++++++++++++++++++
4 files changed, 117 insertions(+), 3 deletions(-)
diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig
index fd1f0aa..321dab3 100644
--- a/src/soc/nvidia/tegra124/Kconfig
+++ b/src/soc/nvidia/tegra124/Kconfig
@@ -4,7 +4,7 @@ config SOC_NVIDIA_TEGRA124
select ARCH_RAMSTAGE_ARMV7
bool
default n
- select CPU_HAS_BOOTBLOCK_INIT
+ select ARM_BOOTBLOCK_CUSTOM
if SOC_NVIDIA_TEGRA124
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index 3f626cf..b1ecb0f 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -1,6 +1,10 @@
CBOOTIMAGE = cbootimage
+bootblock-c-ccopts += -marm
+bootblock-S-ccopts += -marm
+
bootblock-y += bootblock.c
+bootblock-y += bootblock_asm.S
bootblock-y += cbfs.c
bootblock-y += clock.c
bootblock-y += monotonic_timer.c
diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c
index 66e6b3b..97180a0 100644
--- a/src/soc/nvidia/tegra124/bootblock.c
+++ b/src/soc/nvidia/tegra124/bootblock.c
@@ -17,8 +17,20 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <bootblock_common.h>
+#include <arch/hlt.h>
+#include <arch/stages.h>
+#include <cbfs.h>
+#include <console/console.h>
-void bootblock_cpu_init(void)
+void main(void)
{
+ void *entry;
+
+ if (CONFIG_BOOTBLOCK_CONSOLE)
+ console_init();
+
+ entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage");
+
+ if (entry) stage_exit(entry);
+ hlt();
}
diff --git a/src/soc/nvidia/tegra124/bootblock_asm.S b/src/soc/nvidia/tegra124/bootblock_asm.S
new file mode 100644
index 0000000..8d0beb8
--- /dev/null
+++ b/src/soc/nvidia/tegra124/bootblock_asm.S
@@ -0,0 +1,98 @@
+/*
+ * Early initialization code for ARMv7 architecture.
+ *
+ * This file is based off of the OMAP3530/ARM Cortex start.S file from Das
+ * U-Boot, which itself got the file from armboot.
+ *
+ * Copyright (c) 2004 Texas Instruments <r-woodruff2(a)ti.com>
+ * Copyright (c) 2001 Marius Gröger <mag(a)sysgo.de>
+ * Copyright (c) 2002 Alex Züpke <azu(a)sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <garyj(a)denx.de>
+ * Copyright (c) 2003 Richard Woodruff <r-woodruff2(a)ti.com>
+ * Copyright (c) 2003 Kshitij <kshitij(a)ti.com>
+ * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim(a)ti.com>
+ * Copyright (c) 2013 The Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.section ".start", "a", %progbits
+.globl _start
+_start: b reset
+ .balignl 16,0xdeadbeef
+
+_cbfs_master_header:
+ /* The CBFS master header is inserted by cbfstool at the first
+ * aligned offset after the above anchor string is found.
+ * Hence, we leave some space for it.
+ */
+ .skip 128 @ Assumes 64-byte alignment
+
+reset:
+ /*
+ * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
+ * aborts may happen early and crash before the abort handlers are
+ * installed, but at least the problem will show up near the code that
+ * causes it.
+ */
+ msr cpsr_cxf, #0xdf
+
+ /*
+ * Initialize the stack to a known value. This is used to check for
+ * stack overflow later in the boot process.
+ */
+ ldr r0, .Stack
+ ldr r1, .Stack_size
+ sub r0, r0, r1
+ ldr r1, .Stack
+ ldr r2, =0xdeadbeef
+init_stack_loop:
+ str r2, [r0]
+ add r0, #4
+ cmp r0, r1
+ bne init_stack_loop
+
+/* Set stackpointer in internal RAM to call board_init_f */
+call_bootblock:
+ ldr sp, .Stack /* Set up stack pointer */
+ ldr r0,=0x00000000
+ /*
+ * The current design of cpu_info places the
+ * struct at the top of the stack. The number of
+ * words pushed must be at least as large as that
+ * struct.
+ */
+ push {r0-r2}
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+ /*
+ * Use "bl" instead of "b" even though we do not intend to return.
+ * "bl" gets compiled to "blx" if we're transitioning from ARM to
+ * Thumb. However, "b" will not and GCC may attempt to create a
+ * wrapper which is currently broken.
+ */
+ bl main
+
+/* we do it this way because it's a 32-bit constant and
+ * in some cases too far away to be loaded as just an offset
+ * from IP
+ */
+.align 2
+.Stack:
+ .word CONFIG_STACK_TOP
+.align 2
+/* create this size the same way we do in coreboot_ram.ld: top-bottom */
+.Stack_size:
+ .word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM
Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5957
-gerrit
commit 10952b9cec3bdfbf8c4bef0121521cc3bbb5c91c
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sat Jun 7 21:50:21 2014 +0200
[NOTFORMERGE] device/Kconfig: Select native graphics init by default
Just for build testing the native graphics patches.
Change-Id: I47ed328ce8ce3516ad3997978a01d2359d9b1ca8
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Signed-off-by: Francis Rowe <info(a)gluglug.org.uk>
---
src/device/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 58dcc1b..3d47602 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -32,7 +32,7 @@ config MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
config MAINBOARD_DO_NATIVE_VGA_INIT
bool "Use native graphics initialization"
depends on MAINBOARD_HAS_NATIVE_VGA_INIT
- default n
+ default y
help
Some mainboards, such as the Google Link, allow initializing the display
without the need of a binary only VGA OPROM. Enabling this option may be
Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5927
-gerrit
commit 581ca4ff46831f5c5e5c4e876b3fd1db43fd601e
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Thu Jun 5 22:45:35 2014 +0200
intel/i945/gma: Place GTT below top of memory
Since commit 17fec8a0 [1]
drm/i915: Use Graphics Base of Stolen Memory on all gen3+
present in the Linux kernel since version 3.12, 3D does not work
anymore [2].
Comparing the graphics registers, in this case that means output of
`intel_reg_dumper`, the vendor Video BIOS is setting the register
PGTBL_CTL/PGETBL_CTL, only documented in the i965 datasheet [3], to
`0x3ffc0001` on a system with 1 GB of RAM, while native graphics init
sets it to `0x3f800001`.
Currently native graphis init sets the GTT right above the base
address of stolen memory. The Video BIOS sets it below the top of
memory. The Linux Intel driver expects it to be below top of memory, so
do it this way, by setting the address to TOM minus the size of the GTT,
which is hardcoded to 256 KiB.
As `PGETBL_CTL` is zero by default, reading its value in the beginning
is not necessary and is only confusing. Make it clear that the code
calculates the value.
There is still a PTE error reported during boot, but 3D works
with Linux 3.12+ and no user visible problems are shown.
[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=…
[2] https://bugs.freedesktop.org/show_bug.cgi?id=79038
[3] https://01.org/linuxgraphics/sites/default/files/documentation/965_g35_vol_…
Intel ® 965 Express Chipset Family and
Intel ® G35 Express Chipset Graphics Controller
Programmer’s Reference Manual
Volume 1: Graphics Core
Revision 1.0a
Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Signed-off-by: Francis Rowe <info(a)gluglug.org.uk>
---
src/northbridge/intel/i945/gma.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 140aaa7..e8a57b1 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -52,11 +52,19 @@
static int gtt_setup(unsigned int mmiobase)
{
unsigned long PGETBL_save;
-
- PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
+ unsigned long tom; // top of memory
+
+ /*
+ * The Video BIOS places the GTT right below top of memory.
+ *
+ * It is not documented in the Intel 945 datasheet, but the Intel
+ * developers said that it is normally placed there.
+ *
+ * TODO: Add option to make the GTT size runtime configurable
+ */
+ tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24;
+ PGETBL_save = tom - 256 * KiB;
PGETBL_save |= PGETBL_ENABLED;
-
- PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000;
PGETBL_save |= 2; /* set GTT to 256kb */
write32(mmiobase + GFX_FLSH_CNTL, 0);
Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5957
-gerrit
commit 33358ea87d83257b7bedb622cce92b57742a4255
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sat Jun 7 21:50:21 2014 +0200
[NOTFORMERGE] device/Kconfig: Select native graphics init by default
Just for build testing the native graphics patches.
Change-Id: I47ed328ce8ce3516ad3997978a01d2359d9b1ca8
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Signed-off-by: Francis Rowe <info(a)gluglug.org.uk>
---
src/device/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 58dcc1b..3d47602 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -32,7 +32,7 @@ config MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
config MAINBOARD_DO_NATIVE_VGA_INIT
bool "Use native graphics initialization"
depends on MAINBOARD_HAS_NATIVE_VGA_INIT
- default n
+ default y
help
Some mainboards, such as the Google Link, allow initializing the display
without the need of a binary only VGA OPROM. Enabling this option may be
Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5927
-gerrit
commit ff21c1019b95e4331db587e6260e15880f0b228c
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Thu Jun 5 22:45:35 2014 +0200
intel/i945/gma: Place GTT below top of memory
Since commit 17fec8a0 [1]
drm/i915: Use Graphics Base of Stolen Memory on all gen3+
present in the Linux kernel since version 3.12, 3D does not work
anymore [2].
Comparing the graphics registers, in this case that means output of
`intel_reg_dumper`, the vendor Video BIOS is setting the register
PGTBL_CTL/PGETBL_CTL, only documented in the i965 datasheet [3], to
`0x3ffc0001` on a system with 1 GB of RAM, while native graphics init
sets it to `0x3f800001`.
Currently native graphis init sets the GTT right above the base
address of stolen memory. The Video BIOS sets it below the top of
memory. The Linux Intel driver expects it to be below top of memory, so
do it this way, by setting the address to TOM minus the size of the GTT,
which is hardcoded to 256 KiB.
As `PGETBL_CTL` is zero by default, reading its value in the beginning
is not necessary and is only confusing. Make it clear that the code
calculates the value.
There is still an error PTE error reported during boot, but 3D works
with Linux 3.12+ and no user visible problems are shown.
[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=…
[2] https://bugs.freedesktop.org/show_bug.cgi?id=79038
[3] https://01.org/linuxgraphics/sites/default/files/documentation/965_g35_vol_…
Intel ® 965 Express Chipset Family and
Intel ® G35 Express Chipset Graphics Controller
Programmer’s Reference Manual
Volume 1: Graphics Core
Revision 1.0a
Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Signed-off-by: Francis Rowe <info(a)gluglug.org.uk>
---
src/northbridge/intel/i945/gma.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 140aaa7..e8a57b1 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -52,11 +52,19 @@
static int gtt_setup(unsigned int mmiobase)
{
unsigned long PGETBL_save;
-
- PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
+ unsigned long tom; // top of memory
+
+ /*
+ * The Video BIOS places the GTT right below top of memory.
+ *
+ * It is not documented in the Intel 945 datasheet, but the Intel
+ * developers said that it is normally placed there.
+ *
+ * TODO: Add option to make the GTT size runtime configurable
+ */
+ tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24;
+ PGETBL_save = tom - 256 * KiB;
PGETBL_save |= PGETBL_ENABLED;
-
- PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000;
PGETBL_save |= 2; /* set GTT to 256kb */
write32(mmiobase + GFX_FLSH_CNTL, 0);
Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5957
-gerrit
commit 9be9fdd9cb081595d7708f0e766c1e2117a16334
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sat Jun 7 21:50:21 2014 +0200
[NOTFORMERGE] device/Kconfig: Select native graphics init by default
Just for build testing the native graphics patches.
Change-Id: I47ed328ce8ce3516ad3997978a01d2359d9b1ca8
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Signed-off-by: Francis Rowe <info(a)gluglug.org.uk>
---
src/device/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 58dcc1b..3d47602 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -32,7 +32,7 @@ config MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
config MAINBOARD_DO_NATIVE_VGA_INIT
bool "Use native graphics initialization"
depends on MAINBOARD_HAS_NATIVE_VGA_INIT
- default n
+ default y
help
Some mainboards, such as the Google Link, allow initializing the display
without the need of a binary only VGA OPROM. Enabling this option may be