Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6108
-gerrit
commit 1a1862058f30dbfb2668c91e4cafa0794c4fdd9a
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Thu Jun 26 05:30:54 2014 +0300
AMD boards: Fix typos
Change-Id: I090e98fbf28595d3917ef84e19bd6d6742f11b94
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/mainboard/advansus/a785e-i/platform_cfg.h | 14 +++++++-------
src/mainboard/amd/inagua/platform_cfg.h | 14 +++++++-------
src/mainboard/amd/persimmon/platform_cfg.h | 14 +++++++-------
src/mainboard/amd/south_station/platform_cfg.h | 14 +++++++-------
src/mainboard/amd/torpedo/platform_cfg.h | 14 +++++++-------
src/mainboard/amd/union_station/platform_cfg.h | 14 +++++++-------
src/mainboard/asrock/e350m1/platform_cfg.h | 14 +++++++-------
src/mainboard/asus/m5a88-v/platform_cfg.h | 14 +++++++-------
src/mainboard/avalue/eax-785e/platform_cfg.h | 14 +++++++-------
src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h | 14 +++++++-------
src/mainboard/lippert/frontrunner-af/platform_cfg.h | 14 +++++++-------
src/mainboard/lippert/toucan-af/platform_cfg.h | 14 +++++++-------
12 files changed, 84 insertions(+), 84 deletions(-)
diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h
index 100b033..03ce4f2 100644
--- a/src/mainboard/advansus/a785e-i/platform_cfg.h
+++ b/src/mainboard/advansus/a785e-i/platform_cfg.h
@@ -53,13 +53,13 @@
* @brief bit[0-6] used to control USB
* 0 - Disable
* 1 - Enable
- * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
*/
#define USB_CONFIG 0x7F
diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h
index 151f587..a71412f 100644
--- a/src/mainboard/amd/inagua/platform_cfg.h
+++ b/src/mainboard/amd/inagua/platform_cfg.h
@@ -53,13 +53,13 @@
* @brief bit[0-6] used to control USB
* 0 - Disable
* 1 - Enable
- * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
*/
#define USB_CONFIG 0x7F
diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h
index f084b2f..3303282 100644
--- a/src/mainboard/amd/persimmon/platform_cfg.h
+++ b/src/mainboard/amd/persimmon/platform_cfg.h
@@ -53,13 +53,13 @@
* @brief bit[0-6] used to control USB
* 0 - Disable
* 1 - Enable
- * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
*/
#define USB_CONFIG 0x7F
diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h
index 151f587..a71412f 100644
--- a/src/mainboard/amd/south_station/platform_cfg.h
+++ b/src/mainboard/amd/south_station/platform_cfg.h
@@ -53,13 +53,13 @@
* @brief bit[0-6] used to control USB
* 0 - Disable
* 1 - Enable
- * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
*/
#define USB_CONFIG 0x7F
diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h
index bc69938..de4e89d 100644
--- a/src/mainboard/amd/torpedo/platform_cfg.h
+++ b/src/mainboard/amd/torpedo/platform_cfg.h
@@ -272,25 +272,25 @@
/**
* @section INCHIP_USB_CINFIG INCHIP_USB_CINFIG
*
- * - Usb Ohci1 Contoller is define at BIT0
+ * - Usb Ohci1 Controller is define at BIT0
* 0:Disable 1:Enable
* (Bus 0 Dev 18 Func0)
- * - Usb Ehci1 Contoller is define at BIT1
+ * - Usb Ehci1 Controller is define at BIT1
* 0:Disable 1:Enable
* (Bus 0 Dev 18 Func2)
- * - Usb Ohci2 Contoller is define at BIT2
+ * - Usb Ohci2 Controller is define at BIT2
* 0:Disable 1:Enable
* (Bus 0 Dev 19 Func0)
- * - Usb Ehci2 Contoller is define at BIT3
+ * - Usb Ehci2 Controller is define at BIT3
* 0:Disable 1:Enable
* (Bus 0 Dev 19 Func2)
- * - Usb Ohci3 Contoller is define at BIT4
+ * - Usb Ohci3 Controller is define at BIT4
* 0:Disable 1:Enable
* (Bus 0 Dev 22 Func0)
- * - Usb Ehci3 Contoller is define at BIT5
+ * - Usb Ehci3 Controller is define at BIT5
* 0:Disable 1:Enable
* (Bus 0 Dev 22 Func2)
- * - Usb Ohci4 Contoller is define at BIT6
+ * - Usb Ohci4 Controller is define at BIT6
* 0:Disable 1:Enable
* (Bus 0 Dev 20 Func5)
*/
diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h
index 151f587..a71412f 100644
--- a/src/mainboard/amd/union_station/platform_cfg.h
+++ b/src/mainboard/amd/union_station/platform_cfg.h
@@ -53,13 +53,13 @@
* @brief bit[0-6] used to control USB
* 0 - Disable
* 1 - Enable
- * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
*/
#define USB_CONFIG 0x7F
diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h
index 100b033..03ce4f2 100644
--- a/src/mainboard/asrock/e350m1/platform_cfg.h
+++ b/src/mainboard/asrock/e350m1/platform_cfg.h
@@ -53,13 +53,13 @@
* @brief bit[0-6] used to control USB
* 0 - Disable
* 1 - Enable
- * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
*/
#define USB_CONFIG 0x7F
diff --git a/src/mainboard/asus/m5a88-v/platform_cfg.h b/src/mainboard/asus/m5a88-v/platform_cfg.h
index 100b033..03ce4f2 100644
--- a/src/mainboard/asus/m5a88-v/platform_cfg.h
+++ b/src/mainboard/asus/m5a88-v/platform_cfg.h
@@ -53,13 +53,13 @@
* @brief bit[0-6] used to control USB
* 0 - Disable
* 1 - Enable
- * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
*/
#define USB_CONFIG 0x7F
diff --git a/src/mainboard/avalue/eax-785e/platform_cfg.h b/src/mainboard/avalue/eax-785e/platform_cfg.h
index 100b033..03ce4f2 100644
--- a/src/mainboard/avalue/eax-785e/platform_cfg.h
+++ b/src/mainboard/avalue/eax-785e/platform_cfg.h
@@ -53,13 +53,13 @@
* @brief bit[0-6] used to control USB
* 0 - Disable
* 1 - Enable
- * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
*/
#define USB_CONFIG 0x7F
diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
index ce08bee..69360c3 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
@@ -54,13 +54,13 @@
* @brief bit[0-6] used to control USB
* 0 - Disable
* 1 - Enable
- * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
*/
#define USB_CONFIG 0x7F
diff --git a/src/mainboard/lippert/frontrunner-af/platform_cfg.h b/src/mainboard/lippert/frontrunner-af/platform_cfg.h
index ed455ee..1d60263 100644
--- a/src/mainboard/lippert/frontrunner-af/platform_cfg.h
+++ b/src/mainboard/lippert/frontrunner-af/platform_cfg.h
@@ -53,13 +53,13 @@
* @brief bit[0-6] used to control USB
* 0 - Disable
* 1 - Enable
- * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
*/
#define USB_CONFIG 0x3F
diff --git a/src/mainboard/lippert/toucan-af/platform_cfg.h b/src/mainboard/lippert/toucan-af/platform_cfg.h
index 55ada45..2fc056a 100644
--- a/src/mainboard/lippert/toucan-af/platform_cfg.h
+++ b/src/mainboard/lippert/toucan-af/platform_cfg.h
@@ -53,13 +53,13 @@
* @brief bit[0-6] used to control USB
* 0 - Disable
* 1 - Enable
- * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
- * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
- * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
- * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
- * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
- * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
- * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
*/
#define USB_CONFIG 0x0F
the following patch was just integrated into master:
commit 0b4b230163c82e74e7ac9b74c0c8f8e4abe9130e
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Wed Jun 25 10:13:22 2014 -0600
bayleybay_fsp: Switch from EHCI controller to XHCI
- Disable the EHCI controller and enable the XHCI controller.
SeaBIOS has been tested on the board and boots an OS from a
flashdrive at SuperSpeed.
This also enables the top USB port on the 2-port stack, which goes
through a High Speed Inter-Chip port. The HSIC port is only enabled
through the XHCI device.
Change-Id: Ic3dfc55028fa5e081a30819fe9596b1a9f57fd9c
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6106
Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/6106 for details.
-gerrit
Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6106
-gerrit
commit 4858472465ec628ec17b3efa8e7bd5322996e5ff
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Wed Jun 25 10:13:22 2014 -0600
bayleybay_fsp: Switch from EHCI controller to XHCI
- Disable the EHCI controller and enable the XHCI controller.
SeaBIOS has been tested on the board and boots an OS from a
flashdrive at SuperSpeed.
This also enables the top USB port on the 2-port stack, which goes
through a High Speed Inter-Chip port. The HSIC port is only enabled
through the XHCI device.
Change-Id: Ic3dfc55028fa5e081a30819fe9596b1a9f57fd9c
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/mainboard/intel/bayleybay_fsp/devicetree.cb | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
index 1bde834..befd3dc 100644
--- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb
+++ b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
@@ -50,7 +50,7 @@ chip soc/intel/fsp_baytrail
device pci 11.0 on end # 8086 0F15 - SDIO Port (SD2 pins)
device pci 12.0 on end # 8086 0F16 - SD Port (SD3 pins)
device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23)
- device pci 14.0 off end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
+ device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
device pci 15.0 off end # 8086 0F28 - LP Engine Audio
device pci 16.0 off end # 8086 0F37 - OTG controller
device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
@@ -68,7 +68,7 @@ chip soc/intel/fsp_baytrail
device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (half mini pcie slot)
device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (front x1 slot)
device pci 1c.3 on end # 8086 0F4E - PCIe Root Port 4 (rear x1 slot)
- device pci 1d.0 on end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
+ device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
device pci 1e.0 on end # 8086 0F06 - SIO - DMA
device pci 1e.1 on end # 8086 0F08 - PWM 1
device pci 1e.2 on end # 8086 0F09 - PWM 2
Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5973
-gerrit
commit abedc94b43706f61c559f10ee1fcb84a00f5c676
Author: Dave Frodin <dave.frodin(a)se-eng.com>
Date: Wed Jun 11 12:53:47 2014 -0600
drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit()
At the end of some SPI operations the SPI device needs to be polled
to determine if it is done with the operation. For SPI data writes
the predicted time of that operation could be less than 10us.
The current per loop delay of 500us is adding too much delay.
This change replaces the delay(x) in the do-while loop with a
timer so that the actual timeout value won't be lengthened by the
delay of reading the SPI device.
Change-Id: Ia8b00879135f926c402bbd9d08953c77a2dcc84e
Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com>
---
src/drivers/spi/spi_flash.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c
index 33588d5..6d92836 100644
--- a/src/drivers/spi/spi_flash.c
+++ b/src/drivers/spi/spi_flash.c
@@ -16,6 +16,7 @@
#include <cpu/x86/smm.h>
#endif
#include "spi_flash_internal.h"
+#include <timer.h>
static void spi_flash_addr(u32 addr, u8 *cmd)
{
@@ -106,27 +107,24 @@ int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout,
u8 cmd, u8 poll_bit)
{
struct spi_slave *spi = flash->spi;
- unsigned long timebase;
int ret;
u8 status;
+ struct mono_time current, end;
+
+ timer_monotonic_get(¤t);
+ end = current;
+ mono_time_add_msecs(&end, timeout);
- timebase = timeout;
do {
ret = spi_flash_cmd_read(spi, &cmd, 1, &status, 1);
if (ret)
return -1;
-
if ((status & poll_bit) == 0)
- break;
-
- udelay(500);
- } while (timebase--);
-
- if ((status & poll_bit) == 0)
- return 0;
+ return 0;
+ timer_monotonic_get(¤t);
+ } while (!mono_time_after(¤t, &end));
- /* Timed out */
- printk(BIOS_DEBUG, "SF: time out!\n");
+ printk(BIOS_DEBUG, "SF: timeout at %ld msec\n",timeout);
return -1;
}
Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6106
-gerrit
commit 28c204e8c2f1728fe37d02921b16bc39982f7059
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Wed Jun 25 10:13:22 2014 -0600
bayleybay_fsp: Switch from EHCI controller to XHCI
- Disable the EHCI controller and enable the XHCI controller.
SeaBIOS has been tested on the board and boots an OS from a
flashdrive at SuperSpeed.
This also enables the top USB port on the 2-port stack, which goes
through a High Speed Inter-Chip port. The HSIC port is only enabled
through the XHCI device.
Change-Id: Ic3dfc55028fa5e081a30819fe9596b1a9f57fd9c
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/mainboard/intel/bayleybay_fsp/devicetree.cb | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
index 1bde834..befd3dc 100644
--- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb
+++ b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
@@ -50,7 +50,7 @@ chip soc/intel/fsp_baytrail
device pci 11.0 on end # 8086 0F15 - SDIO Port (SD2 pins)
device pci 12.0 on end # 8086 0F16 - SD Port (SD3 pins)
device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23)
- device pci 14.0 off end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
+ device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
device pci 15.0 off end # 8086 0F28 - LP Engine Audio
device pci 16.0 off end # 8086 0F37 - OTG controller
device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
@@ -68,7 +68,7 @@ chip soc/intel/fsp_baytrail
device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (half mini pcie slot)
device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (front x1 slot)
device pci 1c.3 on end # 8086 0F4E - PCIe Root Port 4 (rear x1 slot)
- device pci 1d.0 on end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
+ device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
device pci 1e.0 on end # 8086 0F06 - SIO - DMA
device pci 1e.1 on end # 8086 0F08 - PWM 1
device pci 1e.2 on end # 8086 0F09 - PWM 2
Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6106
-gerrit
commit c02154856d79821c5f57029d8a162caa65eb80d5
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Wed Jun 25 10:13:22 2014 -0600
bayleybay_fsp: Switch from EHCI controller to EHCI
- Disable the EHCI controller and enable the XHCI controller.
SeaBIOS has been tested on the board and boots from a flashdrive at
SuperSpeed.
This also enables the top USB port on the 2-port stack, which goes
through a High Speed Inter-Chip port. The HSIC port is only enabled
through the XHCI device.
Change-Id: Ic3dfc55028fa5e081a30819fe9596b1a9f57fd9c
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/mainboard/intel/bayleybay_fsp/devicetree.cb | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
index 1bde834..befd3dc 100644
--- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb
+++ b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
@@ -50,7 +50,7 @@ chip soc/intel/fsp_baytrail
device pci 11.0 on end # 8086 0F15 - SDIO Port (SD2 pins)
device pci 12.0 on end # 8086 0F16 - SD Port (SD3 pins)
device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23)
- device pci 14.0 off end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
+ device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
device pci 15.0 off end # 8086 0F28 - LP Engine Audio
device pci 16.0 off end # 8086 0F37 - OTG controller
device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
@@ -68,7 +68,7 @@ chip soc/intel/fsp_baytrail
device pci 1c.1 on end # 8086 0F4A - PCIe Root Port 2 (half mini pcie slot)
device pci 1c.2 on end # 8086 0F4C - PCIe Root Port 3 (front x1 slot)
device pci 1c.3 on end # 8086 0F4E - PCIe Root Port 4 (rear x1 slot)
- device pci 1d.0 on end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
+ device pci 1d.0 off end # 8086 0F34 - USB EHCI - Only 1 USB controller at a time
device pci 1e.0 on end # 8086 0F06 - SIO - DMA
device pci 1e.1 on end # 8086 0F08 - PWM 1
device pci 1e.2 on end # 8086 0F09 - PWM 2
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6103
-gerrit
commit f1d54bcf11922059ad1dba5f8ad99753c64d41ed
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Tue Jun 24 17:35:02 2014 +1000
include/device/device.h: Header is ROMCC tentative
This header is incompatible with ROMCC and its inclusion leads to 'odd'
build failures.
Change-Id: If31d774385796dcafe2fd48151e424b4c872aec3
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/include/device/device.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/include/device/device.h b/src/include/device/device.h
index dcd93f6..ced2786 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -1,6 +1,13 @@
#ifndef DEVICE_H
#define DEVICE_H
+/*
+ * NOTICE: Header is ROMCC tentative.
+ * This header is incompatible with ROMCC and its inclusion leads to 'odd'
+ * build failures.
+ */
+#if !defined(__ROMCC__)
+
#include <stdint.h>
#include <stddef.h>
#include <rules.h>
@@ -243,4 +250,6 @@ ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus,
#endif
+#endif /* !defined(__ROMCC__) */
+
#endif /* DEVICE_H */
the following patch was just integrated into master:
commit e3c65b97b4bdd9a5ba90f03e74c02d7d3c9e1856
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Fri Jun 13 11:07:34 2014 +0300
gm45 boards: Switch to use DYNAMIC_CBMEM
Change-Id: Id19d31a2d114bb796b31ad61802d40c8608e4020
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6038
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless(a)gmail.com>
See http://review.coreboot.org/6038 for details.
-gerrit