the following patch was just integrated into master:
commit 61680274c1ded5ea095b15b689f83d5d670d2aae
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon May 5 12:42:35 2014 -0500
broadwell: ACPI, romstage, and other updates
broadwell: Add romstage usbdebug support
Reviewed-on: https://chromium-review.googlesource.com/199412
(cherry picked from commit 1050e7d3be6ec1e4fe5aa2df408f4bb6d33a42b5)
broadwell: Add romstage code to configure PCH UART for console
Reviewed-on: https://chromium-review.googlesource.com/199807
(cherry picked from commit ecebda4eb5d6fe58473d25c2898ba1a2eac0f39a)
broadwell: Expand the PCI device convenience macros
Reviewed-on: https://chromium-review.googlesource.com/199891
(cherry picked from commit f8c54c70f136cd2cb8f977bc25661974d7e529ad)
broadwell: Add ramstage driver for ADSP
Reviewed-on: https://chromium-review.googlesource.com/199892
(cherry picked from commit e8e986b0ba52bbfc9923d71009fbd31e749ca43f)
broadwell: Update ACPI devices
Reviewed-on: https://chromium-review.googlesource.com/201080
(cherry picked from commit 2446b35578eb36e0009415bec340059135751549)
broadwell: Reserve DPR region
Reviewed-on: https://chromium-review.googlesource.com/201081
(cherry picked from commit 8ecd9d2096db2bded6f27ef6ee9a9b39ce2dfec6)
broadwell: Remove old pei_data and add cpu function for romstage
Reviewed-on: https://chromium-review.googlesource.com/201690
(cherry picked from commit d206c9cdd69519d502a90bb0595f0e3a7cb50274)
broadwell: Fixes for graphics without executing VBIOS
Reviewed-on: https://chromium-review.googlesource.com/202356
(cherry picked from commit 0c031df1ce92c875e95ddfd3f026f649c342c7fa)
broadwell: Fix compilation failure when loglevel is lowered
Reviewed-on: https://chromium-review.googlesource.com/202357
(cherry picked from commit 708ce78b2bfae5664b1238e17b086c88cac55bdc)
broadwell: Disable GPIO controller interrupt
Reviewed-on: https://chromium-review.googlesource.com/203645
(cherry picked from commit 2d17e98eded5958258ba5c0abf600284d8d03af9)
broadwell: Add support for E0 stepping
Reviewed-on: https://chromium-review.googlesource.com/205160
(cherry picked from commit 802e9d371418cc7a7fc7af131d7e5dda0ae5b273)
broadwell: misc updates for CPU driver
Reviewed-on: https://chromium-review.googlesource.com/205161
(cherry picked from commit ea1d403817ee193648f2c119fd45894e32e57e97)
broadwell: Read power state earlier and store in romstage params
Reviewed-on: https://chromium-review.googlesource.com/208151
(cherry picked from commit b2198d71084ad3c1360a0bfedc46c8dd3825bd0e)
broadwell: Add parameters to pei_data structure
Reviewed-on: https://chromium-review.googlesource.com/208153
(cherry picked from commit 423fbf67e497a907fbc8e12caf2929d4951858af)
broadwell: Move platform report output after power state is read
Reviewed-on: https://chromium-review.googlesource.com/208213
(cherry picked from commit acedf4146bf9377133433046dae1fa9c8bc69d78)
Squashed 15 commits for broadwell support.
Change-Id: I87e320d3d5376b84dd9c146b0b833e5ce53244aa
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6982
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
See http://review.coreboot.org/6982 for details.
-gerrit
the following patch was just integrated into master:
commit e256295218266325a77e8b6a207e71bedd9a9359
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu May 1 09:07:53 2014 -0700
broadwell: Update D0 microcode to FFFF000E
New microcode released this week.
Change-Id: I426d0e00d1c03650049cbe033b53a909a7d944c9
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198896
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit 63ec6438b566d14a2b878474ca068cf70d9aa9d6)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6966
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
See http://review.coreboot.org/6966 for details.
-gerrit
the following patch was just integrated into master:
commit 842bcd3c723796ca9392b9e561f138f94b1bfb2b
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu May 1 09:07:53 2014 -0700
broadwell: Update microcode for supported CPUs
This broadwell implementation will support Haswell ULT in
addition to broadwell CPUs. Add the latest available microcode
for the broadwell C0 and D0 parts as well as Haswell ULT.
Change-Id: I1beb71e0e28af3508e2260751b6fdfe47d53d90d
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198742
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit 69d5b7c834a4f52656ab14562ea913477418e588)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6965
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
See http://review.coreboot.org/6965 for details.
-gerrit
the following patch was just integrated into master:
commit f0aaa29989f4de7258430715d64c6d465fb0c457
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Apr 22 10:48:29 2014 -0700
baytrail: Move HDA verb table to Intel SOC common directory
This is common code for Intel SOC that can be shared.
Change-Id: Ic703f36f56a8238d5cc1248b353d8c3a49827a9a
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/196264
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit 3a9057b9616c54a8404eee55511743d2492dbc28)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6968
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
See http://review.coreboot.org/6968 for details.
-gerrit
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6230
-gerrit
commit b0f99098ce3def4a677cef601644d73639e8b0f5
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Wed Jul 9 18:41:12 2014 +1000
include/device/device.h: Duplicate '*_pnp_devfn_t' typedefs
'pci_devfn_t' and 'pnp_devfn_t' are already defined in arch/io.h
Change-Id: I006182bf6933fae21fe6671659b76e7031e74b71
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/arch/x86/include/arch/io.h | 9 ++++++---
src/include/device/device.h | 2 --
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index b6d82f9..d5cdf35 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -4,6 +4,11 @@
#include <stdint.h>
#include <rules.h>
+/* FIXME: Sources for romstage still use device_t. */
+/* Use pci_devfn_t or pnp_devfn_t instead */
+typedef u32 pci_devfn_t;
+typedef u32 pnp_devfn_t;
+
/*
* This file contains the definitions for the x86 IO instructions
* inb/inw/inl/outb/outw/outl and the "string versions" of the same
@@ -218,11 +223,9 @@ static inline int log2f(int value)
#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
/* FIXME: Sources for romstage still use device_t. */
+/* Use pci_devfn_t or pnp_devfn_t instead */
typedef u32 device_t;
-typedef u32 pci_devfn_t;
-typedef u32 pnp_devfn_t;
-
/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
* We don't need to set %fs, and %gs anymore
* Before that We need to use %gs, and leave %fs to other RAM access
diff --git a/src/include/device/device.h b/src/include/device/device.h
index cf4cb8c..3810716 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -18,8 +18,6 @@ struct device;
#ifndef __SIMPLE_DEVICE__
typedef struct device * device_t;
-typedef u32 pci_devfn_t;
-typedef u32 pnp_devfn_t;
struct pci_operations;
struct pci_bus_operations;
struct smbus_bus_operations;
the following patch was just integrated into master:
commit d8c4f2b72462f60ae92a59a976437c2407ec6654
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Apr 22 10:46:06 2014 -0700
baytrail: Move MRC cache code to a common directory
This common code can be shared across Intel SOCs.
Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/196263
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6967
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
See http://review.coreboot.org/6967 for details.
-gerrit
the following patch was just integrated into master:
commit 3511023f341b4416ea61558bd5ecfa2ea8416782
Author: Kein Yuan <kein.yuan(a)intel.com>
Date: Sat Feb 22 12:26:55 2014 -0800
baytrail/rambi: S3 support and other updates
baytrail: Change all GPIO related pull resistors from 10K to 20K
Reviewed-on: https://chromium-review.googlesource.com/187570
(cherry picked from commit 762e99861dd1ae61ddcf1ebdec8e698ede54405e)
baytrail: workaround kernel using serial console on resume
Reviewed-on: https://chromium-review.googlesource.com/188011
(cherry picked from commit b0da3bdb5b6b417ad6cab0084359d4eae1cb4469)
baytrail: allow dirty cache line evictions for SMRAM to stick
Reviewed-on: https://chromium-review.googlesource.com/188015
(cherry picked from commit 50fb1e6a844e1db05574c92625da23777ad7a0ca)
baytrail: Optionally pull up TDO and TMS to avoid power loss in S3.
Reviewed-on: https://chromium-review.googlesource.com/188260
(cherry picked from commit e240856609b4eed5ed44ec4e021ed385965768d6)
rambi: always load option rom
Reviewed-on: https://chromium-review.googlesource.com/188721
(cherry picked from commit d8a1d108548d20755f8683497c215e76d513b7a9)
baytrail: use new chromeos ram oops API
Reviewed-on: https://chromium-review.googlesource.com/186394
(cherry picked from commit f38e6969df9b5453b10d49be60b5d033d38b4594)
rambi: always show dev/rec screens on eDP connected panel
Reviewed-on: https://chromium-review.googlesource.com/188731
(cherry picked from commit 7d8570ac52f68492a2250fa536d55f7cbbd9ef95)
baytrail: stop e820 reserving default SMM region
Reviewed-on: https://chromium-review.googlesource.com/189084
(cherry picked from commit 6fce823512f5db5a09a9c89048334c3524c69a24)
baytrai: update MRC wrapper header
Reviewed-on: https://chromium-review.googlesource.com/189196
(cherry picked from commit 36b33a25b6603b6a74990b00d981226440b68970)
rambi: Put LPE device into ACPI mode
Reviewed-on: https://chromium-review.googlesource.com/189371
(cherry picked from commit 5955350cd57fd1b3732b6db62911d824712a5413)
baytrail: DPTF: Enable mainboard-specific PPCC
Reviewed-on: https://chromium-review.googlesource.com/189576
(cherry picked from commit 27fae3e670244b529b7c0241742fc2b55d52c612)
baytrail: Add config option for PCIe wake
Reviewed-on: https://chromium-review.googlesource.com/189994
(cherry picked from commit 1cc31a7c021ec84311f1d4e89dd3e57ca8801ab5)
rambi: Enable PCIe wake
Reviewed-on: https://chromium-review.googlesource.com/189995
(cherry picked from commit c98ae1fee54cfb2b3d3c21a19cdbbf56a0bfa1e6)
Squashed 13 commits for baytrail/rambi.
Change-Id: I153ef5a43e2bede05cfd624f53e24a0013fd8fb4
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6957
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
See http://review.coreboot.org/6957 for details.
-gerrit
Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7020
-gerrit
commit 01f2f165b47a021130a611570b5f710b1aa2dcb9
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Sun Oct 5 17:09:29 2014 +1100
gigabyte/ga-b75m-d3h: Add new Intel mainboard
This is based on lenovo X230 port. Board boots to payload.
(AHCI/XHCI fixed)
Remaining Issues:
1. Native raminit sometimes fails with "timC write discovery failed"
even without changing the ram configuration.
I suggest altering the native raminit code so that it reboots
if that message appears to give a chance for the boot process to recover.
2. VGA not working yet, even with vga rom captured from running vendor bios.
Change-Id: Ib465a4824ef1a71ab6aa17bd40fc281215c6d44f
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
---
src/cpu/intel/Kconfig | 1 +
src/cpu/intel/Makefile.inc | 1 +
src/cpu/intel/socket_LGA1155/Kconfig | 17 ++
src/cpu/intel/socket_LGA1155/Makefile.inc | 12 +
src/cpu/intel/socket_LGA1155/socket_LGA1155.c | 5 +
src/mainboard/gigabyte/Kconfig | 3 +
src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 75 ++++++
src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc | 21 ++
src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl | 1 +
.../gigabyte/ga-b75m-d3h/acpi/mainboard.asl | 28 +++
.../gigabyte/ga-b75m-d3h/acpi/platform.asl | 73 ++++++
.../ga-b75m-d3h/acpi/sandybridge_pci_irqs.asl | 73 ++++++
.../gigabyte/ga-b75m-d3h/acpi/superio.asl | 24 ++
.../gigabyte/ga-b75m-d3h/acpi/thermal.asl | 65 ++++++
src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl | 43 ++++
src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c | 101 +++++++++
src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt | 6 +
src/mainboard/gigabyte/ga-b75m-d3h/cmos.default | 18 ++
src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout | 167 ++++++++++++++
src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 113 +++++++++
src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl | 54 +++++
src/mainboard/gigabyte/ga-b75m-d3h/fadt.c | 167 ++++++++++++++
src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c | 252 +++++++++++++++++++++
src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c | 83 +++++++
src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c | 109 +++++++++
src/mainboard/gigabyte/ga-b75m-d3h/onboard.h | 33 +++
src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 251 ++++++++++++++++++++
src/mainboard/gigabyte/ga-b75m-d3h/thermal.h | 30 +++
src/northbridge/intel/sandybridge/early_init.c | 1 +
src/southbridge/intel/bd82x6x/sata.c | 4 +
30 files changed, 1831 insertions(+)
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index aa3dd5b..de76e3e 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -33,6 +33,7 @@ source src/cpu/intel/socket_mPGA603/Kconfig
source src/cpu/intel/socket_mPGA604/Kconfig
source src/cpu/intel/socket_PGA370/Kconfig
source src/cpu/intel/socket_441/Kconfig
+source src/cpu/intel/socket_LGA1155/Kconfig
source src/cpu/intel/socket_LGA771/Kconfig
source src/cpu/intel/socket_LGA775/Kconfig
source src/cpu/intel/socket_rPGA988B/Kconfig
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index b6e7268..4295bd7 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -29,6 +29,7 @@ subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2
subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771
subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA1155) += socket_LGA1155
#socket_mPGA604_533Mhz
#socket_mPGA604_800Mhz
diff --git a/src/cpu/intel/socket_LGA1155/Kconfig b/src/cpu/intel/socket_LGA1155/Kconfig
new file mode 100644
index 0000000..bb7d35c
--- /dev/null
+++ b/src/cpu/intel/socket_LGA1155/Kconfig
@@ -0,0 +1,17 @@
+config CPU_INTEL_SOCKET_LGA1155
+ bool
+
+if CPU_INTEL_SOCKET_LGA1155
+
+config SOCKET_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_INTEL_MODEL_206AX
+ select CPU_INTEL_MODEL_306AX
+ select MMX
+ select SSE
+
+config CACHE_MRC_BIN
+ bool
+ default n
+
+endif # CPU_INTEL_SOCKET_LGA1155
diff --git a/src/cpu/intel/socket_LGA1155/Makefile.inc b/src/cpu/intel/socket_LGA1155/Makefile.inc
new file mode 100644
index 0000000..9d234d2
--- /dev/null
+++ b/src/cpu/intel/socket_LGA1155/Makefile.inc
@@ -0,0 +1,12 @@
+ramstage-y += socket_LGA1155.c
+#subdirs-y += ../model_206ax
+#subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+#subdirs-y += ../speedstep
+subdirs-y += ../turbo
+
+####cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc
diff --git a/src/cpu/intel/socket_LGA1155/socket_LGA1155.c b/src/cpu/intel/socket_LGA1155/socket_LGA1155.c
new file mode 100644
index 0000000..63c925d
--- /dev/null
+++ b/src/cpu/intel/socket_LGA1155/socket_LGA1155.c
@@ -0,0 +1,5 @@
+#include <device/device.h>
+
+struct chip_operations cpu_intel_socket_LGA1155_ops = {
+ CHIP_NAME("Socket LGA1155 CPU")
+};
diff --git a/src/mainboard/gigabyte/Kconfig b/src/mainboard/gigabyte/Kconfig
index ff96a17..c46b979 100644
--- a/src/mainboard/gigabyte/Kconfig
+++ b/src/mainboard/gigabyte/Kconfig
@@ -27,6 +27,8 @@ config BOARD_GIGABYTE_GA_6BXC
bool "GA-6BXC"
config BOARD_GIGABYTE_GA_6BXE
bool "GA-6BXE"
+config BOARD_GIGABYTE_GA_B75M_D3H
+ bool "GA-B75M-D3H"
config BOARD_GIGABYTE_M57SLI
bool "GA-M57SLI-S4"
config BOARD_GIGABYTE_MA785GMT
@@ -41,6 +43,7 @@ endchoice
source "src/mainboard/gigabyte/ga_2761gxdk/Kconfig"
source "src/mainboard/gigabyte/ga-6bxc/Kconfig"
source "src/mainboard/gigabyte/ga-6bxe/Kconfig"
+source "src/mainboard/gigabyte/ga-b75m-d3h/Kconfig"
source "src/mainboard/gigabyte/m57sli/Kconfig"
source "src/mainboard/gigabyte/ma785gmt/Kconfig"
source "src/mainboard/gigabyte/ma785gm/Kconfig"
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig
new file mode 100644
index 0000000..0192289
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig
@@ -0,0 +1,75 @@
+if BOARD_GIGABYTE_GA_B75M_D3H
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_LGA1155
+ select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
+ select SOUTHBRIDGE_INTEL_C216
+ select SUPERIO_ITE_IT8728F
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select HAVE_ACPI_RESUME
+ select HAVE_SMI_HANDLER
+ select INTEL_INT15
+ select VGA
+ select INTEL_EDID
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
+ select IVYBRIDGE_LVDS
+ select UDELAY_TSC
+ select EARLY_CBMEM_INIT
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config USBDEBUG_HCD_INDEX
+ int
+ default 2
+
+config MAINBOARD_DIR
+ string
+ default gigabyte/ga-b75m-d3h
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "GA-B75M-D3H"
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 8
+
+# No need to override the chipset VGA_BIOS_ID.
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0102.rom"
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+config IFD_BIOS_SECTION
+ string
+ default "0x00600000:0x007fffff"
+
+config IFD_ME_SECTION
+ string
+ default "0x00001000:0x004fffff"
+
+# UNCOMMENT BELOW WHEN YOU BUILD WITH REAL ME IMAGE
+#config IFD_GBE_SECTION
+# string
+# default "0x00fff000:0x00000fff"
+
+endif # BOARD_GIGABYTE_GA_B75M_D3H
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc
new file mode 100644
index 0000000..6a3d7eb
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
+
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl
new file mode 100644
index 0000000..abd87cb
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl
@@ -0,0 +1 @@
+/* This file is empty */
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl
new file mode 100644
index 0000000..09cff9a
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (\_SB)
+{
+ Device (PWRB)
+ {
+ Name (_HID, EisaId("PNP0C0C"))
+ }
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl
new file mode 100644
index 0000000..1448aeb
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/sandybridge_pci_irqs.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..7ce8cd8
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },
+ // XHCI 0:14.0
+ Package() { 0x0014ffff, 0, 0, 19 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 16 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 19 },
+ Package() { 0x001cffff, 1, 0, 20 },
+ Package() { 0x001cffff, 2, 0, 17 },
+ Package() { 0x001cffff, 3, 0, 18 },
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, 0, 19 },
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, 0, 21 },
+ // LPC devices 0:1f.0
+ Package() { 0x001fffff, 0, 0, 17 },
+ Package() { 0x001fffff, 1, 0, 23 },
+ Package() { 0x001fffff, 2, 0, 16 },
+ Package() { 0x001fffff, 3, 0, 18 },
+ })
+ } Else {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // XHCI 0:14.0
+ Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+ })
+ }
+}
+
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl
new file mode 100644
index 0000000..753fc29
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* mainboard configuration */
+
+#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
+#define SIO_ENABLE_PS2M // Enable PS/2 Mouse
+
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl
new file mode 100644
index 0000000..f71611a
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+ ThermalZone (THRM)
+ {
+ Name (_TC1, 0x02)
+ Name (_TC2, 0x03)
+
+ // Thermal zone polling frequency: 10 seconds
+ Name (_TZP, 100)
+
+ // Thermal sampling period for passive cooling: 10 seconds
+ Name (_TSP, 100)
+
+ // Convert from Degrees C to 1/10 Kelvin for ACPI
+ Method (CTOK, 1)
+ {
+ // 10th of Degrees C
+ Multiply (Arg0, 10, Local0)
+
+ // Convert to Kelvin
+ Add (Local0, 2732, Local0)
+
+ Return (Local0)
+ }
+
+ // Threshold for OS to shutdown
+ Method (_CRT, 0, Serialized)
+ {
+ Return (CTOK (\TCRT))
+ }
+
+ // Threshold for passive cooling
+ Method (_PSV, 0, Serialized)
+ {
+ Return (CTOK (\TPSV))
+ }
+
+ // Processors used for passive cooling
+ Method (_PSL, 0, Serialized)
+ {
+ Return (\PPKG ())
+ }
+ }
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl
new file mode 100644
index 0000000..3ececa9
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+ // TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+ // TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
new file mode 100644
index 0000000..fd55bc3
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include "thermal.h"
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+}
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->pcnt = dev_count_cpu();
+
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* IGD Displays */
+ gnvs->ndid = 3;
+ gnvs->did[0] = 0x80000100;
+ gnvs->did[1] = 0x80000240;
+ gnvs->did[2] = 0x80000410;
+ gnvs->did[3] = 0x80000410;
+ gnvs->did[4] = 0x00000005;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ acpi_update_thermal_table(gnvs);
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+ return current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt
new file mode 100644
index 0000000..312f6ef
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4150#sp
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default
new file mode 100644
index 0000000..137f482
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default
@@ -0,0 +1,18 @@
+boot_option=Fallback
+last_boot=Fallback
+baud_rate=115200
+debug_level=Spew
+power_on_after_fail=Enable
+nmi=Enable
+volume=0x3
+first_battery=Primary
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+touchpad=Enable
+sata_mode=AHCI
+fn_ctrl_swap=Disable
+sticky_fn=Disable
+trackpoint=Enable
+hyper_threading=Enable
+backlight=Both
\ No newline at end of file
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout
new file mode 100644
index 0000000..7a2eb01
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout
@@ -0,0 +1,167 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+400 8 h 0 volume
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+
+# coreboot config options: EC
+411 1 e 8 first_battery
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 touchpad
+415 1 e 1 wlan
+416 1 e 1 trackpoint
+417 1 e 1 fn_ctrl_swap
+418 1 e 1 sticky_fn
+#419 2 r 0 unused
+421 1 e 9 sata_mode
+422 2 e 10 backlight
+
+# coreboot config options: cpu
+424 1 e 2 hyper_threading
+#425 7 r 0 unused
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+#435 549 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+8 0 Secondary
+8 1 Primary
+9 0 AHCI
+9 1 Compatible
+10 0 Both
+10 1 Keyboard only
+10 2 Thinklight only
+10 3 None
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
new file mode 100644
index 0000000..8484df6
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
@@ -0,0 +1,113 @@
+chip northbridge/intel/sandybridge
+
+ # Enable DVI Hotplug with 6ms pulse
+ register "gpu_dp_b_hotplug" = "0x06"
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_LGA1155
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1458 0x5000 inherit
+ device pci 00.0 on end # host bridge
+ device pci 01.0 off end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # vga controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
+ #register "pirqa_routing" = "0x8b"
+ #register "pirqb_routing" = "0x8a"
+ #register "pirqc_routing" = "0x8b"
+ #register "pirqd_routing" = "0x8b"
+ #register "pirqe_routing" = "0x80"
+ #register "pirqf_routing" = "0x80"
+ #register "pirqg_routing" = "0x80"
+ #register "pirqh_routing" = "0x80"
+
+ # GPI routing
+ register "alt_gp_smi_en" = "0x0000"
+ register "gpi0_routing" = "0"
+ register "gpi1_routing" = "0"
+ register "gpi2_routing" = "0"
+ register "gpi3_routing" = "0"
+ register "gpi4_routing" = "0"
+ register "gpi5_routing" = "0"
+ register "gpi6_routing" = "0"
+ register "gpi7_routing" = "0"
+ register "gpi8_routing" = "0"
+ register "gpi9_routing" = "0"
+ register "gpi10_routing" = "0"
+ register "gpi11_routing" = "0"
+ register "gpi12_routing" = "0"
+ register "gpi13_routing" = "0"
+ register "gpi14_routing" = "0"
+ register "gpi15_routing" = "0"
+
+ # Set max SATA speed to 6.0 Gb/s
+ register "sata_port_map" = "0x3f"
+ register "sata_interface_speed_support" = "0x3"
+ register "gen1_dec" = "0x003c0a01"
+ register "gen2_dec" = "0x00000000"
+ register "gen3_dec" = "0x00000000"
+
+ # Enable zero-based linear PCIe root port functions
+ register "pcie_port_coalesce" = "1"
+
+ device pci 14.0 off end # USB 3.0 Controller
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 on end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 on end # PCI bridge (ethernet here)
+ device pci 1f.0 on # ISA/LPC bridge
+ chip superio/ite/it8728f
+ device pnp 2e.0 off end # FDC
+ device pnp 2e.1 on # Serial Port 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.4 on # Environment Controller
+ io 0x60 = 0xa30
+ io 0x62 = 0xa20
+ irq 0x70 = 9
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x0
+ io 0x62 = 0xa00
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 on # Mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.a off end # IR
+ end
+ end
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 on end # Thermal
+ end
+ end
+end
+
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
new file mode 100644
index 0000000..3209963
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include "acpi/mainboard.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ #include "acpi/thermal.asl"
+
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/fadt.c b/src/mainboard/gigabyte/ga-b75m-d3h/fadt.c
new file mode 100644
index 0000000..8104d22
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/fadt.c
@@ -0,0 +1,167 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+#include <cpu/x86/smm.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+#define APM_CNT 0xb2
+#define CST_CONTROL 0x85
+#define PST_CONTROL 0x80
+#define ACPI_DISABLE 0x1e
+#define ACPI_ENABLE 0xe1
+#define GNVS_UPDATE 0xea
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
+ 0x40) & 0xfffe;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, "CORE", 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_DESKTOP;
+
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = ACPI_ENABLE;
+ fadt->acpi_disable = ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x20;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 16;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = 87;
+ fadt->flush_size = 1024;
+ fadt->flush_stride = 16;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 0;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
+ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0;
+
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 64;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c
new file mode 100644
index 0000000..29f8a45
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c
@@ -0,0 +1,252 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Vendor Name : IDT
+ * Vendor ID : 0x10ec0269
+ * Subsystem ID : 0x17aa21fa
+ * Revision ID : 0x100303
+ */
+
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC
+ 0x17aa21fa, // Subsystem ID
+ 0x0000007d, // Number of 4 dword sets
+
+/* Bits 31:28 - Codec Address */
+/* Bits 27:20 - NID */
+/* Bits 19:8 - Verb ID */
+/* Bits 7:0 - Payload */
+
+/* NID 0x01 - NodeInfo */
+ AZALIA_SUBVENDOR(0x0, 0x17AA21FA),
+
+/* NID 0x0A - External Microphone Connector
+ * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq)
+ */
+ AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020),
+
+/* NID 0x0B - Headphone Connector
+ * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq)
+ */
+ AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F),
+
+/* NID 0x0C - Not connected
+ * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq)
+ */
+ AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0),
+
+/* NID 0x0D - Internal Speakers
+ * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq)
+ */
+ AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110),
+
+/* NID 0x0F - Not connected
+ * Config=0x40F000F0
+ */
+ AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0),
+
+/* NID 0x11 - Internal Microphone
+ * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq)
+ */
+ AZALIA_PIN_CFG(0x0, 0x11, 0xD5A30140),
+ AZALIA_PIN_CFG(0x0, 0x12, 0x90A60140),
+ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
+ AZALIA_PIN_CFG(0x0, 0x15, 0x03211020),
+ AZALIA_PIN_CFG(0x0, 0x18, 0x03A11830),
+ AZALIA_PIN_CFG(0x0, 0x19, 0x411111F0),
+
+ 0x01970804,
+ 0x01870803,
+ 0x01470740,
+ 0x00970600,
+
+ 0x00370600,
+ 0x00270600,
+ 0x00270600,
+ 0x00270600,
+
+ AZALIA_PIN_CFG(0x0, 0x1A, 0x411111F0),
+ AZALIA_PIN_CFG(0x0, 0x1D, 0x40138205),
+ AZALIA_PIN_CFG(0x0, 0x1E, 0x411111F0),
+
+ /*
+ * Hardware EQ Parameters
+ * Sample Rate 88200
+ */
+ 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F,
+ 0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80,
+ 0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981,
+ 0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80,
+ 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F,
+ 0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80,
+ 0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E,
+ 0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80,
+ 0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1,
+ 0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80,
+ 0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E,
+ 0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80,
+ 0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983,
+ 0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80,
+ 0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D,
+ 0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80,
+ 0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C,
+ 0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80,
+ 0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3,
+ 0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80,
+ 0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F,
+ 0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80,
+ 0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982,
+ 0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80,
+ 0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E,
+ 0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80,
+ 0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D,
+ 0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80,
+ 0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2,
+ 0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80,
+ 0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F,
+ 0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80,
+ 0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E,
+ 0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80,
+ 0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937,
+ 0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80,
+ 0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971,
+ 0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80,
+ 0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9,
+ 0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80,
+ 0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942,
+ 0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80,
+ 0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C,
+ 0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80,
+ 0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934,
+ 0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80,
+ 0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963,
+ 0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80,
+ 0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9,
+ 0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80,
+ 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940,
+ 0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80,
+
+ /*
+ * Hardware EQ Parameters
+ * Sample Rate 96000
+ */
+ 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F,
+ 0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80,
+ 0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981,
+ 0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80,
+ 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F,
+ 0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80,
+ 0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E,
+ 0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80,
+ 0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1,
+ 0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80,
+ 0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E,
+ 0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80,
+ 0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983,
+ 0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80,
+ 0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D,
+ 0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80,
+ 0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C,
+ 0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80,
+ 0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3,
+ 0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80,
+ 0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F,
+ 0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80,
+ 0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982,
+ 0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80,
+ 0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E,
+ 0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80,
+ 0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D,
+ 0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80,
+ 0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1,
+ 0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80,
+ 0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F,
+ 0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80,
+ 0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D,
+ 0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80,
+ 0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938,
+ 0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80,
+ 0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972,
+ 0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80,
+ 0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8,
+ 0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80,
+ 0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941,
+ 0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80,
+ 0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999,
+ 0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80,
+ 0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934,
+ 0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80,
+ 0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966,
+ 0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80,
+ 0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9,
+ 0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80,
+ 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940,
+ 0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80,
+
+ /* SAFEDSP Parameters */
+ 0x022782C1, 0x02277127, 0x02277227, 0x02278801,
+ 0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14,
+ 0x02278B0F, 0x0017B008,
+
+ /* Misc entries */
+ 0x00B707C0, /* Enable PortB as Output with HP amp */
+ 0x00D70740, /* Enable PortD as Output */
+ 0x0017A200, /* Disable ClkEn of PortSenseTst */
+ 0x0017C621, /* Slave Port - Port A used as microphone input for
+ combo Jack
+ Master Port - Port B used for Jack Presence Detect
+ Enable Combo Jack Detection */
+ 0x0017A208, /* Enable ClkEn of PortSenseTst */
+ 0x00170500, /* Set power state to D0 */
+
+ /* --- Next Codec --- */
+
+/* Vendor Name : Intel
+ * Vendor ID : 0x80862806
+ * Subsystem ID : 0x80860101
+ * Revision ID : 0x100000
+ */
+ /* coreboot specific header */
+ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI
+ 0x80860101, // Subsystem ID
+ 0x00000004, // Number of IDs
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+ AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+ /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
+
+ /* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
+
+ /* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030)
+};
+
+const u32 pc_beep_verbs[] = {
+ 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
new file mode 100644
index 0000000..62b437b
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011-2012 Google Inc.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <drivers/intel/gma/int15.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <smbios.h>
+#include <device/pci.h>
+#include <cbfs.h>
+#include <pc80/keyboard.h>
+#include <ec/lenovo/h8/h8.h>
+#include <build.h>
+
+void mainboard_suspend_resume(void)
+{
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+}
+
+const char *smbios_mainboard_bios_version(void)
+{
+ /* Satisfy thinkpad_acpi. */
+ if (strlen(CONFIG_LOCALVERSION))
+ return "CBET4000 " CONFIG_LOCALVERSION;
+ else
+ return "CBET4000 " COREBOOT_VERSION;
+}
+
+
+
+static void mainboard_init(device_t dev)
+{
+ RCBA32(0x38c8) = 0x00002005;
+ RCBA32(0x38c4) = 0x00802005;
+ RCBA32(0x38c0) = 0x00000007;
+
+ /* This sneaked in here, because X201 SuperIO chip isn't really
+ connected to anything and hence we don't init it.
+ */
+ pc_keyboard_init();
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c
new file mode 100644
index 0000000..9f8a29f
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <pc80/mc146818rtc.h>
+#include <delay.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ switch (smif) {
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 1
+ * On failure, the IO Trap Handler returns a value != 1 */
+ return 1;
+}
+
+void mainboard_smi_gpi(u32 gpi_sts)
+{
+
+}
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 data)
+{
+ u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+
+ printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
+ data);
+
+ if (!pmbase)
+ return 0;
+
+ switch (data) {
+ case APM_CNT_ACPI_ENABLE:
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ break;
+ case APM_CNT_FINALIZE:
+ printk(BIOS_DEBUG, "APMC: FINALIZE\n");
+ if (mainboard_finalized) {
+ printk(BIOS_DEBUG, "APMC#: Already finalized\n");
+ return 0;
+ }
+
+ intel_me_finalize_smm();
+ intel_pch_finalize_smm();
+ intel_sandybridge_finalize_smm();
+ intel_model_206ax_finalize_smm();
+
+ mainboard_finalized = 1;
+ break;
+
+ default:
+ break;
+ }
+ return 0;
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h b/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h
new file mode 100644
index 0000000..0580945
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef GAB75MD3V_ONBOARD_H
+#define GAB75MD3V_ONBOARD_H
+
+#include <arch/smp/mpspec.h>
+
+#define GAB75MD3V_NIC_VENDOR_ID 0x10EC
+#define GAB75MD3V_NIC_DEVICE_ID 0x8168
+
+#define XHCI_MODE 2 // Auto
+#define XHCI_PORTS 3 // Port 0 & 1
+#define XHCI_PREBOOT 0 // No PreOS boot support
+#define XHCI_STREAMS 1 // Sure, lets have streams
+
+#endif
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
new file mode 100644
index 0000000..cc108fb
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -0,0 +1,251 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define SUPERIO_BASE 0x2e
+#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0)
+#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
+#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/early_variables.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <delay.h>
+#include <superio/ite/it8728f/it8728f.h>
+#include <superio/ite/common/ite.h>
+#include "southbridge/intel/bd82x6x/me.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit_native.h"
+#include <arch/cpu.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include <cbfs.h>
+#include "onboard.h"
+#include <cpu/intel/romstage.h>
+
+/*
+ * Mainboard specific superio IT8728F settings
+ */
+static void it8728f_b75md3v_conf(device_t dev)
+{
+ ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16
+ ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34
+ ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port
+ ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00
+ ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear!
+ ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in
+ ite_reg_write(dev, 0xe9, 0x21); // bus select disable
+ ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12)
+}
+
+static void it8728f_b75md3v_disable_reboot(device_t dev)
+{
+ ite_reg_write(dev, 0xEF, 0x7E);
+}
+
+static void pch_enable_lpc(void)
+{
+ /*
+ * Enable:
+ * EC Decode Range PortA30/A20
+ * SuperIO Port2E/2F
+ * PS/2 Keyboard/Mouse Port60/64
+ * FDD Port3F0h-3F5h and Port3F7h
+ */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+ CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
+}
+
+void main(unsigned long bist)
+{
+ int boot_mode = 0;
+ u32 pm1_cnt;
+ u16 pm1_sts;
+ spd_raw_data spd[4];
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ tsc_t start_romstage_time;
+ tsc_t before_dram_time;
+ tsc_t after_dram_time;
+ tsc_t base_time = {
+ .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+ .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+ };
+#endif
+#if CONFIG_COLLECT_TIMESTAMPS
+ start_romstage_time = rdtsc();
+#endif
+
+ if (bist == 0)
+ enable_lapic();
+
+ pch_enable_lpc();
+
+ /* Initialize SuperIO */
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ it8728f_b75md3v_disable_reboot(SUPERIO_GPIO);
+
+ /* Initialize console device(s) */
+ console_init();
+ printk(BIOS_EMERG, "START:\n");
+
+ /* Finish setting up SuperIO */
+ it8728f_b75md3v_conf(PNP_DEV(SUPERIO_BASE, IT8728F_GPIO));
+
+ printk(BIOS_EMERG, "Fixed SuperIO\n");
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ printk(BIOS_EMERG, "BIST was ok\n");
+
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ printk(BIOS_EMERG, "soft reset detected\n");
+ boot_mode = 1;
+
+ /* System is not happy after keyboard reset... */
+ printk(BIOS_EMERG, "Issuing CF9 warm reset\n");
+ outb(0x6, 0xcf9);
+ hlt();
+ }
+
+ printk(BIOS_EMERG, "CAFE passed\n");
+
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+ sandybridge_early_initialization(SANDYBRIDGE_DESKTOP);
+ printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
+
+ /* Check PM1_STS[15] to see if we are waking from Sx */
+ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+ /* Read PM1_CNT[12:10] to determine which Sx state */
+ pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+
+ post_code(0x38);
+ /* Enable SPD ROMs and DDR-III DRAM */
+ enable_smbus();
+
+ /* Prepare USB controller early in S3 resume */
+ if (boot_mode == 2)
+ enable_usb_bar();
+
+ post_code(0x39);
+
+ post_code(0x3a);
+
+ ///* Enable PCH GPIOs */
+ //pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+ //pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+ //setup_pch_gpios(&b75md3v_gpio_map);
+
+ //printk(BIOS_EMERG, "Setup PCH GPIOs successful\n");
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ before_dram_time = rdtsc();
+#endif
+
+ intel_early_me_uma_size();
+ intel_early_me_init();
+
+ printk(BIOS_EMERG, "Custom memory init...\n");
+
+ memset (spd, 0, sizeof (spd));
+ read_spd (&spd[0], 0x50);
+ read_spd (&spd[1], 0x51);
+ read_spd (&spd[2], 0x52);
+ read_spd (&spd[3], 0x53);
+
+ init_dram_ddr3 (spd, 0, TCK_800MHZ, 0);
+
+ printk(BIOS_EMERG, "Back from custom memory init...\n");
+
+ intel_early_me_init_done(0);
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ after_dram_time = rdtsc();
+#endif
+ post_code(0x3b);
+
+ post_code(0x3c);
+
+ post_code(0x3d);
+
+ ram_check_nodie(0xf000000, 0xf010000);
+ post_code(0x3e);
+
+ MCHBAR16(SSKPD) = 0xCAFE;
+#if CONFIG_EARLY_CBMEM_INIT
+ ////cbmem_was_initted = !cbmem_initialize();
+#else
+//// cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram()
+//// - HIGH_MEMORY_SIZE));
+#endif
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* If there is no high memory area, we didn't boot before, so
+ * this is not a resume. In that case we just create the cbmem toc.
+ */
+
+ *(u32 *)CBMEM_BOOT_MODE = 0;
+ *(u32 *)CBMEM_RESUME_BACKUP = 0;
+
+ if ((boot_mode == 2) /*&& cbmem_was_initted*/) {
+ void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+ if (resume_backup_memory) {
+ *(u32 *)CBMEM_BOOT_MODE = boot_mode;
+ *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
+ }
+ /* Magic for S3 resume */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+ } else if (boot_mode == 2) {
+ /* Failed S3 resume, reset to come up cleanly */
+ outb(0x6, 0xcf9);
+ hlt();
+ } else {
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+ }
+#endif
+ post_code(0x3f);
+ printk(BIOS_EMERG, "NICEEE!");
+#if CONFIG_COLLECT_TIMESTAMPS
+ timestamp_init(base_time);
+ timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
+ timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
+ timestamp_add(TS_AFTER_INITRAM, after_dram_time );
+ timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+#if CONFIG_CONSOLE_CBMEM
+ /* Keep this the last thing this function does. */
+ cbmemc_reinit();
+#endif
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h
new file mode 100644
index 0000000..ab24bb1
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef X230_THERMAL_H
+#define X230_THERMAL_H
+
+ /* Temperature which OS will shutdown at */
+ #define CRITICAL_TEMPERATURE 100
+
+ /* Temperature which OS will throttle CPU */
+ #define PASSIVE_TEMPERATURE 90
+
+#endif
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index d1d35db..970c7af 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -96,6 +96,7 @@ static void sandybridge_setup_graphics(void)
case 0x0122: /* GT2 Desktop >=1.3GHz */
case 0x0126: /* GT2 Mobile >=1.3GHz */
case 0x0156: /* IvyBridge */
+ case 0x0162: /* IvyBridge */
case 0x0166: /* IvyBridge */
break;
default:
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index cb5699e..65931e1 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -89,6 +89,10 @@ static void sata_init(struct device *dev)
reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
pci_write_config32(dev, IDE_CONFIG, reg32);
+ /* Set AHCI mode with max 6 ports on first controller */
+ reg16 = 0x0050;
+ pci_write_config16(dev, 0x90, reg16);
+
/* for AHCI, Port Enable is managed in memory mapped space */
reg16 = pci_read_config16(dev, 0x92);
reg16 &= ~0x3f; /* 6 ports SKU + ORM */