Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4794
-gerrit
commit 99ea29dcc3a5781425816bcf7188568523fae890
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sat Jan 25 04:03:35 2014 +0100
lenovo/x60: Move non-raminit config to checksummed area
Some non-raminit config was erroneously put to non-checksummed
non-restored area. Put it to right place.
Change-Id: If907bd771a37cb7b7310e3a8533e409b8c42b4fe
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/mainboard/lenovo/x60/cmos.layout | 33 ++++++++++++++++++---------------
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout
index c0cb680..0d6060f 100644
--- a/src/mainboard/lenovo/x60/cmos.layout
+++ b/src/mainboard/lenovo/x60/cmos.layout
@@ -93,10 +93,24 @@ entries
# coreboot config options: bootloader
416 512 s 0 boot_devices
-928 8 h 0 boot_default
-936 1 e 8 cmos_defaults_loaded
-937 1 e 1 lpt
-#938 46 r 0 unused
+928 8 h 0 boot_default
+936 1 e 8 cmos_defaults_loaded
+937 1 e 1 lpt
+938 1 e 9 first_battery
+939 1 e 1 bluetooth
+940 1 e 1 wwan
+941 1 e 1 wlan
+942 1 e 1 trackpoint
+943 1 e 1 fn_ctrl_swap
+
+944 8 h 0 volume
+952 8 h 0 tft_brightness
+960 1 e 1 power_management_beeps
+961 1 e 1 low_battery_beep
+962 1 e 1 sticky_fn
+963 1 e 1 touchpad
+
+#964 20 r 0 unused
# coreboot config options: check sums
984 16 h 0 check_sum
@@ -109,17 +123,6 @@ entries
1048 4 r 0 C0DRT1
1052 4 r 0 C1DRT1
-1064 8 h 0 volume
-1072 8 h 0 tft_brightness
-1080 1 e 9 first_battery
-1081 1 e 1 bluetooth
-1082 1 e 1 wwan
-1083 1 e 1 wlan
-1084 1 e 1 trackpoint
-1085 1 e 1 fn_ctrl_swap
-1086 1 e 1 sticky_fn
-1087 1 e 1 power_management_beeps
-1088 1 e 1 low_battery_beep
# -----------------------------------------------------------------
enumerations
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4796
-gerrit
commit f46f40a3ebef483685fd39f7e0917798bb8e824e
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sat Jan 25 00:24:28 2014 +0100
lenovo/x230: Extend checksummed area to cover all thinkpad options.
Change-Id: I3dd915f1cfa123a5124aec5d118f1b23719c17b8
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/mainboard/lenovo/x230/cmos.layout | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout
index fb1b61c..9f2c0e5 100644
--- a/src/mainboard/lenovo/x230/cmos.layout
+++ b/src/mainboard/lenovo/x230/cmos.layout
@@ -155,6 +155,6 @@ enumerations
# -----------------------------------------------------------------
checksums
-checksum 392 415 984
+checksum 392 431 984
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4797
-gerrit
commit a01f3db0abfe06cf73a33528c90b41f99baf1118
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sat Jan 25 00:08:36 2014 +0100
asus/a8n-e: Rename reserved_memory1 to amd_reserved.
Change-Id: I95676aa162b6faedc5aa2b4d6deb6d8da48791f4
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/mainboard/asus/a8n_e/cmos.layout | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/asus/a8n_e/cmos.layout b/src/mainboard/asus/a8n_e/cmos.layout
index b78884b..de1a56a 100644
--- a/src/mainboard/asus/a8n_e/cmos.layout
+++ b/src/mainboard/asus/a8n_e/cmos.layout
@@ -46,7 +46,7 @@ entries
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
- 1000 24 r 0 reserved_memory1
+ 1000 24 r 0 amd_reserved
enumerations
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4798
-gerrit
commit 8096b89469048cb0274ebfe68a191d31d9097330
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sat Jan 25 00:17:59 2014 +0100
lenovo/t60: Move non-raminit config to checksummed area
Some non-raminit config was erroneously put to non-checksummed
non-restored area. Put it to right place.
Change-Id: Ic0c81e350b5521bfff27a88f82b5e0bd67224afe
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/mainboard/lenovo/t60/cmos.layout | 33 ++++++++++++++++++---------------
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout
index 24deb4f..6abd075 100644
--- a/src/mainboard/lenovo/t60/cmos.layout
+++ b/src/mainboard/lenovo/t60/cmos.layout
@@ -93,10 +93,24 @@ entries
# coreboot config options: bootloader
416 512 s 0 boot_devices
-928 8 h 0 boot_default
-936 1 e 8 cmos_defaults_loaded
-937 1 e 1 lpt
-#938 46 r 0 unused
+928 8 h 0 boot_default
+936 1 e 8 cmos_defaults_loaded
+937 1 e 1 lpt
+938 1 e 9 first_battery
+939 1 e 1 bluetooth
+940 1 e 1 wwan
+941 1 e 1 wlan
+942 1 e 1 trackpoint
+943 1 e 1 fn_ctrl_swap
+
+944 8 h 0 volume
+952 8 h 0 tft_brightness
+960 1 e 1 power_management_beeps
+961 1 e 1 low_battery_beep
+962 1 e 1 sticky_fn
+963 1 e 1 touchpad
+
+#964 20 r 0 unused
# coreboot config options: check sums
984 16 h 0 check_sum
@@ -109,17 +123,6 @@ entries
1048 4 r 0 C0DRT1
1052 4 r 0 C1DRT1
-1060 1 e 1 touchpad
-1061 1 e 1 bluetooth
-1062 1 e 1 wwan
-1063 1 e 1 wlan
-1064 8 h 0 volume
-1072 1 e 9 first_battery
-1073 1 e 1 trackpoint
-1074 1 e 1 fn_ctrl_swap
-1075 1 e 1 sticky_fn
-1076 1 e 1 power_management_beeps
-1077 1 e 1 low_battery_beep
# -----------------------------------------------------------------
enumerations
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4762
-gerrit
commit 040c52854214fbdb148d168151f69d71850171de
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Mon Jan 20 22:26:05 2014 +0100
Revert "Butterfly, Stout: Force SATA link speed to 3 Gbps"
This reverts commit 7b8952c19d8d809b7aeec629b31e1c3d66f19884.
This commit was a hack to solve potential hangs caused by SSD bugs,
but the workaround limited the SATA speed of all connected drives,
despite the problem being localized to one specific model. As such,
this solution is a layering violation, as it makes too many
assumptions about the connected hardware.
Since the SATA speed can now be limited by CMOS config, and is limited
by default on butterfly and stout, the hard limit in devicetree.cb is
of no further use.
Change-Id: Ia35f7e8a24f9cb701ce0e357d9b3e929c4e0a4fb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/mainboard/google/butterfly/devicetree.cb | 2 --
src/mainboard/google/stout/devicetree.cb | 2 --
2 files changed, 4 deletions(-)
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
index 36f3ba3..c797fb0 100644
--- a/src/mainboard/google/butterfly/devicetree.cb
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -58,8 +58,6 @@ chip northbridge/intel/sandybridge
# Enable SATA ports 0 & 1
register "sata_port_map" = "0x3"
- # Set max SATA speed to 3.0 Gb/s
- register "sata_interface_speed_limit" = "0x2"
# Enable EC Port 0x68/0x6C
register "gen1_dec" = "0x00040069"
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index e157035..a9e499f 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -58,8 +58,6 @@ chip northbridge/intel/sandybridge
register "gpi6_routing" = "2"
register "sata_port_map" = "0x3"
- # Set max SATA speed to 3.0 Gb/s
- register "sata_interface_speed_limit" = "0x2"
# Enable EC Port 0x68/0x6C
register "gen1_dec" = "0x00040069"
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4823
-gerrit
commit 41874076d03d6e4095ec06458b1f7d8393bf0a30
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Sun Jan 26 11:36:07 2014 -0600
intel/bd82x6x: Allow limiting of SATA speed in CMOS config
Up until now, the only way to limit SATA speed was via devicetree.cb,
which required recompiling coreboot in order to lift this limit.
However, there are cases where limiting is still desirable with the
option to lift the limit later. To accommodate this, still check
devicetree first, but if no hard limit is specified, then use CMOS
to check if the user desires to limit the speed.
Change-Id: I0d6ac67416edcb28eb2a9091c86dc0a22d7b1d3f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/southbridge/intel/bd82x6x/sata.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 8d12202..1758bfe 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -46,7 +46,7 @@ static void sata_init(struct device *dev)
u16 reg16;
/* Get the chip configuration */
config_t *config = dev->chip_info;
- u8 sata_mode;
+ u8 sata_mode, sata_limit;
printk(BIOS_DEBUG, "SATA: Initializing...\n");
@@ -106,12 +106,25 @@ static void sata_init(struct device *dev)
reg32 = read32(abar + 0x00);
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
reg32 &= ~0x00020060; // clear SXS+EMS+PMS
- /* Set ISS, if available */
+ /* Set ISS, if available
+ * Try devicetree.cb first, for hard limit, otherwise look in
+ * CMOS for user-selectable limit
+ */
if (config->sata_interface_speed_limit)
{
+ printk(BIOS_INFO, "Applying hard limit on SATA speed");
+ sata_limit = config->sata_interface_speed_limit;
+ } else {
+ /* Default to no limit if not configured in CMOS */
+ if (get_option(&sata_limit, "sata_speed_limit")
+ != CB_SUCCESS)
+ sata_limit = 0;
+ }
+ if (sata_limit) {
+ printk(BIOS_INFO, "Limiting SATA speed to Gen%d\n",
+ sata_limit);
reg32 &= ~0x00f00000;
- reg32 |= (config->sata_interface_speed_limit & 0x03)
- << 20;
+ reg32 |= (sata_limit & 0x03) << 20;
}
write32(abar + 0x00, reg32);
/* PI (Ports implemented) */