coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 08bee23 intel/gm45: Refactor DDR3 write training
by gerrit＠coreboot.org 22 May '13

22 May '13

the following patch was just integrated into master: commit 08bee23f7eb31cce4746c51cfde3a7017e0e8b8e Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 11:58:44 2013 +0200 intel/gm45: Refactor DDR3 write training Split some code in individual functions. It's the refactoring part of a bigger change, following... Change-Id: Id19be4588ad8984935040d9bcba4d7c5f2e1114f Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/3255 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3255 for details. -gerrit

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Patch merged into coreboot/master: 35e45c0 intel/gm45: Handle overflows during DDR3 read training
by gerrit＠coreboot.org 22 May '13

22 May '13

the following patch was just integrated into master: commit 35e45c078054a7bd64ba54b8b84b07602e8dd4ff Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 11:25:59 2013 +0200 intel/gm45: Handle overflows during DDR3 read training We halted the machine on any overflow during the read training. However, overflows during the search for a good to bad edge are non-fatal, and should be ignored. Change-Id: I77085840ade25bce955480689c84603334113d1f Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/3254 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3254 for details. -gerrit

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Patch merged into coreboot/master: 26a6435 intel/gm45: Refactor DDR3 read training
by gerrit＠coreboot.org 22 May '13

22 May '13

the following patch was just integrated into master: commit 26a64351234093fbeea6e776be8829eae012ce7f Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 11:43:03 2013 +0200 intel/gm45: Refactor DDR3 read training Split some code in individual functions. It's the refactoring part of a bigger change, following... Change-Id: Ied551a011eaf22f6f8f6db0044de3634134f0b37 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/3253 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3253 for details. -gerrit

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Patch merged into coreboot/master: 0da9286 intel/gm45: Fix interpretation of VT-d disable bit
by gerrit＠coreboot.org 22 May '13

22 May '13

the following patch was just integrated into master: commit 0da92863a754828eb807f1a15927f0dc288a1788 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 11:02:43 2013 +0200 intel/gm45: Fix interpretation of VT-d disable bit When configuring the GTT size for the integrated graphics, the state of VT-d was read wrong. Bit 48 of CAPID0 (D0F0) is set when VT-d is _disabled_. In the log of a VT-d enabled roda/rk9 we have now: [...] VT-d enabled [...] IGD decoded, subtracting 32M UMA and 4M GTT [...] Without this patch, only 2M GTT were reported. Change-Id: I87582c18f4769c2a05be86936d865c0d1fb35966 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/3252 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3252 for details. -gerrit

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Patch set updated for coreboot: 0b349ae intel/gm45: Add more debug output to read/write training
by Nico Huber 22 May '13

22 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3257 -gerrit commit 0b349ae625ffd594ae9465b6339ab277641aebb9 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 12:28:42 2013 +0200 intel/gm45: Add more debug output to read/write training Add debug output for the timing values of the edges found during read and write training. Now, output for one DIMM of DDR3-1066 in a roda/rk9 looks like: [...] Lower bound for byte lane 0 on channel 0: 0.0 Upper bound for byte lane 0 on channel 0: 8.4 Final timings for byte lane 0 on channel 0: 4.2 Lower bound for byte lane 1 on channel 0: 0.0 Upper bound for byte lane 1 on channel 0: 10.2 Final timings for byte lane 1 on channel 0: 5.1 Lower bound for byte lane 2 on channel 0: 0.0 Upper bound for byte lane 2 on channel 0: 7.5 Final timings for byte lane 2 on channel 0: 3.6 Lower bound for byte lane 3 on channel 0: 0.0 Upper bound for byte lane 3 on channel 0: 11.4 Final timings for byte lane 3 on channel 0: 5.6 Lower bound for byte lane 4 on channel 0: 0.0 Upper bound for byte lane 4 on channel 0: 9.4 Final timings for byte lane 4 on channel 0: 4.6 Lower bound for byte lane 5 on channel 0: 0.0 Upper bound for byte lane 5 on channel 0: 11.2 Final timings for byte lane 5 on channel 0: 5.5 Lower bound for byte lane 6 on channel 0: 0.0 Upper bound for byte lane 6 on channel 0: 8.4 Final timings for byte lane 6 on channel 0: 4.2 Lower bound for byte lane 7 on channel 0: 0.0 Upper bound for byte lane 7 on channel 0: 10.4 Final timings for byte lane 7 on channel 0: 5.2 Lower bound for group 0 on channel 0: 1.7.5 Upper bound for group 0 on channel 0: 2.2.2 Final timings for group 0 on channel 0: 1.10.7 Lower bound for group 1 on channel 0: 1.6.1 Upper bound for group 1 on channel 0: 2.0.2 Final timings for group 1 on channel 0: 1.9.1 Lower bound for group 2 on channel 0: 2.0.7 Upper bound for group 2 on channel 0: 2.8.1 Final timings for group 2 on channel 0: 2.4.4 Lower bound for group 3 on channel 0: 2.4.7 Upper bound for group 3 on channel 0: 3.0.0 Final timings for group 3 on channel 0: 2.8.3 [...] Final timings are always the average of the two bounds. The last dots separate eights (not decimals) and the middles are elenvenths or twelfths depending on the clock speed (twelfths in this case). Change-Id: Idb7c84b514716c7265b94890c39b7225de7800dc Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- .../intel/gm45/raminit_read_write_training.c | 28 +++++++++++++++++----- 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 65e16a3..5149c2b 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -56,6 +56,14 @@ typedef struct { int t; int p; } read_timing_t; +static void print_read_timing(const int msg_lvl, const char *const msg, + const int lane, const int channel, + const read_timing_t *const timing) +{ + printk(msg_lvl, "%s for byte lane %d on channel %d: %d.%d\n", + msg, lane, channel, timing->t, timing->p); +} + static int normalize_read_timing(read_timing_t *const timing) { while (timing->p >= READ_TIMING_P_BOUND) { @@ -183,6 +191,7 @@ static void read_training_per_lane(const int channel, const int lane, lower.p = 0; if (read_training_find_lower(channel, lane, addresses, &lower) < 0) die("Read training failure: lower bound.\n"); + print_read_timing(BIOS_SPEW, "Lower bound", lane, channel, &lower); /*** Search upper bound. ***/ @@ -192,6 +201,7 @@ static void read_training_per_lane(const int channel, const int lane, if (read_training_find_upper(channel, lane, addresses, &upper) < 0) /* Overflow on upper edge is not fatal. */ printk(BIOS_WARNING, "Read training failure: upper bound.\n"); + print_read_timing(BIOS_SPEW, "Upper bound", lane, channel, &upper); /*** Calculate and program mean value. ***/ @@ -202,8 +212,7 @@ static void read_training_per_lane(const int channel, const int lane, lower.t = mean_p >> READ_TIMING_P_SHIFT; lower.p = mean_p & (READ_TIMING_P_BOUND - 1); program_read_timing(channel, lane, &lower); - printk(BIOS_DEBUG, "Final timings for byte lane %d on channel %d: " - "%d.%d\n", lane, channel, lower.t, lower.p); + print_read_timing(BIOS_DEBUG, "Final timings", lane, channel, &lower); } static void perform_read_training(const dimminfo_t *const dimms) { @@ -342,6 +351,14 @@ typedef struct { const int t_bound; int p; } write_timing_t; +static void print_write_timing(const int msg_lvl, const char *const msg, + const int group, const int channel, + const write_timing_t *const timing) +{ + printk(msg_lvl, "%s for group %d on channel %d: %d.%d.%d\n", + msg, group, channel, timing->f, timing->t, timing->p); +} + static int normalize_write_timing(write_timing_t *const timing) { while (timing->p >= WRITE_TIMING_P_BOUND) { @@ -518,6 +535,7 @@ static void write_training_per_group(const int ch, const int group, if (write_training_find_lower(ch, group, addresses, masks, memclk1067, &lower) < 0) die("Write training failure: lower bound.\n"); + print_write_timing(BIOS_SPEW, "Lower bound", group, ch, &lower); /*** Search upper bound. ***/ @@ -529,6 +547,7 @@ static void write_training_per_group(const int ch, const int group, if (write_training_find_upper(ch, group, addresses, masks, memclk1067, &upper) < 0) printk(BIOS_WARNING, "Write training failure: upper bound.\n"); + print_write_timing(BIOS_SPEW, "Upper bound", group, ch, &upper); /*** Calculate and program mean value. ***/ @@ -542,10 +561,7 @@ static void write_training_per_group(const int ch, const int group, lower.t = (mean_p >> WRITE_TIMING_P_SHIFT) % lower.t_bound; lower.p = mean_p & (WRITE_TIMING_P_BOUND - 1); program_write_timing(ch, group, &lower, memclk1067); - - printk(BIOS_DEBUG, "Final timings for group %d" - " on channel %d: %d.%d.%d\n", - group, ch, lower.f, lower.t, lower.p); + print_write_timing(BIOS_DEBUG, "Final timings", group, ch, &lower); } static void perform_write_training(const int memclk1067, const dimminfo_t *const dimms)

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Patch set updated for coreboot: 32f09fd intel/gm45: Handle overflows during DDR3 write training
by Nico Huber 22 May '13

22 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3256 -gerrit commit 32f09fdf3cc0760ab5d5949babd32d335056caf2 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 12:15:05 2013 +0200 intel/gm45: Handle overflows during DDR3 write training We halted the machine on any overflow during the write training. However, overflows during the search for a good to bad edge are non-fatal, and should be ignored. Change-Id: I45ccbabc214e208974039246d806b0d2ca2fdc03 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- .../intel/gm45/raminit_read_write_training.c | 91 +++++++++++++++------- 1 file changed, 63 insertions(+), 28 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 72c83a7..65e16a3 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -342,7 +342,7 @@ typedef struct { const int t_bound; int p; } write_timing_t; -static void normalize_write_timing(write_timing_t *const timing) +static int normalize_write_timing(write_timing_t *const timing) { while (timing->p >= WRITE_TIMING_P_BOUND) { timing->t++; @@ -360,16 +360,31 @@ static void normalize_write_timing(write_timing_t *const timing) timing->f--; timing->t += timing->t_bound; } - if ((timing->f < 0) || (timing->f >= WRITE_TIMING_F_BOUND)) - die("Timing under-/overflow during write training.\n"); + if (timing->f < 0) { + printk(BIOS_WARNING, + "Timing underflow during write training.\n"); + timing->f = 0; + timing->t = 0; + timing->p = 0; + return -1; + } else if (timing->f >= WRITE_TIMING_F_BOUND) { + printk(BIOS_WARNING, + "Timing overflow during write training.\n"); + timing->f = WRITE_TIMING_F_BOUND - 1; + timing->t = timing->t_bound - 1; + timing->p = WRITE_TIMING_P_BOUND - 1; + return -1; + } + return 0; } -static void program_write_timing(const int ch, const int group, - write_timing_t *const timing, int memclk1067) +static int program_write_timing(const int ch, const int group, + write_timing_t *const timing, int memclk1067) { /* MEM_CLOCK_1067MT? X lower/upper */ const u32 d_bounds[2][2] = { { 1, 6 }, { 2, 9 } }; - normalize_write_timing(timing); + if (normalize_write_timing(timing) < 0) + return -1; const int f = timing->f; const int t = timing->t; @@ -385,6 +400,8 @@ static void program_write_timing(const int ch, const int group, reg &= ~CxWRTy_D_MASK; reg |= CxWRTy_T(t) | CxWRTy_P(p) | CxWRTy_F(f) | d; MCHBAR32(CxWRTy_MCHBAR(ch, group)) = reg; + + return 0; } /* Returns 1 on success, 0 on failure. */ static int write_training_test(const address_bunch_t *const addresses, @@ -426,45 +443,61 @@ _bad_timing_out: return ret; } -static void write_training_find_lower(const int ch, const int group, - const address_bunch_t *const addresses, - const u32 masks[][2], const int memclk1067, - write_timing_t *const lower) +static int write_training_find_lower(const int ch, const int group, + const address_bunch_t *const addresses, + const u32 masks[][2], const int memclk1067, + write_timing_t *const lower) { program_write_timing(ch, group, lower, memclk1067); /* Coarse search for good t. */ while (!write_training_test(addresses, masks[group])) { ++lower->t; - program_write_timing(ch, group, lower, memclk1067); + if (program_write_timing(ch, group, lower, memclk1067) < 0) + return -1; } - /* Fine search for good p. */ + /* Step back, then fine search for good p. */ + if ((lower->f <= 0) && (lower->t <= 0)) + /* Can't step back, zero is good. */ + return 0; + --lower->t; program_write_timing(ch, group, lower, memclk1067); while (!write_training_test(addresses, masks[group])) { ++lower->p; - program_write_timing(ch, group, lower, memclk1067); + if (program_write_timing(ch, group, lower, memclk1067) < 0) + return -1; } + + return 0; } -static void write_training_find_upper(const int ch, const int group, - const address_bunch_t *const addresses, - const u32 masks[][2], const int memclk1067, - write_timing_t *const upper) +static int write_training_find_upper(const int ch, const int group, + const address_bunch_t *const addresses, + const u32 masks[][2], const int memclk1067, + write_timing_t *const upper) { - program_write_timing(ch, group, upper, memclk1067); - if (!write_training_test(addresses, masks[group])) - die("Write training failed; limits too narrow.\n"); - /* Coarse search for good t. */ + if (program_write_timing(ch, group, upper, memclk1067) < 0) + return -1; + if (!write_training_test(addresses, masks[group])) { + printk(BIOS_WARNING, + "Write training failure; limits too narrow.\n"); + return -1; + } + /* Coarse search for bad t. */ while (write_training_test(addresses, masks[group])) { ++upper->t; - program_write_timing(ch, group, upper, memclk1067); + if (program_write_timing(ch, group, upper, memclk1067) < 0) + return -1; } - /* Fine search for good p. */ + /* Fine search for bad p. */ --upper->t; program_write_timing(ch, group, upper, memclk1067); while (write_training_test(addresses, masks[group])) { ++upper->p; - program_write_timing(ch, group, upper, memclk1067); + if (program_write_timing(ch, group, upper, memclk1067) < 0) + return -1; } + + return 0; } static void write_training_per_group(const int ch, const int group, const address_bunch_t *const addresses, @@ -482,8 +515,9 @@ static void write_training_per_group(const int ch, const int group, lower.p = (reg >> 8) & 0x7; lower.f = ((reg >> 2) & 0x3) - 1; - write_training_find_lower(ch, group, addresses, - masks, memclk1067, &lower); + if (write_training_find_lower(ch, group, addresses, + masks, memclk1067, &lower) < 0) + die("Write training failure: lower bound.\n"); /*** Search upper bound. ***/ @@ -492,8 +526,9 @@ static void write_training_per_group(const int ch, const int group, upper.p = lower.p; upper.f = lower.f; - write_training_find_upper(ch, group, addresses, - masks, memclk1067, &upper); + if (write_training_find_upper(ch, group, addresses, + masks, memclk1067, &upper) < 0) + printk(BIOS_WARNING, "Write training failure: upper bound.\n"); /*** Calculate and program mean value. ***/

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Patch set updated for coreboot: ba811f5 intel/gm45: Refactor DDR3 read training
by Nico Huber 22 May '13

22 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3253 -gerrit commit ba811f583eb8305db835d5bc8684659e2dda808c Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 11:43:03 2013 +0200 intel/gm45: Refactor DDR3 read training Split some code in individual functions. It's the refactoring part of a bigger change, following... Change-Id: Ied551a011eaf22f6f8f6db0044de3634134f0b37 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- .../intel/gm45/raminit_read_write_training.c | 74 ++++++++++++++-------- 1 file changed, 46 insertions(+), 28 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 8c8e66a..6936d07 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -99,50 +99,68 @@ static int read_training_test(const int channel, const int lane, } return 1; } -static void read_training_per_lane(const int channel, const int lane, - const address_bunch_t *const addresses) +static void read_training_find_lower(const int channel, const int lane, + const address_bunch_t *const addresses, + read_timing_t *const lower) { - read_timing_t lower, upper; - - MCHBAR32(CxRDTy_MCHBAR(channel, lane)) |= 3 << 25; - - /* Search lower bound. */ - lower.t = 0; - lower.p = 0; - program_read_timing(channel, lane, &lower); /* Coarse search for good t. */ + program_read_timing(channel, lane, lower); while (!read_training_test(channel, lane, addresses)) { - ++lower.t; - program_read_timing(channel, lane, &lower); + ++lower->t; + program_read_timing(channel, lane, lower); } + /* Step back, then fine search for good p. */ - if (lower.t > 0) { - --lower.t; - program_read_timing(channel, lane, &lower); + if (lower->t > 0) { + --lower->t; + program_read_timing(channel, lane, lower); while (!read_training_test(channel, lane, addresses)) { - ++lower.p; - program_read_timing(channel, lane, &lower); + ++lower->p; + program_read_timing(channel, lane, lower); } } - - /* Search upper bound. */ - upper.t = lower.t + 1; - upper.p = lower.p; - program_read_timing(channel, lane, &upper); +} +static void read_training_find_upper(const int channel, const int lane, + const address_bunch_t *const addresses, + read_timing_t *const upper) +{ + program_read_timing(channel, lane, upper); if (!read_training_test(channel, lane, addresses)) die("Read training failed: limits too narrow.\n"); /* Coarse search for bad t. */ do { - ++upper.t; - program_read_timing(channel, lane, &upper); + ++upper->t; + program_read_timing(channel, lane, upper); } while (read_training_test(channel, lane, addresses)); /* Fine search for bad p. */ - --upper.t; - program_read_timing(channel, lane, &upper); + --upper->t; + program_read_timing(channel, lane, upper); while (read_training_test(channel, lane, addresses)) { - ++upper.p; - program_read_timing(channel, lane, &upper); + ++upper->p; + program_read_timing(channel, lane, upper); } +} +static void read_training_per_lane(const int channel, const int lane, + const address_bunch_t *const addresses) +{ + read_timing_t lower, upper; + + MCHBAR32(CxRDTy_MCHBAR(channel, lane)) |= 3 << 25; + + /*** Search lower bound. ***/ + + /* Start at zero. */ + lower.t = 0; + lower.p = 0; + read_training_find_lower(channel, lane, addresses, &lower); + + /*** Search upper bound. ***/ + + /* Start at lower + 1t. */ + upper.t = lower.t + 1; + upper.p = lower.p; + + read_training_find_upper(channel, lane, addresses, &upper); /* Calculate and program mean value. */ lower.p += lower.t << READ_TIMING_P_SHIFT;

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Patch set updated for coreboot: 9e3f342 intel/gm45: Fix interpretation of VT-d disable bit
by Nico Huber 22 May '13

22 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3252 -gerrit commit 9e3f34256c05dd1f3d458b93c8f0d10518958d10 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 11:02:43 2013 +0200 intel/gm45: Fix interpretation of VT-d disable bit When configuring the GTT size for the integrated graphics, the state of VT-d was read wrong. Bit 48 of CAPID0 (D0F0) is set when VT-d is _disabled_. In the log of a VT-d enabled roda/rk9 we have now: [...] VT-d enabled [...] IGD decoded, subtracting 32M UMA and 4M GTT [...] Without this patch, only 2M GTT were reported. Change-Id: I87582c18f4769c2a05be86936d865c0d1fb35966 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/northbridge/intel/gm45/igd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index d54ee41..0a8f21e 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -67,7 +67,7 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) reg16 = pci_read_config16(mch_dev, D0F0_GGC); reg16 &= 0xf00f; reg16 |= 0x0350; - if (capid & (1 << (48 - 32))) + if (!(capid & (1 << (48 - 32)))) reg16 |= 0x0800; pci_write_config16(mch_dev, D0F0_GGC, reg16);

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Patch set updated for coreboot: 76c0744 intel/gm45: Refactor DDR3 write training
by Nico Huber 22 May '13

22 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3255 -gerrit commit 76c0744e996383fb921b8d76e652876bd4c6a866 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 11:58:44 2013 +0200 intel/gm45: Refactor DDR3 write training Split some code in individual functions. It's the refactoring part of a bigger change, following... Change-Id: Id19be4588ad8984935040d9bcba4d7c5f2e1114f Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- .../intel/gm45/raminit_read_write_training.c | 85 ++++++++++++++-------- 1 file changed, 54 insertions(+), 31 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index f13cde8..72c83a7 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -426,6 +426,46 @@ _bad_timing_out: return ret; } +static void write_training_find_lower(const int ch, const int group, + const address_bunch_t *const addresses, + const u32 masks[][2], const int memclk1067, + write_timing_t *const lower) +{ + program_write_timing(ch, group, lower, memclk1067); + /* Coarse search for good t. */ + while (!write_training_test(addresses, masks[group])) { + ++lower->t; + program_write_timing(ch, group, lower, memclk1067); + } + /* Fine search for good p. */ + --lower->t; + program_write_timing(ch, group, lower, memclk1067); + while (!write_training_test(addresses, masks[group])) { + ++lower->p; + program_write_timing(ch, group, lower, memclk1067); + } +} +static void write_training_find_upper(const int ch, const int group, + const address_bunch_t *const addresses, + const u32 masks[][2], const int memclk1067, + write_timing_t *const upper) +{ + program_write_timing(ch, group, upper, memclk1067); + if (!write_training_test(addresses, masks[group])) + die("Write training failed; limits too narrow.\n"); + /* Coarse search for good t. */ + while (write_training_test(addresses, masks[group])) { + ++upper->t; + program_write_timing(ch, group, upper, memclk1067); + } + /* Fine search for good p. */ + --upper->t; + program_write_timing(ch, group, upper, memclk1067); + while (write_training_test(addresses, masks[group])) { + ++upper->p; + program_write_timing(ch, group, upper, memclk1067); + } +} static void write_training_per_group(const int ch, const int group, const address_bunch_t *const addresses, const u32 masks[][2], const int memclk1067) @@ -434,46 +474,29 @@ static void write_training_per_group(const int ch, const int group, write_timing_t lower = { 0, 0, t_bound, 0 }, upper = { 0, 0, t_bound, 0 }; - /* Search lower bound. */ + /*** Search lower bound. ***/ + + /* Start at -1f from current values. */ const u32 reg = MCHBAR32(CxWRTy_MCHBAR(ch, group)); lower.t = (reg >> 12) & 0xf; lower.p = (reg >> 8) & 0x7; lower.f = ((reg >> 2) & 0x3) - 1; - program_write_timing(ch, group, &lower, memclk1067); - /* Coarse search for good t. */ - while (!write_training_test(addresses, masks[group])) { - ++lower.t; - program_write_timing(ch, group, &lower, memclk1067); - } - /* Fine search for good p. */ - --lower.t; - program_write_timing(ch, group, &lower, memclk1067); - while (!write_training_test(addresses, masks[group])) { - ++lower.p; - program_write_timing(ch, group, &lower, memclk1067); - } - /* Search upper bound. */ + write_training_find_lower(ch, group, addresses, + masks, memclk1067, &lower); + + /*** Search upper bound. ***/ + + /* Start at lower + 3t. */ upper.t = lower.t + 3; upper.p = lower.p; upper.f = lower.f; - program_write_timing(ch, group, &upper, memclk1067); - if (!write_training_test(addresses, masks[group])) - die("Write training failed; limits too narrow.\n"); - /* Coarse search for good t. */ - while (write_training_test(addresses, masks[group])) { - ++upper.t; - program_write_timing(ch, group, &upper, memclk1067); - } - /* Fine search for good p. */ - --upper.t; - program_write_timing(ch, group, &upper, memclk1067); - while (write_training_test(addresses, masks[group])) { - ++upper.p; - program_write_timing(ch, group, &upper, memclk1067); - } - /* Calculate and program mean value. */ + write_training_find_upper(ch, group, addresses, + masks, memclk1067, &upper); + + /*** Calculate and program mean value. ***/ + lower.t += lower.f * lower.t_bound; lower.p += lower.t << WRITE_TIMING_P_SHIFT; upper.t += upper.f * upper.t_bound;

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Patch set updated for coreboot: 4b464a2 intel/gm45: Handle overflows during DDR3 read training
by Nico Huber 22 May '13

22 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3254 -gerrit commit 4b464a238796f87a73cde451cb2e2e0832280b22 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 11:25:59 2013 +0200 intel/gm45: Handle overflows during DDR3 read training We halted the machine on any overflow during the read training. However, overflows during the search for a good to bad edge are non-fatal, and should be ignored. Change-Id: I77085840ade25bce955480689c84603334113d1f Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- .../intel/gm45/raminit_read_write_training.c | 88 +++++++++++++++------- 1 file changed, 60 insertions(+), 28 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 6936d07..f13cde8 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -56,7 +56,7 @@ typedef struct { int t; int p; } read_timing_t; -static void normalize_read_timing(read_timing_t *const timing) +static int normalize_read_timing(read_timing_t *const timing) { while (timing->p >= READ_TIMING_P_BOUND) { timing->t++; @@ -66,18 +66,33 @@ static void normalize_read_timing(read_timing_t *const timing) timing->t--; timing->p += READ_TIMING_P_BOUND; } - if ((timing->t < 0) || (timing->t >= READ_TIMING_T_BOUND)) - die("Timing under-/overflow during read training.\n"); + if (timing->t < 0) { + printk(BIOS_WARNING, + "Timing underflow during read training.\n"); + timing->t = 0; + timing->p = 0; + return -1; + } else if (timing->t >= READ_TIMING_T_BOUND) { + printk(BIOS_WARNING, + "Timing overflow during read training.\n"); + timing->t = READ_TIMING_T_BOUND - 1; + timing->p = READ_TIMING_P_BOUND - 1; + return -1; + } + return 0; } -static void program_read_timing(const int ch, const int lane, - read_timing_t *const timing) +static int program_read_timing(const int ch, const int lane, + read_timing_t *const timing) { - normalize_read_timing(timing); + if (normalize_read_timing(timing) < 0) + return -1; u32 reg = MCHBAR32(CxRDTy_MCHBAR(ch, lane)); reg &= ~(CxRDTy_T_MASK | CxRDTy_P_MASK); reg |= CxRDTy_T(timing->t) | CxRDTy_P(timing->p); MCHBAR32(CxRDTy_MCHBAR(ch, lane)) = reg; + + return 0; } /* Returns 1 on success, 0 on failure. */ static int read_training_test(const int channel, const int lane, @@ -99,46 +114,60 @@ static int read_training_test(const int channel, const int lane, } return 1; } -static void read_training_find_lower(const int channel, const int lane, - const address_bunch_t *const addresses, - read_timing_t *const lower) +static int read_training_find_lower(const int channel, const int lane, + const address_bunch_t *const addresses, + read_timing_t *const lower) { /* Coarse search for good t. */ program_read_timing(channel, lane, lower); while (!read_training_test(channel, lane, addresses)) { ++lower->t; - program_read_timing(channel, lane, lower); + if (program_read_timing(channel, lane, lower) < 0) + return -1; } /* Step back, then fine search for good p. */ - if (lower->t > 0) { - --lower->t; - program_read_timing(channel, lane, lower); - while (!read_training_test(channel, lane, addresses)) { - ++lower->p; - program_read_timing(channel, lane, lower); - } + if (lower->t <= 0) + /* Can't step back, zero is good. */ + return 0; + + --lower->t; + program_read_timing(channel, lane, lower); + while (!read_training_test(channel, lane, addresses)) { + ++lower->p; + if (program_read_timing(channel, lane, lower) < 0) + return -1; } + + return 0; } -static void read_training_find_upper(const int channel, const int lane, - const address_bunch_t *const addresses, - read_timing_t *const upper) +static int read_training_find_upper(const int channel, const int lane, + const address_bunch_t *const addresses, + read_timing_t *const upper) { - program_read_timing(channel, lane, upper); - if (!read_training_test(channel, lane, addresses)) - die("Read training failed: limits too narrow.\n"); + if (program_read_timing(channel, lane, upper) < 0) + return -1; + if (!read_training_test(channel, lane, addresses)) { + printk(BIOS_WARNING, + "Read training failure: limits too narrow.\n"); + return -1; + } /* Coarse search for bad t. */ do { ++upper->t; - program_read_timing(channel, lane, upper); + if (program_read_timing(channel, lane, upper) < 0) + return -1; } while (read_training_test(channel, lane, addresses)); /* Fine search for bad p. */ --upper->t; program_read_timing(channel, lane, upper); while (read_training_test(channel, lane, addresses)) { ++upper->p; - program_read_timing(channel, lane, upper); + if (program_read_timing(channel, lane, upper) < 0) + return -1; } + + return 0; } static void read_training_per_lane(const int channel, const int lane, const address_bunch_t *const addresses) @@ -152,17 +181,20 @@ static void read_training_per_lane(const int channel, const int lane, /* Start at zero. */ lower.t = 0; lower.p = 0; - read_training_find_lower(channel, lane, addresses, &lower); + if (read_training_find_lower(channel, lane, addresses, &lower) < 0) + die("Read training failure: lower bound.\n"); /*** Search upper bound. ***/ /* Start at lower + 1t. */ upper.t = lower.t + 1; upper.p = lower.p; + if (read_training_find_upper(channel, lane, addresses, &upper) < 0) + /* Overflow on upper edge is not fatal. */ + printk(BIOS_WARNING, "Read training failure: upper bound.\n"); - read_training_find_upper(channel, lane, addresses, &upper); + /*** Calculate and program mean value. ***/ - /* Calculate and program mean value. */ lower.p += lower.t << READ_TIMING_P_SHIFT; upper.p += upper.t << READ_TIMING_P_SHIFT; const int mean_p = (lower.p + upper.p) >> 1;

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coreboot-gerrit May 2013