Change in flashrom[master]: ichspi.c: Consolidate ich_spi_mode select into a switch stmt

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43894 )

Change subject: ichspi.c: Consolidate ich_spi_mode select into a switch stmt
......................................................................

ichspi.c: Consolidate ich_spi_mode select into a switch stmt

Change-Id: I35535c3dac9fa796d204d60e5fc72a7d5f85d706
Signed-off-by: Edward O'Callaghan 
---
M ichspi.c
1 file changed, 12 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/43894/1

diff --git a/ichspi.c b/ichspi.c
index 4dbe69a..1cc1cd7 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -2002,16 +2002,18 @@
    		ich_spi_mode = ich_hwseq;
    	}

-		if (ich_spi_mode == ich_auto &&
-		    (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT ||
-		     ich_gen == CHIPSET_300_SERIES_CANNON_POINT)) {
-			msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n");
-			ich_spi_mode = ich_hwseq;
-		}
-
-		if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_APOLLO_LAKE) {
-			msg_pdbg("Enabling hardware sequencing by default for Apollo Lake.\n");
-			ich_spi_mode = ich_hwseq;
+		if (ich_spi_mode == ich_auto) {
+			switch (ich_gen) {
+			case CHIPSET_100_SERIES_SUNRISE_POINT:
+			case CHIPSET_300_SERIES_CANNON_POINT:
+			case CHIPSET_APOLLO_LAKE:
+				msg_pdbg("Enabling hardware sequencing by default "
+					 "for 100+ series PCH.\n");
+				ich_spi_mode = ich_hwseq;
+				break;
+			default:
+				break;
+			}
    	}

if (ich_spi_mode == ich_hwseq) {

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/43894 )

Change subject: ichspi.c: Consolidate ich_spi_mode select into a switch stmt
......................................................................

Patch Set 1: Code-Review+1

(1 comment)

https://review.coreboot.org/c/flashrom/+/43894/1/ichspi.c 
File ichspi.c:

https://review.coreboot.org/c/flashrom/+/43894/1/ichspi.c@2011 
PS1, Line 2011: 					 "for 100+ series PCH.\n");
nit: mention Apollo Lake too?

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/43894 )

Change subject: ichspi.c: Consolidate ich_spi_mode select into a switch stmt
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/flashrom/+/43894/1/ichspi.c 
File ichspi.c:

https://review.coreboot.org/c/flashrom/+/43894/1/ichspi.c@2011 
PS1, Line 2011: 					 "for 100+ series PCH.\n");
> nit: mention Apollo Lake too?

Isn't this all done already by the strings in chipset_enable.c ? I think this is the wrong place to be printing this stuff apart from the fact that we are taking the PCH100+ path here.

snip from cros tree:
```
chipset_enable.c:       {0x8086, 0x5af0, B_FS,    OK, "Intel", "Apollolake",                    enable_flash_apl},
```