Konstantin Grudnev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34496 )
Change subject: Add support for M95M02-A125 ......................................................................
Add support for M95M02-A125
Automotive 2 Mbit (256KiB) serial SPI bus EEPROM PREW tested successfully with use of ch341a programmer on Linux host 5.2.0-1-MANJARO x86_64
Signed-off-by: Konstantin Grudnev grudnevkv@gmail.com Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b --- M chipdrivers.h M flashchips.c M flashchips.h M spi.h M spi25.c 5 files changed, 102 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/34496/1
diff --git a/chipdrivers.h b/chipdrivers.h index e380878..0b4435c 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -34,6 +34,7 @@ int probe_spi_res1(struct flashctx *flash); int probe_spi_res2(struct flashctx *flash); int probe_spi_res3(struct flashctx *flash); +int probe_spi_st95(struct flashctx *flash); int probe_spi_at25f(struct flashctx *flash); int spi_write_enable(struct flashctx *flash); int spi_write_disable(struct flashctx *flash); @@ -51,6 +52,7 @@ int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_dc(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen); erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); int spi_chip_write_1(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int spi_nbyte_read(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); diff --git a/flashchips.c b/flashchips.c index 166af6a..44875c6 100644 --- a/flashchips.c +++ b/flashchips.c @@ -14104,6 +14104,33 @@ },
{ + .vendor = "ST", + .name = "M95M02", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M95M02, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_st95, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 256 * 1024, 1 } }, + .block_erase = spi_block_erase_emulation, + } + }, + + .printlock = spi_prettyprint_status_register_bp1_srwd, + .unlock = spi_disable_blockprotect_bp1_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2500, 5500}, + }, + + { .vendor = "Sanyo", .name = "LE25FU106B", .bustype = BUS_SPI, diff --git a/flashchips.h b/flashchips.h index 006b95e..d1eed91 100644 --- a/flashchips.h +++ b/flashchips.h @@ -851,6 +851,12 @@ #define ST_M58WR032KT 0x8814 #define ST_M58WR064KB 0x8811 #define ST_M58WR064KT 0x8810 + +/* 00h ST Manufacturer code ST_ID*/ +/* 01h SPI Family code 0x00*/ +/* 02h Memory Density code ST_M95XXX */ +#define ST_M95M02 0x0012 /* ST M95XXX 2Mbit (256KiB) */ + #define ST_MT28GU01G___1 0x88B0 #define ST_MT28GU01G___2 0x88B1 #define ST_MT28GU256___1 0x8901 diff --git a/spi.h b/spi.h index 0073c71..9f199f3 100644 --- a/spi.h +++ b/spi.h @@ -28,6 +28,12 @@ /* INSIZE may be 0x04 for some chips*/ #define JEDEC_RDID_INSIZE 0x03
+/* Some ST M95X model */ +#define ST_M95_RDID 0x83 +#define ST_M95_RDID_OUTSIZE 0x04 /* 8b op, 24bit addr where size >64KiB */ +#define ST_M95_RDID_INSIZE 0x03 + + /* Some Atmel AT25F* models have bit 3 as don't care bit in commands */ #define AT25F_RDID 0x15 /* 0x15 or 0x1d */ #define AT25F_RDID_OUTSIZE 0x01 diff --git a/spi25.c b/spi25.c index 2a1d492..ec35585 100644 --- a/spi25.c +++ b/spi25.c @@ -21,6 +21,7 @@ #include <stddef.h> #include <string.h> #include <stdbool.h> +#include <stdlib.h> #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" @@ -262,6 +263,32 @@ return 1; }
+/* Only used for some stm95080 and higher chip. */ +int probe_spi_st95(struct flashctx *flash) +{ + /* ST_M95_RDID_OUTSIZE depends on size of the flash and + * not all ST_M95XXX have RDID + */ + static const unsigned char cmd[ST_M95_RDID_OUTSIZE] = {ST_M95_RDID}; + unsigned char readarr[ST_M95_RDID_INSIZE]; + uint32_t id1, id2; + + spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); + + id1 = readarr[0]; // manufacture id + id2 = readarr[2]; // model id + + msg_ginfo("RDID[%s: id1 0x%02x, id2 0x%02x, " + "L 0x%02x, M 0x%02x, H 0x%02x]\n", + __func__, flash->chip->manufacture_id, flash->chip->model_id, + readarr[0], readarr[1], readarr[2]); + + if (id1 == flash->chip->manufacture_id && id2 == flash->chip->model_id) + return 1; + + return 0; +} + /* Only used for some Atmel chips. */ int probe_spi_at25f(struct flashctx *flash) { @@ -440,6 +467,13 @@ return result ? result : status; }
+static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) +{ + const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_WRITE && spi_master_4ba(flash); + const uint8_t op = native_4ba ? JEDEC_BYTE_PROGRAM_4BA : JEDEC_BYTE_PROGRAM; + return spi_write_cmd(flash, op, native_4ba, addr, bytes, len, 10); +} + static int spi_chip_erase_60(struct flashctx *flash) { /* This usually takes 1-85s, so wait in 1s steps. */ @@ -577,6 +611,33 @@ return spi_write_cmd(flash, 0xdc, true, addr, NULL, 0, 100 * 1000); }
+/* some chips don't have erase function */ +int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + unsigned int i; + const unsigned int erase_len = flash->chip->page_size; + uint8_t *erased_contents = NULL; + int result = 0; + + erased_contents = (uint8_t*) malloc(erase_len * sizeof(uint8_t)); + if (!erased_contents) { + msg_cerr("Out of memory!\n"); + return 1; + } + + memset(erased_contents, ERASED_VALUE(flash), erase_len * sizeof(uint8_t)); + msg_cinfo("\n"); + for (i = addr; i < blocklen; i+=erase_len) { + if (spi_nbyte_program(flash, i, erased_contents, erase_len)) { + result = 1; + break; + } + } + + free(erased_contents); + return result; +} + erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode) { switch(opcode){ @@ -619,13 +680,6 @@ } }
-static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) -{ - const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_WRITE && spi_master_4ba(flash); - const uint8_t op = native_4ba ? JEDEC_BYTE_PROGRAM_4BA : JEDEC_BYTE_PROGRAM; - return spi_write_cmd(flash, op, native_4ba, addr, bytes, len, 10); -} - int spi_nbyte_read(struct flashctx *flash, unsigned int address, uint8_t *bytes, unsigned int len) {
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/34496 )
Change subject: Add support for M95M02-A125 ......................................................................
Patch Set 1:
(8 comments)
Nice work, I didn't think it would be that simple :)
Beside coding style, there are some thinks that would probably much easier be done now:
* Probing can be generic (i.e. decide the command bytes based on EEPROM size). * _erase_emulation() can be much simpler if restricted to the page size. * As we don't have to erase before writing FEATURE_NO_ERASE should work (erase emulation is still useful for -E).
https://review.coreboot.org/c/flashrom/+/34496/1/flashchips.h File flashchips.h:
https://review.coreboot.org/c/flashrom/+/34496/1/flashchips.h@856 PS1, Line 856: 0x00 If we know it's supposed to be 0x00, why not check it?
https://review.coreboot.org/c/flashrom/+/34496/1/flashchips.c File flashchips.c:
https://review.coreboot.org/c/flashrom/+/34496/1/flashchips.c@14114 PS1, Line 14114: .feature_bits = FEATURE_WRSR_WREN, FEATURE_NO_ERASE and FEATURE_ERASED_ZERO?
https://review.coreboot.org/c/flashrom/+/34496/1/flashchips.c@14121 PS1, Line 14121: .eraseblocks = { { 256 * 1024, 1 } }, Alternatively to handle pages in spi_block_erase_emulation(), we could declare this as { 256, 1 }. Actually, I think that would be much cleaner (you can also add a check there that `blocklen` matches the page size). So you can ignore my comment in `spi25.c`.
https://review.coreboot.org/c/flashrom/+/34496/1/spi25.c File spi25.c:
PS1: (spi)25 != 95, please don't hesitate to start a new file. Or maybe we should rename this one to `spi_jedec.c`?
General coding style is that of the Linux kernel with the exception that we allow up to 112 chars per line (if it helps readability). Use tabs for indentation (they count as 8 chars w.r.t. the line length).
https://review.coreboot.org/c/flashrom/+/34496/1/spi25.c@269 PS1, Line 269: /* ST_M95_RDID_OUTSIZE depends on size of the flash and Please start multi-line comments with /* on a separate line. However this should fit on one line (112 char limit).
Also, why not turn it into code? you can read the size of the EEPROM entry (flash->chip->total_size?), decide the number of bytes to send based on that?
https://review.coreboot.org/c/flashrom/+/34496/1/spi25.c@272 PS1, Line 272: static const unsigned char cmd[ST_M95_RDID_OUTSIZE] = {ST_M95_RDID}; spaces around ST_M95_RDID, please
https://review.coreboot.org/c/flashrom/+/34496/1/spi25.c@282 PS1, Line 282: "L 0x%02x, M 0x%02x, H 0x%02x]\n", Please align output with the existing probing functions.
`id1` and `id2` usually refer to the data read from the chip, afaik.
https://review.coreboot.org/c/flashrom/+/34496/1/spi25.c@635 PS1, Line 635: } Alternatively, allocate `blocklen` bytes and let spi_write_chunked() take care of the pages.
Konstantin Grudnev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/34496 )
Change subject: Add support for M95M02-A125 ......................................................................
Patch Set 1:
(1 comment)
some answers are needed
https://review.coreboot.org/c/flashrom/+/34496/1/flashchips.c File flashchips.c:
https://review.coreboot.org/c/flashrom/+/34496/1/flashchips.c@14121 PS1, Line 14121: .eraseblocks = { { 256 * 1024, 1 } },
Alternatively to handle pages in spi_block_erase_emulation(), […]
what do you mean by declaring { 256, 1 } ? I tried it and it tries to erase only first 256 bytes, also tried .eraseblocks { 256, 1024 } and it doesn't work, cause eraseblocks.count is not used in .block_erase() function in no shape or form, so the only way to compute eraseblocks.count is to divide total_size(256KiB)/blocklen(256) = 1024. So, your comment needs more elaboration, or I will leave it as it is.
Hello build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/34496
to look at the new patch set (#2).
Change subject: Add support for M95M02-A125 ......................................................................
Add support for M95M02-A125
Automotive 2 Mbit (256KiB) serial SPI bus EEPROM PREW tested successfully with use of ch341a programmer on Linux host 5.2.0-1-MANJARO x86_64
Signed-off-by: Konstantin Grudnev grudnevkv@gmail.com Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b --- M Makefile M chipdrivers.h M flashchips.c M flashchips.h M spi.h M spi25.c A spi95.c 7 files changed, 125 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/34496/2
Konstantin Grudnev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/34496 )
Change subject: Add support for M95M02-A125 ......................................................................
Patch Set 2:
(8 comments)
fixed
https://review.coreboot.org/c/flashrom/+/34496/1/flashchips.h File flashchips.h:
https://review.coreboot.org/c/flashrom/+/34496/1/flashchips.h@856 PS1, Line 856: 0x00
If we know it's supposed to be 0x00, why not check it?
Done
https://review.coreboot.org/c/flashrom/+/34496/1/flashchips.c File flashchips.c:
https://review.coreboot.org/c/flashrom/+/34496/1/flashchips.c@14114 PS1, Line 14114: .feature_bits = FEATURE_WRSR_WREN,
FEATURE_NO_ERASE and FEATURE_ERASED_ZERO?
Done
https://review.coreboot.org/c/flashrom/+/34496/1/flashchips.c@14121 PS1, Line 14121: .eraseblocks = { { 256 * 1024, 1 } },
what do you mean by declaring { 256, 1 } ? I tried it and it tries to erase only first 256 bytes, al […]
Done
https://review.coreboot.org/c/flashrom/+/34496/1/spi25.c File spi25.c:
PS1:
(spi)25 != 95, please don't hesitate to start a new file. Or maybe […]
Done
https://review.coreboot.org/c/flashrom/+/34496/1/spi25.c@269 PS1, Line 269: /* ST_M95_RDID_OUTSIZE depends on size of the flash and
Please start multi-line comments with /* on a separate line. However this […]
Done
https://review.coreboot.org/c/flashrom/+/34496/1/spi25.c@272 PS1, Line 272: static const unsigned char cmd[ST_M95_RDID_OUTSIZE] = {ST_M95_RDID};
spaces around ST_M95_RDID, please
Done
https://review.coreboot.org/c/flashrom/+/34496/1/spi25.c@282 PS1, Line 282: "L 0x%02x, M 0x%02x, H 0x%02x]\n",
Please align output with the existing probing functions. […]
Done
https://review.coreboot.org/c/flashrom/+/34496/1/spi25.c@635 PS1, Line 635: }
Alternatively, allocate `blocklen` bytes and let spi_write_chunked() take […]
Done
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/34496 )
Change subject: Add support for M95M02-A125 ......................................................................
Patch Set 2:
(8 comments)
Thanks for the update. It seems nearly ready.
I've looked closer at this "family code" and am sure that it is usually handled as part of what flashrom calls the model id.
https://review.coreboot.org/c/flashrom/+/34496/2/flashchips.h File flashchips.h:
https://review.coreboot.org/c/flashrom/+/34496/2/flashchips.h@858 PS2, Line 858: #define ST_SPI_FAMILY_CODE 0x00 : #define ST_M95M02 0x0012 /* ST M95XXX 2Mbit (256KiB) */ Please use tabs for alignment.
https://review.coreboot.org/c/flashrom/+/34496/2/flashchips.h@859 PS2, Line 859: 00 The high byte 00 here is actually the family code. I don't think we need a separate definition for that. The "model id" for ST_M95M02 should simply include it.
https://review.coreboot.org/c/flashrom/+/34496/1/flashchips.c File flashchips.c:
https://review.coreboot.org/c/flashrom/+/34496/1/flashchips.c@14121 PS1, Line 14121: .eraseblocks = { { 256 * 1024, 1 } },
Done
I guess, I really meant `{ 256, 1024 }`. The `.count` is handled in walk_eraseblocks(). I don't care much, as running flashrom with -E for an EEPROM is rather theoretical anyway.
https://review.coreboot.org/c/flashrom/+/34496/2/spi25.c File spi25.c:
https://review.coreboot.org/c/flashrom/+/34496/2/spi25.c@443 PS2, Line 443: static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) Moving this function doesn't seem needed anymore?
https://review.coreboot.org/c/flashrom/+/34496/2/spi95.c File spi95.c:
https://review.coreboot.org/c/flashrom/+/34496/2/spi95.c@8 PS2, Line 8: * the Free Software Foundation; version 2 of the License. I would prefer new code to be added under
"either version 2 of the License, or (at your option) any later version."
It's your call. I just want to make sure, you are aware that not all of flashrom agrees to the v2-only choice.
https://review.coreboot.org/c/flashrom/+/34496/2/spi95.c@34 PS2, Line 34: uint32_t id1, id2, id3; As mentioned in `flashchips.h`, the model id (id2) should include the family code. So this should be:
uint8_t id1; uint16_t id2;
https://review.coreboot.org/c/flashrom/+/34496/2/spi95.c@43 PS2, Line 43: id2 = readarr[2]; // model id : id3 = readarr[1]; // SPI Family code, must be 0x00 : Please join these into a single `id2` that is compared against `chip->model_id`.
https://review.coreboot.org/c/flashrom/+/34496/2/spi95.c@61 PS2, Line 61: (uint8_t*) malloc Please place space as follows:
(uint8_t *)malloc
Hello build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/34496
to look at the new patch set (#3).
Change subject: Add support for M95M02-A125 ......................................................................
Add support for M95M02-A125
Automotive 2 Mbit (256KiB) serial SPI bus EEPROM PREW tested successfully with use of ch341a programmer on Linux host 5.2.0-1-MANJARO x86_64
Signed-off-by: Konstantin Grudnev grudnevkv@gmail.com Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b --- M Makefile M chipdrivers.h M flashchips.c M flashchips.h M spi.h A spi95.c 6 files changed, 115 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/34496/3
Konstantin Grudnev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/34496 )
Change subject: Add support for M95M02-A125 ......................................................................
Patch Set 3:
(7 comments)
fixed
https://review.coreboot.org/c/flashrom/+/34496/2/flashchips.h File flashchips.h:
https://review.coreboot.org/c/flashrom/+/34496/2/flashchips.h@858 PS2, Line 858: #define ST_SPI_FAMILY_CODE 0x00 : #define ST_M95M02 0x0012 /* ST M95XXX 2Mbit (256KiB) */
Please use tabs for alignment.
Done
https://review.coreboot.org/c/flashrom/+/34496/2/flashchips.h@859 PS2, Line 859: 00
The high byte 00 here is actually the family code. I don't […]
Done
https://review.coreboot.org/c/flashrom/+/34496/2/spi25.c File spi25.c:
https://review.coreboot.org/c/flashrom/+/34496/2/spi25.c@443 PS2, Line 443: static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len)
Moving this function doesn't seem needed anymore?
Done
https://review.coreboot.org/c/flashrom/+/34496/2/spi95.c File spi95.c:
https://review.coreboot.org/c/flashrom/+/34496/2/spi95.c@8 PS2, Line 8: * the Free Software Foundation; version 2 of the License.
I would prefer new code to be added under […]
Done
https://review.coreboot.org/c/flashrom/+/34496/2/spi95.c@34 PS2, Line 34: uint32_t id1, id2, id3;
As mentioned in `flashchips.h`, the model id (id2) should include the […]
Done
https://review.coreboot.org/c/flashrom/+/34496/2/spi95.c@43 PS2, Line 43: id2 = readarr[2]; // model id : id3 = readarr[1]; // SPI Family code, must be 0x00 :
Please join these into a single `id2` that is compared against `chip->model_id`.
Done
https://review.coreboot.org/c/flashrom/+/34496/2/spi95.c@61 PS2, Line 61: (uint8_t*) malloc
Please place space as follows: […]
Done
Hello build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/34496
to look at the new patch set (#4).
Change subject: Add support for M95M02-A125 ......................................................................
Add support for M95M02-A125
Automotive 2 Mbit (256KiB) serial SPI bus EEPROM PREW tested successfully with use of ch341a programmer on Linux host 5.2.0-1-MANJARO x86_64
Signed-off-by: Konstantin Grudnev grudnevkv@gmail.com Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b --- M Makefile M chipdrivers.h M flashchips.c M flashchips.h M spi.h A spi95.c 6 files changed, 115 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/34496/4
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/34496 )
Change subject: Add support for M95M02-A125 ......................................................................
Patch Set 4:
(3 comments)
Hi,
um, sorry for the huge delay. I thought we didn't need another round and could merge as is, then I noticed the license change. GPL v3 only just doesn't work, because parts of flashrom are v2 only. I believe it would be best for flashrom to license new code as v2 and later. That and v2 only are the only options.
https://review.coreboot.org/c/flashrom/+/34496/4/flashchips.h File flashchips.h:
https://review.coreboot.org/c/flashrom/+/34496/4/flashchips.h@855 PS4, Line 855: /* 00h ST Manufacturer code ST_ID*/ : /* 01h SPI Family code 0x00*/ : /* 02h Memory Density code ST_M95XXX */ This is just like it always is, imho, no need for this comment.
If you want to keep it, please remove the ST_ID and keep it to the two bytes defined below (the indices are confusing because they refer to the specific RDID command).
https://review.coreboot.org/c/flashrom/+/34496/4/spi95.c File spi95.c:
https://review.coreboot.org/c/flashrom/+/34496/4/spi95.c@8 PS4, Line 8: version 3 ugh, this is incompatible with much of flashrom (some parts are version 2 only, doesn't mix well with 3 only)
https://review.coreboot.org/c/flashrom/+/34496/4/spi95.c@59 PS4, Line 59: Nit, still a spurious space after the closing parenthesis.
Hello David Hendricks, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/34496
to look at the new patch set (#5).
Change subject: Add support for M95M02-A125 ......................................................................
Add support for M95M02-A125
Automotive 2 Mbit (256KiB) serial SPI bus EEPROM PREW tested successfully with use of ch341a programmer on Linux host 5.2.0-1-MANJARO x86_64
Signed-off-by: Konstantin Grudnev grudnevkv@gmail.com Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b --- M Makefile M chipdrivers.h M flashchips.c M flashchips.h M spi.h A spi95.c 6 files changed, 111 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/34496/5
Konstantin Grudnev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/34496 )
Change subject: Add support for M95M02-A125 ......................................................................
Patch Set 4:
(3 comments)
fixed
https://review.coreboot.org/c/flashrom/+/34496/4/flashchips.h File flashchips.h:
https://review.coreboot.org/c/flashrom/+/34496/4/flashchips.h@855 PS4, Line 855: /* 00h ST Manufacturer code ST_ID*/ : /* 01h SPI Family code 0x00*/ : /* 02h Memory Density code ST_M95XXX */
This is just like it always is, imho, no need for this comment. […]
Done
https://review.coreboot.org/c/flashrom/+/34496/4/spi95.c File spi95.c:
https://review.coreboot.org/c/flashrom/+/34496/4/spi95.c@8 PS4, Line 8: version 3
ugh, this is incompatible with much of flashrom (some parts are version 2 […]
Done
https://review.coreboot.org/c/flashrom/+/34496/4/spi95.c@59 PS4, Line 59:
Nit, still a spurious space after the closing parenthesis.
Done
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/34496 )
Change subject: Add support for M95M02-A125 ......................................................................
Patch Set 5: Code-Review+2
Thanks for the patience, looks really good now :)
Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/34496 )
Change subject: Add support for M95M02-A125 ......................................................................
Add support for M95M02-A125
Automotive 2 Mbit (256KiB) serial SPI bus EEPROM PREW tested successfully with use of ch341a programmer on Linux host 5.2.0-1-MANJARO x86_64
Signed-off-by: Konstantin Grudnev grudnevkv@gmail.com Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b Reviewed-on: https://review.coreboot.org/c/flashrom/+/34496 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M Makefile M chipdrivers.h M flashchips.c M flashchips.h M spi.h A spi95.c 6 files changed, 111 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/Makefile b/Makefile index 1a20933..b0c242d 100644 --- a/Makefile +++ b/Makefile @@ -542,7 +542,7 @@ CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \ sst28sf040.o 82802ab.o \ sst49lfxxxc.o sst_fwhub.o edi.o flashchips.o spi.o spi25.o spi25_statusreg.o \ - opaque.o sfdp.o en29lv640b.o at45db.o + spi95.o opaque.o sfdp.o en29lv640b.o at45db.o
############################################################################### # Library code. diff --git a/chipdrivers.h b/chipdrivers.h index e380878..cb1e877 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -202,4 +202,8 @@ int edi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int edi_probe_kb9012(struct flashctx *flash);
+/* spi95.c */ +int probe_spi_st95(struct flashctx *flash); +int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + #endif /* !__CHIPDRIVERS_H__ */ diff --git a/flashchips.c b/flashchips.c index 7635942..65110fe 100644 --- a/flashchips.c +++ b/flashchips.c @@ -14240,6 +14240,33 @@ },
{ + .vendor = "ST", + .name = "M95M02", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M95M02, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_NO_ERASE | FEATURE_ERASED_ZERO, + .tested = TEST_OK_PREW, + .probe = probe_spi_st95, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_emulation, + } + }, + + .printlock = spi_prettyprint_status_register_bp1_srwd, + .unlock = spi_disable_blockprotect_bp1_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2500, 5500}, + }, + + { .vendor = "Sanyo", .name = "LE25FU106B", .bustype = BUS_SPI, diff --git a/flashchips.h b/flashchips.h index c4b863d..88816c4 100644 --- a/flashchips.h +++ b/flashchips.h @@ -852,6 +852,9 @@ #define ST_M58WR032KT 0x8814 #define ST_M58WR064KB 0x8811 #define ST_M58WR064KT 0x8810 + +#define ST_M95M02 0x0012 /* ST M95XXX 2Mbit (256KiB) */ + #define ST_MT28GU01G___1 0x88B0 #define ST_MT28GU01G___2 0x88B1 #define ST_MT28GU256___1 0x8901 diff --git a/spi.h b/spi.h index 0073c71..3f45038 100644 --- a/spi.h +++ b/spi.h @@ -28,6 +28,13 @@ /* INSIZE may be 0x04 for some chips*/ #define JEDEC_RDID_INSIZE 0x03
+/* Some ST M95X model */ +#define ST_M95_RDID 0x83 +#define ST_M95_RDID_3BA_OUTSIZE 0x04 /* 8b op, 24bit addr where size >64KiB */ +#define ST_M95_RDID_2BA_OUTSIZE 0x03 /* 8b op, 16bit addr where size <=64KiB */ +#define ST_M95_RDID_OUTSIZE_MAX 0x04 /* ST_M95_RDID_3BA_OUTSIZE */ +#define ST_M95_RDID_INSIZE 0x03 + /* Some Atmel AT25F* models have bit 3 as don't care bit in commands */ #define AT25F_RDID 0x15 /* 0x15 or 0x1d */ #define AT25F_RDID_OUTSIZE 0x01 diff --git a/spi95.c b/spi95.c new file mode 100644 index 0000000..ecb2c1d --- /dev/null +++ b/spi95.c @@ -0,0 +1,69 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2019 Konstantin Grudnev + * Copyright (C) 2019 Nikolay Nikolaev + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, + * or any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Contains SPI chip driver functions related to ST95XXX series (SPI EEPROM) + */ +#include <string.h> +#include <stdlib.h> +#include "flashchips.h" +#include "chipdrivers.h" +#include "spi.h" + +/* For ST95XXX chips which have RDID */ +int probe_spi_st95(struct flashctx *flash) +{ + /* + * ST_M95_RDID_OUTSIZE depends on size of the flash and + * not all ST_M95XXX have RDID. + */ + static const unsigned char cmd[ST_M95_RDID_OUTSIZE_MAX] = { ST_M95_RDID }; + unsigned char readarr[ST_M95_RDID_INSIZE]; + uint32_t id1, id2; + + uint32_t rdid_outsize = ST_M95_RDID_2BA_OUTSIZE; // 16 bit address + if (flash->chip->total_size * KiB > 64 * KiB) + rdid_outsize = ST_M95_RDID_3BA_OUTSIZE; // 24 bit address + + spi_send_command(flash, rdid_outsize, sizeof(readarr), cmd, readarr); + + id1 = readarr[0]; // manufacture id + id2 = (readarr[1] << 8) | readarr[2]; // SPI family code + model id + + msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); + + if (id1 == flash->chip->manufacture_id && id2 == flash->chip->model_id) + return 1; + + return 0; +} + +/* ST95XXX chips don't have erase operation and erase is made as part of write command */ +int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + uint8_t *erased_contents = NULL; + int result = 0; + + erased_contents = (uint8_t *)malloc(blocklen * sizeof(uint8_t)); + if (!erased_contents) { + msg_cerr("Out of memory!\n"); + return 1; + } + memset(erased_contents, ERASED_VALUE(flash), blocklen * sizeof(uint8_t)); + result = spi_write_chunked(flash, erased_contents, 0, blocklen, flash->chip->page_size); + free(erased_contents); + return result; +}
-
Konstantin Grudnev (Code Review) -
Nico Huber (Code Review)