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[L] Change in flashrom[main]: flashrom.c: Delete legacy erase and write logic
by Anastasia Klimchuk (Code Review) 09 Aug '24

09 Aug '24

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83846?usp=email ) Change subject: flashrom.c: Delete legacy erase and write logic ...................................................................... flashrom.c: Delete legacy erase and write logic Current code path for erase and write has been enabled in the tree since May 2023, which is more than 1 year ago (15 months ago), and legacy path has been disabled since the same time. Current logic has been officially released in v1.4.0 in July 2024. Change-Id: I08fd686fecf6a5313eea2d66b368661c664f4800 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M flashrom.c 1 file changed, 0 insertions(+), 366 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/46/83846/1 diff --git a/flashrom.c b/flashrom.c index dbf06cf..b0edcf8 100644 --- a/flashrom.c +++ b/flashrom.c @@ -36,8 +36,6 @@ #include "chipdrivers.h" #include "erasure_layout.h" -static bool use_legacy_erase_path = false; - const char flashrom_version[] = FLASHROM_VERSION; static const struct programmer_entry *programmer = NULL; @@ -1330,248 +1328,6 @@ } typedef int (*erasefn_t)(struct flashctx *, unsigned int addr, unsigned int len); -/** - * @private - * - * For read-erase-write, `curcontents` and `newcontents` shall point - * to buffers of the chip's size. Both are supposed to be prefilled - * with at least the included layout regions of the current flash - * contents (`curcontents`) and the data to be written to the flash - * (`newcontents`). - * - * For erase, `curcontents` and `newcontents` shall be NULL-pointers. - * - * The `chipoff_t` values are used internally by `walk_by_layout()`. - */ -struct walk_info { - uint8_t *curcontents; - const uint8_t *newcontents; - chipoff_t region_start; - chipoff_t region_end; - chipoff_t erase_start; - chipoff_t erase_end; -}; -/* returns 0 on success, 1 to retry with another erase function, 2 for immediate abort */ -typedef int (*per_blockfn_t)(struct flashctx *, const struct walk_info *, erasefn_t, bool *); - -static int walk_eraseblocks(struct flashctx *const flashctx, - struct walk_info *const info, - const size_t erasefunction, const per_blockfn_t per_blockfn, - bool *all_skipped) -{ - int ret; - size_t i, j; - bool first = true; - struct block_eraser *const eraser = &flashctx->chip->block_erasers[erasefunction]; - - info->erase_start = 0; - for (i = 0; i < NUM_ERASEREGIONS; ++i) { - /* count==0 for all automatically initialized array - members so the loop below won't be executed for them. */ - for (j = 0; j < eraser->eraseblocks[i].count; ++j, info->erase_start = info->erase_end + 1) { - info->erase_end = info->erase_start + eraser->eraseblocks[i].size - 1; - - /* Skip any eraseblock that is completely outside the current region. */ - if (info->erase_end < info->region_start) - continue; - if (info->region_end < info->erase_start) - break; - - /* Print this for every block except the first one. */ - if (first) - first = false; - else - msg_cdbg(", "); - msg_cdbg("0x%06"PRIx32"-0x%06"PRIx32":", info->erase_start, info->erase_end); - - erasefunc_t *erase_func = lookup_erase_func_ptr(eraser); - ret = per_blockfn(flashctx, info, erase_func, all_skipped); - if (ret) - return ret; - } - if (info->region_end < info->erase_start) - break; - } - msg_cdbg("\n"); - return 0; -} - -static int walk_by_layout(struct flashctx *const flashctx, struct walk_info *const info, - const per_blockfn_t per_blockfn, bool *all_skipped) -{ - const struct flashrom_layout *const layout = get_layout(flashctx); - const struct romentry *entry = NULL; - - *all_skipped = true; - msg_cinfo("Erasing and writing flash chip... "); - - while ((entry = layout_next_included(layout, entry))) { - const struct flash_region *region = &entry->region; - info->region_start = region->start; - info->region_end = region->end; - - size_t j; - int error = 1; /* retry as long as it's 1 */ - for (j = 0; j < NUM_ERASEFUNCTIONS; ++j) { - if (j != 0) - msg_cinfo("Looking for another erase function.\n"); - msg_cdbg("Trying erase function %zi... ", j); - if (check_block_eraser(flashctx, j, 1)) - continue; - - error = walk_eraseblocks(flashctx, info, j, per_blockfn, all_skipped); - if (error != 1) - break; - - if (info->curcontents) { - msg_cinfo("Reading current flash chip contents... "); - if (read_by_layout(flashctx, info->curcontents)) { - /* Now we are truly screwed. Read failed as well. */ - msg_cerr("Can't read anymore! Aborting.\n"); - /* We have no idea about the flash chip contents, so - retrying with another erase function is pointless. */ - error = 2; - break; - } - msg_cinfo("done. "); - } - } - if (error == 1) - msg_cinfo("No usable erase functions left.\n"); - if (error) { - msg_cerr("FAILED!\n"); - return 1; - } - } - if (*all_skipped) - msg_cinfo("\nWarning: Chip content is identical to the requested image.\n"); - msg_cinfo("Erase/write done.\n"); - return 0; -} - -static int erase_block(struct flashctx *const flashctx, - const struct walk_info *const info, const erasefn_t erasefn, - bool *all_skipped) -{ - const unsigned int erase_len = info->erase_end + 1 - info->erase_start; - const bool region_unaligned = info->region_start > info->erase_start || - info->erase_end > info->region_end; - uint8_t *backup_contents = NULL, *erased_contents = NULL; - int ret = 2; - - /* - * If the region is not erase-block aligned, merge current flash con- - * tents into a new buffer `backup_contents`. - */ - if (region_unaligned) { - backup_contents = malloc(erase_len); - erased_contents = malloc(erase_len); - if (!backup_contents || !erased_contents) { - msg_cerr("Out of memory!\n"); - ret = 1; - goto _free_ret; - } - memset(backup_contents, ERASED_VALUE(flashctx), erase_len); - memset(erased_contents, ERASED_VALUE(flashctx), erase_len); - - msg_cdbg("R"); - /* Merge data preceding the current region. */ - if (info->region_start > info->erase_start) { - const chipoff_t start = info->erase_start; - const chipsize_t len = info->region_start - info->erase_start; - if (read_flash(flashctx, backup_contents, start, len)) { - msg_cerr("Can't read! Aborting.\n"); - goto _free_ret; - } - } - /* Merge data following the current region. */ - if (info->erase_end > info->region_end) { - const chipoff_t start = info->region_end + 1; - const chipoff_t rel_start = start - info->erase_start; /* within this erase block */ - const chipsize_t len = info->erase_end - info->region_end; - if (read_flash(flashctx, backup_contents + rel_start, start, len)) { - msg_cerr("Can't read! Aborting.\n"); - goto _free_ret; - } - } - } - - ret = 1; - *all_skipped = false; - - msg_cdbg("E"); - - if (!flashctx->flags.skip_unwritable_regions) { - if (check_for_unwritable_regions(flashctx, info->erase_start, erase_len)) - goto _free_ret; - } - - unsigned int len; - for (unsigned int addr = info->erase_start; addr < info->erase_start + erase_len; addr += len) { - struct flash_region region; - get_flash_region(flashctx, addr, &region); - - len = min(info->erase_start + erase_len, region.end + 1) - addr; - - if (region.write_prot) { - msg_gdbg("%s: cannot erase inside %s region (%#08"PRIx32"..%#08"PRIx32"), skipping range (%#08x..%#08x).\n", - __func__, region.name, region.start, region.end, addr, addr + len - 1); - free(region.name); - continue; - } - - msg_gdbg("%s: %s region (%#08"PRIx32"..%#08"PRIx32") is writable, erasing range (%#08x..%#08x).\n", - __func__, region.name, region.start, region.end, addr, addr + len - 1); - free(region.name); - - if (erasefn(flashctx, addr, len)) - goto _free_ret; - if (check_erased_range(flashctx, addr, len)) { - msg_cerr("ERASE FAILED!\n"); - goto _free_ret; - } - } - - - if (region_unaligned) { - unsigned int starthere = 0, lenhere = 0, writecount = 0; - /* get_next_write() sets starthere to a new value after the call. */ - while ((lenhere = get_next_write(erased_contents + starthere, backup_contents + starthere, - erase_len - starthere, &starthere, flashctx->chip->gran))) { - if (!writecount++) - msg_cdbg("W"); - /* Needs the partial write function signature. */ - if (write_flash(flashctx, backup_contents + starthere, - info->erase_start + starthere, lenhere)) - goto _free_ret; - starthere += lenhere; - } - } - - ret = 0; - -_free_ret: - free(erased_contents); - free(backup_contents); - return ret; -} - -/** - * @brief Erases the included layout regions. - * - * If there is no layout set in the given flash context, the whole chip will - * be erased. - * - * @param flashctx Flash context to be used. - * @return 0 on success, - * 1 if all available erase functions failed. - */ -static int erase_by_layout_legacy(struct flashctx *const flashctx) -{ - struct walk_info info = { 0 }; - bool all_skipped = true; - return walk_by_layout(flashctx, &info, &erase_block, &all_skipped); -} static int erase_by_layout_new(struct flashctx *const flashctx) { @@ -1618,129 +1374,9 @@ static int erase_by_layout(struct flashctx *const flashctx) { - if (use_legacy_erase_path) - return erase_by_layout_legacy(flashctx); return erase_by_layout_new(flashctx); } -static int read_erase_write_block(struct flashctx *const flashctx, - const struct walk_info *const info, const erasefn_t erasefn, - bool *all_skipped) -{ - const chipsize_t erase_len = info->erase_end + 1 - info->erase_start; - const bool region_unaligned = info->region_start > info->erase_start || - info->erase_end > info->region_end; - const uint8_t *newcontents = NULL; - int ret = 2; - - /* - * If the region is not erase-block aligned, merge current flash con- - * tents into `info->curcontents` and a new buffer `newc`. The former - * is necessary since we have no guarantee that the full erase block - * was already read into `info->curcontents`. For the latter a new - * buffer is used since `info->newcontents` might contain data for - * other unaligned regions that touch this erase block too. - */ - if (region_unaligned) { - msg_cdbg("R"); - uint8_t *const newc = malloc(erase_len); - if (!newc) { - msg_cerr("Out of memory!\n"); - return 1; - } - memcpy(newc, info->newcontents + info->erase_start, erase_len); - - /* Merge data preceding the current region. */ - if (info->region_start > info->erase_start) { - const chipoff_t start = info->erase_start; - const chipsize_t len = info->region_start - info->erase_start; - if (read_flash(flashctx, newc, start, len)) { - msg_cerr("Can't read! Aborting.\n"); - goto _free_ret; - } - memcpy(info->curcontents + start, newc, len); - } - /* Merge data following the current region. */ - if (info->erase_end > info->region_end) { - const chipoff_t start = info->region_end + 1; - const chipoff_t rel_start = start - info->erase_start; /* within this erase block */ - const chipsize_t len = info->erase_end - info->region_end; - if (read_flash(flashctx, newc + rel_start, start, len)) { - msg_cerr("Can't read! Aborting.\n"); - goto _free_ret; - } - memcpy(info->curcontents + start, newc + rel_start, len); - } - - newcontents = newc; - } else { - newcontents = info->newcontents + info->erase_start; - } - - ret = 1; - bool skipped = true; - uint8_t *const curcontents = info->curcontents + info->erase_start; - const uint8_t erased_value = ERASED_VALUE(flashctx); - if (!(flashctx->chip->feature_bits & FEATURE_NO_ERASE) && - need_erase(curcontents, newcontents, erase_len, flashctx->chip->gran, erased_value)) { - if (erase_block(flashctx, info, erasefn, all_skipped)) - goto _free_ret; - /* Erase was successful. Adjust curcontents. */ - memset(curcontents, erased_value, erase_len); - skipped = false; - } - - unsigned int starthere = 0, lenhere = 0, writecount = 0; - /* get_next_write() sets starthere to a new value after the call. */ - while ((lenhere = get_next_write(curcontents + starthere, newcontents + starthere, - erase_len - starthere, &starthere, flashctx->chip->gran))) { - if (!writecount++) - msg_cdbg("W"); - /* Needs the partial write function signature. */ - if (write_flash(flashctx, newcontents + starthere, - info->erase_start + starthere, lenhere)) - goto _free_ret; - starthere += lenhere; - skipped = false; - } - if (skipped) - msg_cdbg("S"); - else - *all_skipped = false; - - /* Update curcontents, other regions with overlapping erase blocks - might rely on this. */ - memcpy(curcontents, newcontents, erase_len); - ret = 0; - -_free_ret: - if (region_unaligned) - free((void *)newcontents); - return ret; -} - -/** - * @brief Writes the included layout regions from a given image. - * - * If there is no layout set in the given flash context, the whole image - * will be written. - * - * @param flashctx Flash context to be used. - * @param curcontents A buffer of full chip size with current chip contents of included regions. - * @param newcontents The new image to be written. - * @return 0 on success, - * 1 if anything has gone wrong. - */ -static int write_by_layout_legacy(struct flashctx *const flashctx, - void *const curcontents, const void *const newcontents, - bool *all_skipped) -{ - struct walk_info info; - info.curcontents = curcontents; - info.newcontents = newcontents; - return walk_by_layout(flashctx, &info, read_erase_write_block, all_skipped); -} - static int write_by_layout_new(struct flashctx *const flashctx, void *const curcontents, const void *const newcontents, bool *all_skipped) @@ -1780,8 +1416,6 @@ uint8_t *const curcontents, const uint8_t *const newcontents, bool *all_skipped) { - if (use_legacy_erase_path) - return write_by_layout_legacy(flashctx, curcontents, newcontents, all_skipped); return write_by_layout_new(flashctx, curcontents, newcontents, all_skipped); } -- To view, visit https://review.coreboot.org/c/flashrom/+/83846?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I08fd686fecf6a5313eea2d66b368661c664f4800 Gerrit-Change-Number: 83846 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>

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[M] Change in flashrom[main]: doc: Convert the doc for MSI JSPI1
by Anastasia Klimchuk (Code Review) 09 Aug '24

09 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83753?usp=email ) Change subject: doc: Convert the doc for MSI JSPI1 ...................................................................... doc: Convert the doc for MSI JSPI1 The doc converted from https://wiki.flashrom.org/MSI_JSPI1 Change-Id: Idd215a3a3a4d62629803a71d360755c43c1ab599 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83753 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> --- M doc/user_docs/index.rst A doc/user_docs/msi_jspi1.rst 2 files changed, 53 insertions(+), 0 deletions(-) Approvals: David Hendricks: Looks good to me, approved build bot (Jenkins): Verified diff --git a/doc/user_docs/index.rst b/doc/user_docs/index.rst index 6eadfa4..e03789e 100644 --- a/doc/user_docs/index.rst +++ b/doc/user_docs/index.rst @@ -11,4 +11,7 @@ management_engine misc_intel in_system + msi_jspi1 misc_notes + +.. Keep misc notes last diff --git a/doc/user_docs/msi_jspi1.rst b/doc/user_docs/msi_jspi1.rst new file mode 100644 index 0000000..dc20866 --- /dev/null +++ b/doc/user_docs/msi_jspi1.rst @@ -0,0 +1,50 @@ +========= +MSI JSPI1 +========= + +JSPI1 is a 5x2 or 6x2 2.0mm pitch pin header on many MSI motherboards. +It is used to recover from bad boot ROM images. Specifically, +it appears to be used to connect an alternate ROM with a working image. +Pull the #HOLD line low to deselect the onboard SPI ROM, allowing another +SPI ROM to take its place on the bus. Pull the #WP line high to disable write-protection. +Some boards use 1.8V flash chips, while others use 3.3V flash chips; +Check the flash chip datasheet to determine the correct value. + +**JSPI1 (5x2)** + +======== ======== ======== ==== +name pin pin name +======== ======== ======== ==== +VCC 1 2 VCC +MISO 3 4 MOSI +#SS 5 6 SCLK +GND 7 8 GND +#HOLD 9 10 NC +======== ======== ======== ==== + +**JSPI1 (6x2)** + +======== ======== ======== ============ +name pin pin name +======== ======== ======== ============ +VCC 1 2 VCC +SO 3 4 SI +#SS 5 6 CLK +GND 7 8 GND +NC 9 10 NC (no pin) +#WP 11 12 #HOLD +======== ======== ======== ============ + +======== ===================================== +name function +======== ===================================== +VCC Voltage (See flash chip datasheet) +MISO SPI Master In/Slave Out +MOSI SPI Master Out/Slave In +#SS SPI Slave (Chip) Select (active low) +SCLK SPI Clock +GND ground/common +#HOLD SPI hold (active low) +#WP SPI write-protect (active low) +NC Not Connected (or no pin) +======== ===================================== -- To view, visit https://review.coreboot.org/c/flashrom/+/83753?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Idd215a3a3a4d62629803a71d360755c43c1ab599 Gerrit-Change-Number: 83753 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in flashrom[main]: tree: Retype variable `is_laptop` to enum
by Aarya (Code Review) 08 Aug '24

08 Aug '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/83834?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: tree: Retype variable `is_laptop` to enum ...................................................................... tree: Retype variable `is_laptop` to enum Use enum instead of integer for the variable `is_laptop`. Change-Id: I47b7611a08bdf9992131cab57ee386fd59d147d3 Signed-off-by: Aarya Chaumal <aarya.chaumal(a)gmail.com> --- M board_enable.c M dmi.c M include/programmer.h M internal.c 4 files changed, 38 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/83834/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/83834?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I47b7611a08bdf9992131cab57ee386fd59d147d3 Gerrit-Change-Number: 83834 Gerrit-PatchSet: 3 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in flashrom[main]: tree: Retype variable `is_laptop` to enum
by Aarya (Code Review) 08 Aug '24

08 Aug '24

Aarya has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83834?usp=email ) Change subject: tree: Retype variable `is_laptop` to enum ...................................................................... tree: Retype variable `is_laptop` to enum Use enum instead of integer for the variable `is_laptop`. Change-Id: I47b7611a08bdf9992131cab57ee386fd59d147d3 Signed-off-by: Aarya Chaumal <aarya.chaumal(a)gmail.com> --- M board_enable.c M dmi.c M include/programmer.h M internal.c 4 files changed, 38 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/83834/1 diff --git a/board_enable.c b/board_enable.c index 6e48a62..b039413 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2282,7 +2282,7 @@ static int p2_not_a_laptop(struct board_cfg *cfg) { /* label this board as not a laptop */ - cfg->is_laptop = 0; + cfg->is_laptop = NO; msg_pdbg("Laptop detection overridden by P2 board enable.\n"); return 0; } @@ -2292,7 +2292,7 @@ */ static int p2_whitelist_laptop(struct board_cfg *cfg) { - cfg->is_laptop = 1; + cfg->is_laptop = YES; cfg->laptop_ok = true; msg_pdbg("Whitelisted laptop detected.\n"); return 0; diff --git a/dmi.c b/dmi.c index 94e47fb..ab64438 100644 --- a/dmi.c +++ b/dmi.c @@ -74,24 +74,24 @@ */ static const struct { uint8_t type; - uint8_t is_laptop; + enum is_laptop is_laptop; const char *name; } dmi_chassis_types[] = { - {0x01, 2, "Other"}, - {0x02, 2, "Unknown"}, - {0x03, 0, "Desktop"}, - {0x04, 0, "Low Profile Desktop"}, - {0x06, 0, "Mini Tower"}, - {0x07, 0, "Tower"}, - {0x08, 1, "Portable"}, - {0x09, 1, "Laptop"}, - {0x0a, 1, "Notebook"}, - {0x0b, 1, "Hand Held"}, - {0x0e, 1, "Sub Notebook"}, - {0x11, 0, "Main Server Chassis"}, - {0x17, 0, "Rack Mount Chassis"}, - {0x18, 0, "Sealed-case PC"}, /* used by Supermicro (X8SIE) */ - {0x19, 0, "Multi-system"}, /* used by Supermicro (X7DWT) */ + {0x01, UNKNOWN, "Other"}, + {0x02, UNKNOWN, "Unknown"}, + {0x03, NO, "Desktop"}, + {0x04, NO, "Low Profile Desktop"}, + {0x06, NO, "Mini Tower"}, + {0x07, NO, "Tower"}, + {0x08, YES, "Portable"}, + {0x09, YES, "Laptop"}, + {0x0a, YES, "Notebook"}, + {0x0b, YES, "Hand Held"}, + {0x0e, YES, "Sub Notebook"}, + {0x11, NO, "Main Server Chassis"}, + {0x17, NO, "Rack Mount Chassis"}, + {0x18, NO, "Sealed-case PC"}, /* used by Supermicro (X8SIE) */ + {0x19, NO, "Multi-system"}, /* used by Supermicro (X7DWT) */ }; #if CONFIG_INTERNAL_DMI == 1 @@ -151,11 +151,11 @@ return newbuf; } -static int dmi_chassis_type(uint8_t code) +static enum is_laptop dmi_chassis_type(uint8_t code) { unsigned int i; code &= 0x7f; /* bits 6:0 are chassis type, 7th bit is the lock bit */ - int is_laptop = 2; + enum is_laptop is_laptop = UNKNOWN; for (i = 0; i < ARRAY_SIZE(dmi_chassis_types); i++) { if (code == dmi_chassis_types[i].type) { msg_pdbg("DMI string chassis-type: \"%s\"\n", dmi_chassis_types[i].name); @@ -166,7 +166,7 @@ return is_laptop; } -static void dmi_table(uint32_t base, uint16_t len, uint16_t num, int *is_laptop) +static void dmi_table(uint32_t base, uint16_t len, uint16_t num, enum is_laptop *is_laptop) { unsigned int i = 0, j = 0; @@ -233,7 +233,7 @@ } #if SM_SUPPORT -static int smbios_decode(uint8_t *buf, int *is_laptop) +static int smbios_decode(uint8_t *buf, enum is_laptop *is_laptop) { /* TODO: other checks mentioned in the conformance guidelines? */ if (!dmi_checksum(buf, buf[0x05]) || @@ -247,7 +247,7 @@ } #endif -static int legacy_decode(uint8_t *buf, int *is_laptop) +static int legacy_decode(uint8_t *buf, enum is_laptop *is_laptop) { if (!dmi_checksum(buf, 0x0F)) return 1; @@ -257,7 +257,7 @@ return 0; } -static int dmi_fill(int *is_laptop) +static int dmi_fill(enum is_laptop *is_laptop) { size_t fp; uint8_t *dmi_mem; @@ -351,7 +351,7 @@ return result; } -static int dmi_fill(int *is_laptop) +static int dmi_fill(enum is_laptop *is_laptop) { unsigned int i; char *chassis_type; @@ -368,7 +368,7 @@ return 0; /* chassis-type handling is optional anyway */ msg_pdbg("DMI string chassis-type: \"%s\"\n", chassis_type); - *is_laptop = 2; + *is_laptop = UNKNOWN; for (i = 0; i < ARRAY_SIZE(dmi_chassis_types); i++) { if (strcasecmp(chassis_type, dmi_chassis_types[i].name) == 0) { *is_laptop = dmi_chassis_types[i].is_laptop; @@ -392,7 +392,7 @@ return 0; } -void dmi_init(int *is_laptop) +void dmi_init(enum is_laptop *is_laptop) { /* Register shutdown function before we allocate anything. */ if (register_shutdown(dmi_shutdown, NULL)) { @@ -405,12 +405,14 @@ return; switch (*is_laptop) { - case 1: + case YES: msg_pdbg("Laptop detected via DMI.\n"); break; - case 2: + case UNKNOWN: msg_pdbg("DMI chassis-type is not specific enough.\n"); break; + default: + break; } g_has_dmi_support = true; diff --git a/include/programmer.h b/include/programmer.h index 3b1ebeb..dd13a9e 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -171,7 +171,7 @@ }; struct board_cfg { - int is_laptop; + enum is_laptop is_laptop; bool laptop_ok; }; @@ -257,7 +257,7 @@ /* dmi.c */ #if defined(__i386__) || defined(__x86_64__) -void dmi_init(int *is_laptop); +void dmi_init(enum is_laptop *is_laptop); bool dmi_is_supported(void); int dmi_match(const char *pattern); #endif // defined(__i386__) || defined(__x86_64__) diff --git a/internal.c b/internal.c index faeb463..647f730 100644 --- a/internal.c +++ b/internal.c @@ -107,14 +107,14 @@ static void report_nonwl_laptop_detected(const struct board_cfg *bcfg) { - const int is_laptop = bcfg->is_laptop; + const enum is_laptop is_laptop = bcfg->is_laptop; const bool laptop_ok = bcfg->laptop_ok; - if (!is_laptop || laptop_ok) + if ((is_laptop != YES) || laptop_ok) return; msg_pinfo("========================================================================\n"); - if (is_laptop == 1) { + if (is_laptop == YES) { msg_pinfo("You seem to be running flashrom on an unknown laptop. Some\n" "internal buses have been disabled for safety reasons.\n\n"); } else { @@ -202,7 +202,7 @@ } } - bcfg.is_laptop = 2; /* Assume that we don't know by default. */ + bcfg.is_laptop = UNKNOWN; /* Assume that we don't know by default. */ dmi_init(&bcfg.is_laptop); @@ -227,7 +227,7 @@ * this isn't a laptop. Board-enables may override this, * non-legacy buses (SPI and opaque atm) are probed anyway. */ - if (bcfg.is_laptop && !(bcfg.laptop_ok || force_laptop || (not_a_laptop && bcfg.is_laptop == 2))) + if ((bcfg.is_laptop == YES) && !(bcfg.laptop_ok || force_laptop || (not_a_laptop && bcfg.is_laptop == UNKNOWN))) internal_buses_supported = BUS_NONE; /* try to enable it. Failure IS an option, since not all motherboards -- To view, visit https://review.coreboot.org/c/flashrom/+/83834?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I47b7611a08bdf9992131cab57ee386fd59d147d3 Gerrit-Change-Number: 83834 Gerrit-PatchSet: 1 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com>

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[XS] Change in flashrom[main]: programmer.h: Introduce new enum for is_laptop
by Aarya (Code Review) 08 Aug '24

08 Aug '24

Aarya has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83833?usp=email ) Change subject: programmer.h: Introduce new enum for is_laptop ...................................................................... programmer.h: Introduce new enum for is_laptop Add new enum for `is_laptop` variable. The enum would take values NO, YES, UNKNOWN. Change-Id: I6b06e83fa5824cd4078f762195a99e0ce9fc3806 Signed-off-by: Aarya Chaumal <aarya.chaumal(a)gmail.com> --- M include/programmer.h 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/33/83833/1 diff --git a/include/programmer.h b/include/programmer.h index a90624b..3b1ebeb 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -164,6 +164,12 @@ P3 }; +enum is_laptop { + NO, + YES, + UNKNOWN, +}; + struct board_cfg { int is_laptop; bool laptop_ok; -- To view, visit https://review.coreboot.org/c/flashrom/+/83833?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I6b06e83fa5824cd4078f762195a99e0ce9fc3806 Gerrit-Change-Number: 83833 Gerrit-PatchSet: 1 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com>

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[XS] Change in flashrom[main]: doc: Fix the link to In-System programming doc
by Anastasia Klimchuk (Code Review) 08 Aug '24

08 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83761?usp=email ) Change subject: doc: Fix the link to In-System programming doc ...................................................................... doc: Fix the link to In-System programming doc Change-Id: Ic82be2b926b0d3a9de7d4b030bbef31c1b3746fb Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83761 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Peter Marheine <pmarheine(a)chromium.org> --- M doc/user_docs/overview.rst 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Peter Marheine: Looks good to me, approved diff --git a/doc/user_docs/overview.rst b/doc/user_docs/overview.rst index 1b3fe40..9825f22 100644 --- a/doc/user_docs/overview.rst +++ b/doc/user_docs/overview.rst @@ -185,7 +185,7 @@ Similarly to the DIP8 chips, these always use the SPI protocol. However, SO8/SOIC8 chips are most often soldered onto the board directly without a socket. -In that case a few boards have a header to allow :doc:`in-system`. You can also desolder +In that case a few boards have a header to allow :doc:`in_system`. You can also desolder a soldered SO8 chip and solder an SO8 socket/adapter in its place, or build a `SOIC-to-DIP adapter <http://blogs.coreboot.org/blog/2013/07/16/gsoc-2013-flashrom-week-4/>`_. Some of the cheapest SOIC ZIF sockets are made by `Wieson <https://www.wieson.com/go/en/wieson/index.php?lang=en>`_. -- To view, visit https://review.coreboot.org/c/flashrom/+/83761?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ic82be2b926b0d3a9de7d4b030bbef31c1b3746fb Gerrit-Change-Number: 83761 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in flashrom[main]: flashchip: add GD25LB512ME
by Victor Lim (Code Review) 07 Aug '24

07 Aug '24

Victor Lim has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83795?usp=email ) Change subject: flashchip: add GD25LB512ME ...................................................................... flashchip: add GD25LB512ME Added GD25LB512ME to Flashchip.C GD25LB512ME is 1.8V 512Mbit, Quad enabled when shipped. https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-0… Tested on ch347 with erase, program, read, and protection. Change-Id: I04103814f901478098c1a989f4239792b64073ec Signed-off-by: Victor <vlim(a)gigadevice.com> --- M flashchips.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/83795/1 diff --git a/flashchips.c b/flashchips.c index 0f0ac0b..1198ae4 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7068,7 +7068,7 @@ { .vendor = "GigaDevice", - .name = "GD25LR512ME", + .name = "GD25LB512ME/GD25LR512ME", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25LR512ME, @@ -7076,7 +7076,7 @@ .page_size = 256, /* OTP: 4096B total; read 0x48; write 0x42, erase 0x44 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_4BA, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PREWB, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, .block_erasers = -- To view, visit https://review.coreboot.org/c/flashrom/+/83795?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I04103814f901478098c1a989f4239792b64073ec Gerrit-Change-Number: 83795 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com>

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[M] Change in flashrom[main]: flashchips: add GD25LF256F
by Anastasia Klimchuk (Code Review) 06 Aug '24

06 Aug '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/83717?usp=email ) Change subject: flashchips: add GD25LF256F ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I21a71606476e823faa38a7920aa2b10e25d68d26 Gerrit-Change-Number: 83717 Gerrit-PatchSet: 4 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Tue, 06 Aug 2024 09:26:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in flashrom[main]: flashchips: add GD25LF256F
by Victor Lim (Code Review) 06 Aug '24

06 Aug '24

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer. Victor Lim has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/83717?usp=email ) Change subject: flashchips: add GD25LF256F ...................................................................... Patch Set 4: (4 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/83717/comment/2ca9b198_ad6316b7?us… : PS1, Line 13: I will have to email you the datasheet. > I got the datasheet, thank you! You can remove this sentence from commit message. Done https://review.coreboot.org/c/flashrom/+/83717/comment/4c914fe1_2e3ae2b6?us… : PS1, Line 15: protestion > A typo: protestion -> protection Done File flashchips.c: https://review.coreboot.org/c/flashrom/+/83717/comment/44d7e051_569acb73?us… : PS1, Line 6736: GD25LF256F > Could you please move this definition to be after GD25LF128E, in the same order as you did for IDs i […] Done https://review.coreboot.org/c/flashrom/+/83717/comment/d6cd8158_6998af28?us… : PS1, Line 6785: BP4 > Lets put the full comment here, as usual: […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/83717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I21a71606476e823faa38a7920aa2b10e25d68d26 Gerrit-Change-Number: 83717 Gerrit-PatchSet: 4 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Tue, 06 Aug 2024 00:21:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[M] Change in flashrom[main]: flashchips: add GD25LF256F
by Victor Lim (Code Review) 06 Aug '24

06 Aug '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/83717?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: flashchips: add GD25LF256F ...................................................................... flashchips: add GD25LF256F added GD25LF256F on flashchips.c added GIGADEVICE_GD25LF256F=0x6319 on flashchip.h GD25LF256F is a higher performance 1.8V 256Mbit SPI flash I have tested on CH347 with erase, program, read, protection. Change-Id: I21a71606476e823faa38a7920aa2b10e25d68d26 Signed-off-by: Victor <vlim(a)gigadevice.com> --- M flashchips.c M include/flashchips.h 2 files changed, 59 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/83717/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/83717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I21a71606476e823faa38a7920aa2b10e25d68d26 Gerrit-Change-Number: 83717 Gerrit-PatchSet: 4 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com>

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