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[XS] Change in flashrom[main]: doc: Fix the link to In-System programming doc
by Anastasia Klimchuk (Code Review) 03 Aug '24

03 Aug '24

Attention is currently required from: Peter Marheine. Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83761?usp=email ) Change subject: doc: Fix the link to In-System programming doc ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I messed up the link :( -- To view, visit https://review.coreboot.org/c/flashrom/+/83761?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ic82be2b926b0d3a9de7d4b030bbef31c1b3746fb Gerrit-Change-Number: 83761 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Sat, 03 Aug 2024 13:49:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in flashrom[main]: doc: Fix the link to In-System programming doc
by Anastasia Klimchuk (Code Review) 03 Aug '24

03 Aug '24

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83761?usp=email ) Change subject: doc: Fix the link to In-System programming doc ...................................................................... doc: Fix the link to In-System programming doc Change-Id: Ic82be2b926b0d3a9de7d4b030bbef31c1b3746fb Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M doc/user_docs/overview.rst 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/61/83761/1 diff --git a/doc/user_docs/overview.rst b/doc/user_docs/overview.rst index 1b3fe40..9825f22 100644 --- a/doc/user_docs/overview.rst +++ b/doc/user_docs/overview.rst @@ -185,7 +185,7 @@ Similarly to the DIP8 chips, these always use the SPI protocol. However, SO8/SOIC8 chips are most often soldered onto the board directly without a socket. -In that case a few boards have a header to allow :doc:`in-system`. You can also desolder +In that case a few boards have a header to allow :doc:`in_system`. You can also desolder a soldered SO8 chip and solder an SO8 socket/adapter in its place, or build a `SOIC-to-DIP adapter <http://blogs.coreboot.org/blog/2013/07/16/gsoc-2013-flashrom-week-4/>`_. Some of the cheapest SOIC ZIF sockets are made by `Wieson <https://www.wieson.com/go/en/wieson/index.php?lang=en>`_. -- To view, visit https://review.coreboot.org/c/flashrom/+/83761?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ic82be2b926b0d3a9de7d4b030bbef31c1b3746fb Gerrit-Change-Number: 83761 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>

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[S] Change in flashrom[main]: flashchips: add support for MX77U51250F chip
by Anastasia Klimchuk (Code Review) 03 Aug '24

03 Aug '24

Attention is currently required from: Bora Guvendik, DZ, Nikolai Artemiev, Stefan Reinauer, Subrata Banik. Anastasia Klimchuk has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/flashrom/+/82626?usp=email ) Change subject: flashchips: add support for MX77U51250F chip ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Bora, I just wanted to remind that now it's your turn to action on the patch. We did the review collectively, you need to go through all unresolved comments and resolve them. Then upload the new patchset, reply to comments, and then reviewers can look at the patch again. If you have any questions, you are welcome to ask. Thank you! -- To view, visit https://review.coreboot.org/c/flashrom/+/82626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I2c2e94f01dc63f60cf636bc6afe1f033e2a6f83c Gerrit-Change-Number: 82626 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: DZ <danielzhang(a)mxic.com.cn> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: DZ <danielzhang(a)mxic.com.cn> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Sat, 03 Aug 2024 09:51:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in flashrom[main]: doc: Add overview doc for user_docs
by Anastasia Klimchuk (Code Review) 03 Aug '24

03 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83584?usp=email ) Change subject: doc: Add overview doc for user_docs ...................................................................... doc: Add overview doc for user_docs This document is converted from Technology page on wiki https://wiki.flashrom.org/Technology Change-Id: I93107d6b5530c301dd90f7177758632d9d1810eb Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83584 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M doc/intro.rst A doc/user_docs/Amd_am29f010_tsop32.jpg A doc/user_docs/Bios_savior.jpg A doc/user_docs/Dip32_chip.jpg A doc/user_docs/Dip32_chip_back.jpg A doc/user_docs/Dip32_in_socket.jpg A doc/user_docs/Dip8_chip.jpg A doc/user_docs/Dip8_chip_back.jpg A doc/user_docs/Dip8_in_socket.jpg A doc/user_docs/Dip_tool.jpg A doc/user_docs/Dual_plcc32_soldered.jpg A doc/user_docs/Empty_dip32_socket.jpg A doc/user_docs/Empty_dip8_socket.jpg A doc/user_docs/Empty_plcc32_socket.jpg A doc/user_docs/Flash-BGA.jpg A doc/user_docs/Plcc32_chip.jpg A doc/user_docs/Plcc32_chip_back.jpg A doc/user_docs/Plcc32_in_socket.jpg A doc/user_docs/Plcc_tool.jpg A doc/user_docs/Pushpin_roms_2.jpg A doc/user_docs/Soic8_chip.jpg A doc/user_docs/Soic8_socket_back.jpg A doc/user_docs/Soic8_socket_front_closed.jpg A doc/user_docs/Soic8_socket_half_opened.jpg A doc/user_docs/Soic8_socket_open.jpg A doc/user_docs/Soic8_socket_with_chip.jpg A doc/user_docs/Soic8_socket_with_chip_inserted.jpg A doc/user_docs/Soldered_plcc32.jpg A doc/user_docs/Soldered_tsop40.jpg A doc/user_docs/Soldered_tsop48.jpg A doc/user_docs/Spi-socket-dscn2913-1024x768.jpg A doc/user_docs/Sst_39vf040_tsop32.jpg A doc/user_docs/Top_hat_flash.jpeg M doc/user_docs/index.rst A doc/user_docs/overview.rst 35 files changed, 303 insertions(+), 1 deletion(-) Approvals: Stefan Reinauer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/doc/intro.rst b/doc/intro.rst index b9a2c97..92bcac5 100644 --- a/doc/intro.rst +++ b/doc/intro.rst @@ -7,7 +7,7 @@ For more information, see the pages under :doc:`/supported_hw/index`. * Supports parallel, LPC, FWH and SPI flash interfaces and various chip packages (DIP32, - PLCC32, DIP8, SO8/SOIC8, TSOP32, TSOP40, TSOP48, BGA and more). + PLCC32, DIP8, SO8/SOIC8, TSOP32, TSOP40, TSOP48, BGA and more), see :doc:`user_docs/overview`. * No physical access needed, root access is sufficient (not needed for some programmers). diff --git a/doc/user_docs/Amd_am29f010_tsop32.jpg b/doc/user_docs/Amd_am29f010_tsop32.jpg new file mode 100644 index 0000000..faf0982 --- /dev/null +++ b/doc/user_docs/Amd_am29f010_tsop32.jpg Binary files differ diff --git a/doc/user_docs/Bios_savior.jpg b/doc/user_docs/Bios_savior.jpg new file mode 100644 index 0000000..91d5557 --- /dev/null +++ b/doc/user_docs/Bios_savior.jpg Binary files differ diff --git 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a/doc/user_docs/Top_hat_flash.jpeg b/doc/user_docs/Top_hat_flash.jpeg new file mode 100644 index 0000000..8edd27e --- /dev/null +++ b/doc/user_docs/Top_hat_flash.jpeg Binary files differ diff --git a/doc/user_docs/index.rst b/doc/user_docs/index.rst index 3ca928a..6eadfa4 100644 --- a/doc/user_docs/index.rst +++ b/doc/user_docs/index.rst @@ -4,6 +4,7 @@ .. toctree:: :maxdepth: 1 + overview fw_updates_vs_spi_wp example_partial_wp chromebooks diff --git a/doc/user_docs/overview.rst b/doc/user_docs/overview.rst new file mode 100644 index 0000000..1b3fe40 --- /dev/null +++ b/doc/user_docs/overview.rst @@ -0,0 +1,301 @@ +========== +Overview +========== + +Modern mainboards store the BIOS in a reprogrammable flash chip. +There are hundreds of different flash (`EEPROM <https://en.wikipedia.org/wiki/EEPROM>`_) chips, +with variables such as memory size, speed, communication bus (Parallel, LPC, FWH, SPI) and packaging to name just a few. + +Packaging/housing/form factor +============================= + +DIP32: Dual In-line Package, 32 pins +------------------------------------ + +DIP32 top + +.. image:: Dip32_chip.jpg + :alt: DIP32 top + +DIP32 bottom + +.. image:: Dip32_chip_back.jpg + :alt: DIP32 bottom + +DIP32 in a socket + +.. image:: Dip32_in_socket.jpg + :alt: DIP32 in a socket + +DIP32 socket + +.. image:: Empty_dip32_socket.jpg + :alt: DIP32 socket + +DIP32 extractor tool + +.. image:: Dip_tool.jpg + :alt: DIP32 extractor tool + +A rectangular black plastic block with 16 pins along each of the two longer sides of the package +(32 pins in total). DIP32 chips can be socketed which means they are detachable from the mainboard +using physical force. If they haven't been moved in and out of the socket very much, +they can appear to be quite difficult to release from the socket. One way to remove a DIP32 chip +from a socket is by prying a **thin screwdriver** in between the plastic package and the socket, +along the shorter sides where there are no pins, and then gently bending the screwdriver to push +the chip upwards, away from the mainboard. Alternate between the two sides to avoid bending the pins, +and don't touch any of the pins with the screwdriver (search about ESD, electro-static discharge). +If the chip is **soldered directly to the mainboard**, it has to be desoldered in order to be +reprogrammed outside the mainboard. If you do this, it's a good idea to +`solder a socket to the mainboard <http://www.coreboot.org/Soldering_a_socket_on_your_board>`_ instead, +to ease any future experiments. + +PLCC32: Plastic Leaded Chip Carrier, 32 pins +-------------------------------------------- + +PLCC32 top + + .. image:: Plcc32_chip.jpg + :alt: PLCC32 top + +PLCC32 botto + + .. image:: Plcc32_chip_back.jpg + :alt: PLCC32 bottom + +PLCC32 socket + + .. image:: Plcc32_in_socket.jpg + :alt: PLCC32 socket + +PLCC32 in a socket + + .. image:: Empty_plcc32_socket.jpg + :alt: PLCC32 in a socket + +Soldered PLCC3 + + .. image:: Soldered_plcc32.jpg + :alt: Soldered PLCC32 + +Two soldered PLCC32 + + .. image:: Dual_plcc32_soldered.jpg + :alt: Two soldered PLCC32 + +PLCC32 Bios Savior + + .. image:: Bios_savior.jpg + :alt: PLCC32 Bios Savior + +PLCC32 Top-Hat-Flash adapte + + .. image:: Top_hat_flash.jpeg + :alt: PLCC32 Top-Hat-Flash adapter + +PLCC32 pushpin trick + + .. image:: Pushpin_roms_2.jpg + :alt: PLCC32 pushpin trick + +PLCC extractor tool + + .. image:: Plcc_tool.jpg + :alt: PLCC extractor tool + +Black plastic block again, but this one is much more square. +PLCC32 was becoming the standard for mainboards after DIP32 chips because of its smaller physical size. +PLCC can also be **socketed** or **soldered directly to the mainboard**. +Socketed PLCC32 chips can be removed using a special PLCC removal tool, +or using a piece of nylon line tied in a loop around the chip and pulled swiftly straight up, +or bending/prying using small screwdrivers if one is careful. PLCC32 sockets are often fragile +so the screwdriver approach is not recommended. While the nylon line method sounds strange it works well. +Desoldering PLCC32 chips and soldering on a socket can be done using either a desoldering station +or even just a heat gun. You can also cut the chip with a sharp knife, **but it will be destroyed in the process, of course**. + +DIP8: Dual In-line Package, 8 pins +---------------------------------- + +DIP8 top + + .. image:: Dip8_chip.jpg + :alt: DIP8 top + +DIP8 bottom + + .. image:: Dip8_chip_back.jpg + :alt: DIP8 bottom + +DIP8 in a socket + + .. image:: Dip8_in_socket.jpg + :alt: DIP8 in a socket + +DIP8 socket + + .. image:: Empty_dip8_socket.jpg + :alt: DIP8 socket + +Most recent boards use DIP8 chips (which always employ the SPI protocol) or SO8/SOIC8 chips (see below). +DIP8 chips are always **socketed**, and can thus be easily removed (and hot-swapped), +for example using a small screwdriver. This allows for relatively simple recovery in case of an incorrectly flashed chip. + +SO8/SOIC8: Small-Outline Integrated Circuit, 8 pins +--------------------------------------------------- + +Soldered SOIC8 + + .. image:: Soic8_chip.jpg + :alt: Soldered SOIC8 + +SOIC8 socket, front, closed + + .. image:: Soic8_socket_front_closed.jpg + :alt: SOIC8 socket, front, closed + +SOIC8 socket, half open + + .. image:: Soic8_socket_half_opened.jpg + :alt: SOIC8 socket, half open + +SOIC8 socket, open + + .. image:: Soic8_socket_open.jpg + :alt: SOIC8 socket, open + +SOIC8 socket, back + + .. image:: Soic8_socket_back.jpg + :alt: SOIC8 socket, back + +SOIC8 socket, chip nearby + + .. image:: Soic8_socket_with_chip.jpg + :alt: SOIC8 socket, chip nearby + +SOIC8 socket, chip inserted + + .. image:: Soic8_socket_with_chip_inserted.jpg + :alt: SOIC8 socket, chip inserted + +Another type of SOIC8 adapter + + .. image:: Spi-socket-dscn2913-1024x768.jpg + :alt: Another type of SOIC8 adapter + +Similarly to the DIP8 chips, these always use the SPI protocol. +However, SO8/SOIC8 chips are most often soldered onto the board directly without a socket. +In that case a few boards have a header to allow :doc:`in-system`. You can also desolder +a soldered SO8 chip and solder an SO8 socket/adapter in its place, or build +a `SOIC-to-DIP adapter <http://blogs.coreboot.org/blog/2013/07/16/gsoc-2013-flashrom-week-4/>`_. +Some of the cheapest SOIC ZIF sockets are made by `Wieson <https://www.wieson.com/go/en/wieson/index.php?lang=en>`_. +They have 3 models available - G6179-10(0000), G6179-20(0000) and a 16 pin version named G6179-07(0000). +They are available for example from `siliconkit <https://siliconkit.com/oc3/>`_, +`Dediprog <https://www.dediprog.com/>`_, as well as `alibaba <http://alibaba.com/>`_. +For the usual "BIOS" flash chips you want the G6179-10 model (look also for G6179-100000). +Dediprog usually has them or similar ones as well but has steep shipping costs and an unpractical minimum order quantity. + +TSOP: Thin Small-Outline Package, 32, 40, or 48 pins +---------------------------------------------------- + +Soldered TSOP32 + + .. image:: Amd_am29f010_tsop32.jpg + :alt: Soldered TSOP32 + +Soldered TSOP32 + + .. image:: Sst_39vf040_tsop32.jpg + :alt: Soldered TSOP32 + +Soldered TSOP40 + + .. image:: Soldered_tsop40.jpg + :alt: Soldered TSOP40 + +Soldered TSOP48 + + .. image:: Soldered_tsop48.jpg + :alt: Soldered TSOP48 + +TSOPs are often used in embedded systems where size is important and there is no need +for replacement in the field. It is possible to (de)solder TSOPs by hand, +but it's not trivial and a reasonable amount of soldering skills are required. + +BGA: Ball Grid Array +-------------------- + +BGA package flash + + .. image:: Flash-BGA.jpg + :alt: BGA package flash + +BGAs are often used in embedded systems where size is important and there is no need +for replacement in the field. It is not easily possible to (de)solder BGA by hand. + +Communication bus protocol +========================== + +There are four major communication bus protocols for flash chips, +each with multiple subtle variants in the command set: + +* **SPI**: Serial Peripheral Interface, introduced ca. 2006. +* **Parallel**: The oldest flash bus, phased out on mainboards around 2002. +* **LPC**: Low Pin Count, a standard introduced ca. 1998. +* **FWH**: Firmware Hub, a variant of the LPC standard introduced at the same time. + FWH is a special case variant of LPC with one bit set differently in the memory read/write commands. + That means some data sheets mention the chips speak LPC although + they will not respond to regular LPC read/write cycles. + +Here's an attempt to create a marketing language -> chip type mapping: + +* JEDEC Flash -> Parallel (well, mostly) +* FWH -> FWH +* Firmware Hub -> FWH +* LPC Firmware -> FWH +* Firmware Memory -> FWH +* Low Pin Count (if Firmware/FWH is not mentioned) -> LPC +* LPC (if Firmware is not mentioned) -> LPC +* Serial Flash -> SPI + +SST data sheets have the following conventions: + +* LPC Memory Read -> LPC +* Firmware Memory Read -> FWH + +If both are mentioned, the chip supports both. + +If you're not sure about whether a device is LPC or FWH, look at the read/write cycle definitions. + +FWH + +=========== ========== ============== ========================================================== +Clock Cycle Field Name Field contents Comments +=========== ========== ============== ========================================================== +1 START 1101/1110 1101 for READ, 1110 for WRITE. +2 IDSEL 0000 to 1111 IDSEL value to be shifted out to the chip. +3-9 IMADDR YYYY The address to be read/written. 7 cycles total == 28 bits. +10+ ... ... ... +=========== ========== ============== ========================================================== + +LPC + +=========== =================== ============== ========================================================== +Clock Cycle Field Name Field contents Comments +=========== =================== ============== ========================================================== +1 START 0000 ... +2 CYCLETYPE+DIRECTION 010X/011X 010X for READ, 011X for WRITE. X means "reserved". +3-10 ADDRESS YYYY The address to be read/written. 8 cycles total == 32 bits. +11+ ... ... ... +=========== =================== ============== ========================================================== + +Generally, a parallel flash chip will not speak any other protocols. +SPI flash chips also don't speak any other protocols. +LPC flash chips sometimes speak FWH as well and vice versa, +but they will not speak any protocols besides LPC/FWH. + +Hardware Redundancy +=================== +Gigabyte's DualBios: http://www.google.com/patents/US6892323 + +ASUS: http://www.google.com/patents/US8015449 -- To view, visit https://review.coreboot.org/c/flashrom/+/83584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I93107d6b5530c301dd90f7177758632d9d1810eb Gerrit-Change-Number: 83584 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in flashrom[main]: doc: Add overview doc for user_docs
by Anastasia Klimchuk (Code Review) 03 Aug '24

03 Aug '24

Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83584?usp=email ) Change subject: doc: Add overview doc for user_docs ...................................................................... Patch Set 2: (1 comment) File doc/user_docs/overview.rst: https://review.coreboot.org/c/flashrom/+/83584/comment/c35a2376_5339398b?us… : PS1, Line 188: :doc:`in-system` > the doc is in CB:83451 Done -- To view, visit https://review.coreboot.org/c/flashrom/+/83584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I93107d6b5530c301dd90f7177758632d9d1810eb Gerrit-Change-Number: 83584 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Aug 2024 08:43:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[M] Change in flashrom[main]: doc: Add doc for buspirate programmer
by Anastasia Klimchuk (Code Review) 03 Aug '24

03 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83471?usp=email ) Change subject: doc: Add doc for buspirate programmer ...................................................................... doc: Add doc for buspirate programmer Doc migrated from the wiki page: https://wiki.flashrom.org/Bus_Pirate Change-Id: I5a57f08ea3fce0c78d73aa61b85ff7b0cff450b8 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83471 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Reguera Garcia (Dreg) <regueragarciadavid(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- A doc/supported_hw/supported_prog/Buspirate_v3_back.jpg A doc/supported_hw/supported_prog/Buspirate_v3_front.jpg A doc/supported_hw/supported_prog/Lycom-pe115-flashrom-buspirate-2.jpg A doc/supported_hw/supported_prog/buspirate.rst M doc/supported_hw/supported_prog/index.rst 5 files changed, 79 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved David Reguera Garcia (Dreg): Looks good to me, approved diff --git a/doc/supported_hw/supported_prog/Buspirate_v3_back.jpg b/doc/supported_hw/supported_prog/Buspirate_v3_back.jpg new file mode 100644 index 0000000..3afb974 --- /dev/null +++ b/doc/supported_hw/supported_prog/Buspirate_v3_back.jpg Binary files differ diff --git a/doc/supported_hw/supported_prog/Buspirate_v3_front.jpg b/doc/supported_hw/supported_prog/Buspirate_v3_front.jpg new file mode 100644 index 0000000..3c4fa9c --- /dev/null +++ b/doc/supported_hw/supported_prog/Buspirate_v3_front.jpg Binary files differ diff --git a/doc/supported_hw/supported_prog/Lycom-pe115-flashrom-buspirate-2.jpg b/doc/supported_hw/supported_prog/Lycom-pe115-flashrom-buspirate-2.jpg new file mode 100644 index 0000000..5962fa9 --- /dev/null +++ b/doc/supported_hw/supported_prog/Lycom-pe115-flashrom-buspirate-2.jpg Binary files differ diff --git a/doc/supported_hw/supported_prog/buspirate.rst b/doc/supported_hw/supported_prog/buspirate.rst new file mode 100644 index 0000000..3d06470 --- /dev/null +++ b/doc/supported_hw/supported_prog/buspirate.rst @@ -0,0 +1,78 @@ +========== +Bus Pirate +========== + +The `Bus Pirate <http://dangerousprototypes.com/docs/Bus_Pirate>`_ is an open source design +for a multi-purpose chip-level serial protocol transceiver and debugger. +flashrom supports the Bus Pirate for `SPI programming <http://dangerousprototypes.com/docs/SPI>`_. +It also has `SPI sniffing <http://dangerousprototypes.com/docs/Bus_Pirate_binary_SPI_sniffer_utility>`_ +functionality, which may come in useful for analysing chip or programmer behaviour. + +They are available for around US$30 from various sources. + +Connections +=========== + +The table below shows how a typical SPI flash chip (sitting in the center of the table) +needs to be connected (NB: not all flash chips feature all of the pins below, but in general +you should always connect all input pins of ICs to some defined potential (usually GND or VCC), +ideally with a pull-up/down resistor in between). Most SPI flash chips require a 3.3V supply voltage, +but there exist some models that use e.g. 1.8V. Make sure the device in question is compatible +before connecting any wires. + +*NB: Some rather rare SPI flash chips (e.g. Atmel AT45DB series) have a completely different layout, please beware.* + ++----------------------+------------+------+---------------------------------+------+------------+-----------------------------+ +| Description | Bus Pirate | Dir. | Flash chip | Dir. | Bus Pirate | Description | ++======================+============+======+===+===========+=============+===+======+============+=============================+ +| (not) Chip Select | CS | → | 1 | /CS | VCC | 8 | ← | +3.3v | Supply | ++----------------------+------------+------+---+-----------+-------------+---+------+------------+-----------------------------+ +| Master In, Slave Out | MISO | ← | 2 | DO (IO1) | /HOLD (IO3) | 7 | ← | +3.3v | (not) hold (see datasheets) | ++----------------------+------------+------+---+-----------+-------------+---+------+------------+-----------------------------+ +| (not) Write Protect | +3.3v | → | 3 | /WP (IO2) | CLK | 6 | ← | CLK | The SPI clock | ++----------------------+------------+------+---+-----------+-------------+---+------+------------+-----------------------------+ +| Ground | GND | → | 4 | GND | DI (IO0) | 5 | ← | MOSI | Master Out, Slave In | ++----------------------+------------+------+---+-----------+-------------+---+------+------------+-----------------------------+ + +Usage +========= + +:: + + $ flashrom -p buspirate_spi:dev=/dev/device,spispeed=frequency + +Example:: + + $ flashrom -p buspirate_spi:dev=/dev/ttyUSB0,spispeed=1M + +Troubleshooting +=============== + +In case of problems probing the chip with flashrom - especially when connecting chips +still soldered in a system - please take a look at the doc :doc:`/user_docs/in_system`. In-system programming is often possible +**only as long as no other devices on the SPI bus are trying to access the device**. + +Speedup +========= + +A beta firmware build exists, to speed up the buspirate. +`See this post on dangerousprototypes.com <http://dangerousprototypes.com/forum/viewtopic.php?f=40&t=3864&start=15#p41…>`_ + +See also: http://dangerousprototypes.com/docs/Bus_Pirate#Firmware_upgrades + +Images +========== + +Bus Pirate v3, front. + +.. image:: Buspirate_v3_front.jpg + +Bus Pirate v3, back. + +.. image:: Buspirate_v3_back.jpg + +Recovering a bricked Lycom PE-115 88SE8123 PCIe to SATA adapter using flashrom and a Bus Pirate - power to the +PE-115 is supplied by a PC. The test probes of the bus pirate are attached directly to the SOIC Atmel AT26F004 SPI flash chip. +The other test clip is connected to GND on another device for convenience (easier than getting yet another clip onto a SOIC device). + +.. image:: Lycom-pe115-flashrom-buspirate-2.jpg diff --git a/doc/supported_hw/supported_prog/index.rst b/doc/supported_hw/supported_prog/index.rst index 130ac20..ec96b9f 100644 --- a/doc/supported_hw/supported_prog/index.rst +++ b/doc/supported_hw/supported_prog/index.rst @@ -15,5 +15,6 @@ .. toctree:: :maxdepth: 1 + buspirate dummyflasher serprog/index -- To view, visit https://review.coreboot.org/c/flashrom/+/83471?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I5a57f08ea3fce0c78d73aa61b85ff7b0cff450b8 Gerrit-Change-Number: 83471 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Reguera Garcia (Dreg) <regueragarciadavid(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in flashrom[main]: doc: Add doc for in-system programming
by Anastasia Klimchuk (Code Review) 03 Aug '24

03 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83451?usp=email ) Change subject: doc: Add doc for in-system programming ...................................................................... doc: Add doc for in-system programming The page on wiki is here: https://wiki.flashrom.org/ISP Change-Id: If4752f0f02ae973b3d832f42166de643d95c9f97 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83451 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Alexander Goncharov <chat(a)joursoir.net> --- A doc/user_docs/1200px-DIP_socket_as_SOIC_clip.jpg A doc/user_docs/Pomona_5250_soic8.jpg A doc/user_docs/in_system.rst M doc/user_docs/index.rst 4 files changed, 46 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Alexander Goncharov: Looks good to me, approved diff --git a/doc/user_docs/1200px-DIP_socket_as_SOIC_clip.jpg b/doc/user_docs/1200px-DIP_socket_as_SOIC_clip.jpg new file mode 100644 index 0000000..c3db692 --- /dev/null +++ b/doc/user_docs/1200px-DIP_socket_as_SOIC_clip.jpg Binary files differ diff --git a/doc/user_docs/Pomona_5250_soic8.jpg b/doc/user_docs/Pomona_5250_soic8.jpg new file mode 100644 index 0000000..83f8c3e --- /dev/null +++ b/doc/user_docs/Pomona_5250_soic8.jpg Binary files differ diff --git a/doc/user_docs/in_system.rst b/doc/user_docs/in_system.rst new file mode 100644 index 0000000..84716d3 --- /dev/null +++ b/doc/user_docs/in_system.rst @@ -0,0 +1,45 @@ +===================== +In-System Programming +===================== + +**In-System Programming** (ISP) sometimes also called **in situ programming** is used to describe +the procedure of writing a flash chip while it is (already/still) attached to the circuit +it is to be used with. Of course any normal "BIOS flash" procedure is a kind of ISP +but when we refer to ISP we usually mean something different: programming a flash chip by external means +while it is mounted on a motherboard. + +This is usually done with SPI chips only. Some mainboards have a special header for this +(often named "ISP", "ISP1", or "SPI") and there should be no problem with accessing the chip +then as long as the wires are not too long. + +If there is no special header then using a special SO(IC) clip is an easy and reliable way +to attach an external programmer. They are produced by different vendors (e.g. Pomona, 3M) +and are available from many distributors (e.g. Distrelec) for 20-50$/€. + +Problems +======== + +* Check the other potential problems (:doc:`misc_notes`) with other types of programming setups first. +* The SPI bus is not isolated enough. Often parts of the chipset are powered on partially + (by the voltage supplied via the Vcc pin of the flash chip). In that case + disconnect Vcc from the programmer and power it with its normal PSU and: + + * Try powering up the board normally and holding it in reset (e.g. use a jumper instead of the reset push button). + * Some chipsets (e.g. Intel ICHs/PCHs) have edge triggered resets. In this case holding them in reset will not work. + This is especially a problem with Intel chipsets because they contain an EC (named ME by Intel, see :doc:`management_engine`), + which uses the flash (r/w!). In this case you can trigger the reset line in short intervals. + For example by connecting it to the chip select (CS) line of the SPI bus or a dedicated clock signal from the programmer. + This should not be too fast though! Reset lines usually require pulses with a minimum duration. + * On some boards, you can try disconnecting the ATX12V header (yellow/black wires only) from the motherboard, + or even remove the CPU or RAM - if the programmer supports SPI sniffing, you may be able to verify that the there is no SPI traffic. + +Images +======== + +Pomona 8-pin SOIC clip with attached jumper wires. + +.. image:: Pomona_5250_soic8.jpg + +A cheap, but very fragile alternative: DIP socket as clip + +.. image:: 1200px-DIP_socket_as_SOIC_clip.jpg diff --git a/doc/user_docs/index.rst b/doc/user_docs/index.rst index 960659e..3ca928a 100644 --- a/doc/user_docs/index.rst +++ b/doc/user_docs/index.rst @@ -9,4 +9,5 @@ chromebooks management_engine misc_intel + in_system misc_notes -- To view, visit https://review.coreboot.org/c/flashrom/+/83451?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: If4752f0f02ae973b3d832f42166de643d95c9f97 Gerrit-Change-Number: 83451 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in flashrom[main]: doc: Add page with misc notes and advice
by Anastasia Klimchuk (Code Review) 03 Aug '24

03 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83450?usp=email ) Change subject: doc: Add page with misc notes and advice ...................................................................... doc: Add page with misc notes and advice This page is a combination of info from the following pages: https://wiki.flashrom.org/Common_problems https://wiki.flashrom.org/Connections https://wiki.flashrom.org/FAQ https://wiki.flashrom.org/Random_notes https://wiki.flashrom.org/Live_CD Change-Id: I538f31765576584760524cd8b06cbf5bce191bde Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83450 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M doc/user_docs/index.rst A doc/user_docs/misc_notes.rst 2 files changed, 150 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/doc/user_docs/index.rst b/doc/user_docs/index.rst index b61567a..960659e 100644 --- a/doc/user_docs/index.rst +++ b/doc/user_docs/index.rst @@ -9,3 +9,4 @@ chromebooks management_engine misc_intel + misc_notes diff --git a/doc/user_docs/misc_notes.rst b/doc/user_docs/misc_notes.rst new file mode 100644 index 0000000..fcb1700 --- /dev/null +++ b/doc/user_docs/misc_notes.rst @@ -0,0 +1,149 @@ +===================== +Misc notes and advice +===================== + +This document contains miscellaneous and unstructured (and mostly, legacy) notes and advice about using flashrom. + +Command set tricks for parallel and LPC chips +============================================= + +This is only mentioned in very few datasheets, but it applies to some parallel (and some LPC) chips. + +Upper address bits of commands are ignored if they are not mentioned explicitly. If a datasheet specifies the following sequence:: + + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0x90, bios + 0x555); + +then it is quite likely the following sequence will work as well:: + + chip_writeb(0xAA, bios + 0x5555); + chip_writeb(0x55, bios + 0x2AAA); + chip_writeb(0x90, bios + 0x5555); + +However, if the chip datasheet specifies addresses like ``0x5555``, you can't shorten them to ``0x555``. + +To summarize, replacing short addresses with long addresses usually works, but the other way round usually fails. + +flashrom doesn't work on my board, what can I do? +================================================= + +* First of all, check if your chipset, ROM chip, and mainboard are supported + (see :doc:`/supported_hw/index`). +* If your board has a jumper for BIOS flash protection (check the manual), disable it. +* Should your BIOS menu have a BIOS flash protection option, disable it. +* If you run flashrom on Linux and see messages about ``/dev/mem``, see next section. +* If you run flashrom on OpenBSD, you might need to obtain raw access permission by setting + ``securelevel = -1`` in ``/etc/rc.securelevel`` and rebooting, or rebooting into single user mode. + +What can I do about /dev/mem errors? +==================================== + +* If flashrom tells you ``/dev/mem mmap failed: Operation not permitted``: + + * Most common at the time of writing is a Linux kernel option, ``CONFIG_IO_STRICT_DEVMEM``, + that prevents even the root user from accessing hardware from user-space if the resource is unknown + to the kernel or a conflicting kernel driver reserved it. On Intel systems, this is most often ``lpc_ich``, + so ``modprobe -r lpc_ich`` can help. A more invasive solution is to try again after rebooting + with ``iomem=relaxed`` in the kernel command line. + + * Some systems with incorrect memory reservations (e.g. E820 map) may have the same problem + even with ``CONFIG_STRICT_DEVMEM``. In that case ``iomem=relaxed`` in the kernel command line may help too. + +* If it tells you ``/dev/mem mmap failed: Resource temporarily unavailable``: + + * This may be an issue with PAT (e.g. if the memory flashrom tries to map is already mapped + in an incompatible mode). Try again after rebooting with nopat in the kernel command line. + +* If you see this message ``Can't mmap memory using /dev/mem: Invalid argument``: + + * Your flashrom is very old, better update it. If the issue persists, try the kernel options mentioned above. + +* Generally, if your version of flashrom is very old, an update might help. + Flashrom has less strict requirements now and works on more systems without having to change the kernel. + +Connections +=========== + +Using In-System programming requires some means to connect the external programmer to the flash chip. + +Note that some external flashers (like the Openmoko debug board) lack a connector, +so they do requires some soldering to be used. Some other don't. For instance the buspirate has a pin connector on it. + +Programmer <-> Removable chip connection +---------------------------------------- + +A breadboard can be used to connect Dual in-line 8 pins chips to the programmer, as they they fit well into it. + +Programmer <-> Clip connection +------------------------------ + +If your programmer has a pin connector, and that you want to avoid soldering, you can use +**Short** `Jump Wires <https://en.wikipedia.org/wiki/Jump_wire>`_ to connect it to a clip. +They usually can be found on some electronic shops. + +Other issues +------------- + +* Wires length and connection quality: Long wires, and bad connection can create some issues, so avoid them. + + * The maximum wires length is very dependent on your setup, so try to have the shortest wires possible. + * If you can't avoid long wires and if you're flash chip is SPI, then lowering the SPI clock could make + it work in some cases. Many programmers do support such option (Called spispeed with most of them, or divisor with ft2232_spi). + +* When soldering wires, the wire tend to break near the soldering point. To avoid such issue, + you have to prevent the wires from bending near the soldering point. + To do that `Heat-shrink_tubing <https://en.wikipedia.org/wiki/Heat-shrink_tubing>`_ or similar methods can be used. + +Common problems +=============== + +The following describes problems commonly found when trying to access flash chips in systems +that are not designed properly for this job, e.g. ad-hoc setups to flash in-system +(TODO add a doc for in-system-specific problems). + +Symptoms indicating you may have at least one of these are for example inconsistent reads or probing results. +This happens basically because the analog electrical waveforms representing the digital information +get too distorted to by interpreted correctly all the time. Depending on the cause different steps can be tried. + +* Not all input pins are connected to the correct voltage level/output pin of the programmer. + Always connect all input pins of ICs! + +* The easiest thing to try is lowering the (SPI) clock frequency if your programmer supports it. + That way the waveforms have more time to settle before being sampled by the receiver which might be enough. + Depending on the design of the driver and receiver as well as the actual communication path + this might not change anything as well. + +* Wires are too long. Shortening them to a few cm (i.e. < 20, the lesser the better) might help. + +* The impedances of the wires/traces do not match the impedances of the input pins + (of either the circuit/chip on the mainboard or the external programmer). + Try using shorter wires, adding small (<100 Ohm) series resistors or parallel capacitors (<20pF) + as near as possible to the input pins (this includes also the MISO line which ends near the programmer)\ + and/or ask someone who has experience with high frequency electronics. + +* The supply voltage of the flash chip is not stable enough. Try adding a 0.1 µF - 1 µF (ceramic) capacitor + between the flash chip's VCC and GND pins as near as possible to the chip. + +Live CD +========= + +A Live CD containing flashrom provides a user with a stable work environment to read, write and verify a flash device on any supported hardware. + +It can help avoid Linux installation issues, which can be a hassle for some users. + +flashrom is already shipped in some of the Live CDs, see below. *Please note, some of these ship very old versions of flashrom*. + +* `SystemRescueCd <http://www.sysresccd.org/>`_ has been including flashrom since about version 2.5.1. + +* `grml <http://grml.org/>`_ + + * Note: You need the full grml ISO, "small" (and "medium") ISOs do not contain flashrom. + * Note: Some releases (e.g. 2011.12) did not contain flashrom. + +* `Parted Magic <http://partedmagic.com/>`_ + +* `Hiren's BootCD <http://www.hirensbootcd.org/>`_ + + * When you select "Linux based rescue environment (Parted Magic 6.7)" and then "Live with default settings", + you have access to a system which has flashrom. -- To view, visit https://review.coreboot.org/c/flashrom/+/83450?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I538f31765576584760524cd8b06cbf5bce191bde Gerrit-Change-Number: 83450 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in flashrom[main]: doc: Add manpage item for nicintel_spi
by Anastasia Klimchuk (Code Review) 03 Aug '24

03 Aug '24

Attention is currently required from: Idwer Vollering. Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83751?usp=email ) Change subject: doc: Add manpage item for nicintel_spi ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hello Idwer! You are the author of nicintel page on wiki (and the programmer nicintel_spi), maybe you can review this patch? That page is really small and it wasn't referenced from any other page (probably by accident, but still). So I thought it can be just a little section on nicintel_spi to the manpage. If you agree, you can vote +1. If at some point you want to expand the documentation about nicintel_spi, or create a separate longer page, it's not a problem, doc can be added any time. Thank you! -- To view, visit https://review.coreboot.org/c/flashrom/+/83751?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I139065611c68c0fa0a675fe49a6f8bc20e9057f7 Gerrit-Change-Number: 83751 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Comment-Date: Sat, 03 Aug 2024 07:40:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in flashrom[main]: flashchips: add GD25LF256F
by Anastasia Klimchuk (Code Review) 02 Aug '24

02 Aug '24

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/83717?usp=email ) Change subject: flashchips: add GD25LF256F ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/83717/comment/3cd44264_7a6a059b?us… : PS1, Line 13: I will have to email you the datasheet. Yes, that would be great! I will wait for you to send me a datasheet. -- To view, visit https://review.coreboot.org/c/flashrom/+/83717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I21a71606476e823faa38a7920aa2b10e25d68d26 Gerrit-Change-Number: 83717 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 02 Aug 2024 12:33:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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