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[S] Change in flashrom[main]: ichspi: Add RaptorPoint PCH support
by Maciej Pijanowski (Code Review) 09 Aug '24

09 Aug '24

Attention is currently required from: Maciej Pijanowski. Hello Michał Żygowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/83854?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: ichspi: Add RaptorPoint PCH support ...................................................................... ichspi: Add RaptorPoint PCH support Change-Id: I13ac52d5400c0e2260e12d605077fc2182c379ef Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M chipset_enable.c M ich_descriptors.c M ichspi.c M include/programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 5 files changed, 37 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/83854/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83854?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I13ac52d5400c0e2260e12d605077fc2182c379ef Gerrit-Change-Number: 83854 Gerrit-PatchSet: 2 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com>

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[S] Change in flashrom[main]: ichspi: Add RaptorPoint PCH support
by Maciej Pijanowski (Code Review) 09 Aug '24

09 Aug '24

Attention is currently required from: Michał Żygowski. Hello Michał Żygowski, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/83854?usp=email to review the following change. Change subject: ichspi: Add RaptorPoint PCH support ...................................................................... ichspi: Add RaptorPoint PCH support Change-Id: I13ac52d5400c0e2260e12d605077fc2182c379ef Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M chipset_enable.c M ich_descriptors.c M ichspi.c M include/programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 5 files changed, 38 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/83854/1 diff --git a/chipset_enable.c b/chipset_enable.c index facf29e..6b1c1b5 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -606,6 +606,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_700_SERIES_RAPTOR_POINT: case CHIPSET_METEOR_LAKE: case CHIPSET_PANTHER_LAKE: case CHIPSET_ELKHART_LAKE: @@ -714,6 +715,7 @@ break; case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_700_SERIES_RAPTOR_POINT: case CHIPSET_C740_SERIES_EMMITSBURG: case CHIPSET_METEOR_LAKE: case CHIPSET_PANTHER_LAKE: @@ -751,6 +753,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_700_SERIES_RAPTOR_POINT: case CHIPSET_METEOR_LAKE: case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: @@ -1017,6 +1020,11 @@ return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_600_SERIES_ALDER_POINT); } +static int enable_flash_pch700(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_700_SERIES_RAPTOR_POINT); +} + static int enable_flash_mtl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) { return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_METEOR_LAKE); @@ -2190,9 +2198,19 @@ {0x8086, 0x7a83, B_S, NT, "Intel", "Q670", enable_flash_pch600}, {0x8086, 0x7a84, B_S, DEP, "Intel", "Z690", enable_flash_pch600}, {0x8086, 0x7a88, B_S, NT, "Intel", "W680", enable_flash_pch600}, - {0x8086, 0x7a8a, B_S, NT, "Intel", "W685", enable_flash_pch600}, {0x8086, 0x7a8d, B_S, NT, "Intel", "WM690", enable_flash_pch600}, {0x8086, 0x7a8c, B_S, NT, "Intel", "HM670", enable_flash_pch600}, + {0x8086, 0x7a90, B_S, NT, "Intel", "R680E", enable_flash_pch600}, + {0x8086, 0x7a91, B_S, NT, "Intel", "Q670E", enable_flash_pch600}, + {0x8086, 0x7a92, B_S, NT, "Intel", "H610E", enable_flash_pch600}, + {0x8086, 0x7a8a, B_S, NT, "Intel", "W790", enable_flash_pch700}, + {0x8086, 0x7a04, B_S, DEP, "Intel", "Z790", enable_flash_pch700}, + {0x8086, 0x7a05, B_S, NT, "Intel", "H770", enable_flash_pch700}, + {0x8086, 0x7a06, B_S, NT, "Intel", "B760", enable_flash_pch700}, + {0x8086, 0x7a0c, B_S, NT, "Intel", "HM770", enable_flash_pch700}, + {0x8086, 0x7a0d, B_S, NT, "Intel", "WM790", enable_flash_pch700}, + {0x8086, 0x7a14, B_S, NT, "Intel", "C262", enable_flash_pch700}, + {0x8086, 0x7a13, B_S, NT, "Intel", "C266", enable_flash_pch700}, {0x8086, 0x7e23, B_S, DEP, "Intel", "Meteor Lake-P/M", enable_flash_mtl}, {0x8086, 0xe323, B_S, DEP, "Intel", "Panther Lake-U/H 12Xe", enable_flash_ptl}, {0x8086, 0xe423, B_S, DEP, "Intel", "Panther Lake-H 4Xe", enable_flash_ptl}, diff --git a/ich_descriptors.c b/ich_descriptors.c index eaf44b0..c436fab 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -49,6 +49,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_700_SERIES_RAPTOR_POINT: case CHIPSET_METEOR_LAKE: case CHIPSET_PANTHER_LAKE: case CHIPSET_ELKHART_LAKE: @@ -80,6 +81,7 @@ case CHIPSET_C740_SERIES_EMMITSBURG: case CHIPSET_APOLLO_LAKE: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_700_SERIES_RAPTOR_POINT: case CHIPSET_METEOR_LAKE: case CHIPSET_PANTHER_LAKE: case CHIPSET_GEMINI_LAKE: @@ -221,6 +223,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_700_SERIES_RAPTOR_POINT: case CHIPSET_METEOR_LAKE: case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: @@ -320,6 +323,7 @@ return freq_str[2][value]; case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_700_SERIES_RAPTOR_POINT: case CHIPSET_C740_SERIES_EMMITSBURG: case CHIPSET_METEOR_LAKE: case CHIPSET_PANTHER_LAKE: @@ -371,6 +375,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_700_SERIES_RAPTOR_POINT: case CHIPSET_METEOR_LAKE: case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: @@ -512,6 +517,7 @@ cs == CHIPSET_400_SERIES_COMET_POINT || cs == CHIPSET_500_SERIES_TIGER_POINT || cs == CHIPSET_600_SERIES_ALDER_POINT || + cs == CHIPSET_700_SERIES_RAPTOR_POINT || cs == CHIPSET_C740_SERIES_EMMITSBURG || cs == CHIPSET_JASPER_LAKE || cs == CHIPSET_METEOR_LAKE || @@ -1115,6 +1121,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_700_SERIES_RAPTOR_POINT: case CHIPSET_METEOR_LAKE: case CHIPSET_PANTHER_LAKE: case CHIPSET_GEMINI_LAKE: @@ -1277,6 +1284,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_700_SERIES_RAPTOR_POINT: case CHIPSET_METEOR_LAKE: case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: @@ -1324,6 +1332,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_700_SERIES_RAPTOR_POINT: case CHIPSET_METEOR_LAKE: case CHIPSET_PANTHER_LAKE: case CHIPSET_APOLLO_LAKE: diff --git a/ichspi.c b/ichspi.c index f74fb05..9718600 100644 --- a/ichspi.c +++ b/ichspi.c @@ -2106,6 +2106,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_700_SERIES_RAPTOR_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -2147,6 +2148,8 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_700_SERIES_RAPTOR_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -2210,6 +2213,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_700_SERIES_RAPTOR_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -2291,6 +2295,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_700_SERIES_RAPTOR_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -2332,6 +2337,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_700_SERIES_RAPTOR_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_JASPER_LAKE: @@ -2371,6 +2377,7 @@ ich_gen == CHIPSET_400_SERIES_COMET_POINT || ich_gen == CHIPSET_500_SERIES_TIGER_POINT || ich_gen == CHIPSET_600_SERIES_ALDER_POINT || + ich_gen == CHIPSET_700_SERIES_RAPTOR_POINT)) { ich_gen == CHIPSET_C740_SERIES_EMMITSBURG)) { msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n"); ich_spi_mode = ich_hwseq; diff --git a/include/programmer.h b/include/programmer.h index a90624b..0210038 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -357,6 +357,7 @@ CHIPSET_400_SERIES_COMET_POINT, CHIPSET_500_SERIES_TIGER_POINT, CHIPSET_600_SERIES_ALDER_POINT, + CHIPSET_700_SERIES_RAPTOR_POINT, CHIPSET_APOLLO_LAKE, CHIPSET_GEMINI_LAKE, CHIPSET_JASPER_LAKE, diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 09587f7..d5289b9 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -239,6 +239,8 @@ cs = CHIPSET_500_SERIES_TIGER_POINT; else if (strcmp(csn, "600") == 0) cs = CHIPSET_600_SERIES_ALDER_POINT; + else if (strcmp(csn, "700") == 0) + cs = CHIPSET_700_SERIES_RAPTOR_POINT; else if (strcmp(csn, "apollo") == 0) cs = CHIPSET_APOLLO_LAKE; else if (strcmp(csn, "gemini") == 0) -- To view, visit https://review.coreboot.org/c/flashrom/+/83854?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I13ac52d5400c0e2260e12d605077fc2182c379ef Gerrit-Change-Number: 83854 Gerrit-PatchSet: 1 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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[S] Change in flashrom[main]: flashrom.c: Rename {erase|write}_by_layout_new as the only one
by Aarya (Code Review) 09 Aug '24

09 Aug '24

Attention is currently required from: Anastasia Klimchuk, Peter Marheine. Aarya has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83852?usp=email ) Change subject: flashrom.c: Rename {erase|write}_by_layout_new as the only one ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83852?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ib21bf29e1993c4fc0516e76fde2ad283eedb50d2 Gerrit-Change-Number: 83852 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Fri, 09 Aug 2024 13:30:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in flashrom[main]: flashrom.c: Delete legacy erase and write logic
by Aarya (Code Review) 09 Aug '24

09 Aug '24

Attention is currently required from: Anastasia Klimchuk, Peter Marheine. Aarya has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83846?usp=email ) Change subject: flashrom.c: Delete legacy erase and write logic ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > I was for some reasons under impression this change will need to wait until removing makefile... […] LGTM -- To view, visit https://review.coreboot.org/c/flashrom/+/83846?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I08fd686fecf6a5313eea2d66b368661c664f4800 Gerrit-Change-Number: 83846 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Fri, 09 Aug 2024 13:28:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[L] Change in flashrom[main]: flashrom.c: Delete legacy erase and write logic
by Aarya (Code Review) 09 Aug '24

09 Aug '24

Attention is currently required from: Anastasia Klimchuk, Peter Marheine. Aarya has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83846?usp=email ) Change subject: flashrom.c: Delete legacy erase and write logic ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83846?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I08fd686fecf6a5313eea2d66b368661c664f4800 Gerrit-Change-Number: 83846 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Fri, 09 Aug 2024 13:27:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in flashrom[main]: flashchips: add GD25LF256F
by Anastasia Klimchuk (Code Review) 09 Aug '24

09 Aug '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83717?usp=email ) Change subject: flashchips: add GD25LF256F ...................................................................... flashchips: add GD25LF256F added GD25LF256F on flashchips.c added GIGADEVICE_GD25LF256F=0x6319 on flashchip.h GD25LF256F is a higher performance 1.8V 256Mbit SPI flash I have tested on CH347 with erase, program, read, protection. Change-Id: I21a71606476e823faa38a7920aa2b10e25d68d26 Signed-off-by: Victor <vlim(a)gigadevice.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83717 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c M include/flashchips.h 2 files changed, 59 insertions(+), 1 deletion(-) Approvals: Anastasia Klimchuk: Looks good to me, approved build bot (Jenkins): Verified diff --git a/flashchips.c b/flashchips.c index 01cf641..60fbb1b 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6585,7 +6585,64 @@ .decode_range = DECODE_RANGE_SPI25, }, - { + { + .vendor = "GigaDevice", + .name = "GD25LF256F", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25LF256F, + .total_size = 32768, + .page_size = 256, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2 | FEATURE_4BA, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = SPI_BLOCK_ERASE_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_5C, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_DC, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, + .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */ + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1650, 2000}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */ + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { .vendor = "GigaDevice", .name = "GD25LQ128E/GD25LB128E/GD25LR128E/GD25LQ128D/GD25LQ128C", .bustype = BUS_SPI, diff --git a/include/flashchips.h b/include/flashchips.h index c4b13d9..d8146ec 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -405,6 +405,7 @@ #define GIGADEVICE_GD25LQ128CD 0x6018 #define GIGADEVICE_GD25LQ255E 0x6019 #define GIGADEVICE_GD25LF128E 0x6318 +#define GIGADEVICE_GD25LF256F 0x6319 #define GIGADEVICE_GD25LR256E 0x6719 #define GIGADEVICE_GD25LR512ME 0x671A #define GIGADEVICE_GD25WQ80E 0x6514 -- To view, visit https://review.coreboot.org/c/flashrom/+/83717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I21a71606476e823faa38a7920aa2b10e25d68d26 Gerrit-Change-Number: 83717 Gerrit-PatchSet: 5 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in flashrom[main]: flashrom.c: Rename {erase|write}_by_layout_new as the only one
by Anastasia Klimchuk (Code Review) 09 Aug '24

09 Aug '24

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83852?usp=email ) Change subject: flashrom.c: Rename {erase|write}_by_layout_new as the only one ...................................................................... flashrom.c: Rename {erase|write}_by_layout_new as the only one We used to have two code paths for erase and write, so we had {erase|write}_by_layout in two variants: *_new and *_legacy. Now that legacy is removed, *_new can be renamed without *_new suffix. Change-Id: Ib21bf29e1993c4fc0516e76fde2ad283eedb50d2 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M flashrom.c 1 file changed, 2 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/52/83852/1 diff --git a/flashrom.c b/flashrom.c index 453a2bf..01a41c4 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1327,7 +1327,7 @@ return ret; } -static int erase_by_layout_new(struct flashctx *const flashctx) +static int erase_by_layout(struct flashctx *const flashctx) { bool all_skipped = true; const uint32_t flash_size = flashctx->chip->total_size * 1024; @@ -1370,12 +1370,7 @@ return ret; } -static int erase_by_layout(struct flashctx *const flashctx) -{ - return erase_by_layout_new(flashctx); -} - -static int write_by_layout_new(struct flashctx *const flashctx, +static int write_by_layout(struct flashctx *const flashctx, void *const curcontents, const void *const newcontents, bool *all_skipped) { @@ -1410,13 +1405,6 @@ return ret; } -static int write_by_layout(struct flashctx *const flashctx, - uint8_t *const curcontents, const uint8_t *const newcontents, - bool *all_skipped) -{ - return write_by_layout_new(flashctx, curcontents, newcontents, all_skipped); -} - /** * @brief Compares the included layout regions with content from a buffer. * -- To view, visit https://review.coreboot.org/c/flashrom/+/83852?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ib21bf29e1993c4fc0516e76fde2ad283eedb50d2 Gerrit-Change-Number: 83852 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>

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[L] Change in flashrom[main]: flashrom.c: Delete legacy erase and write logic
by Anastasia Klimchuk (Code Review) 09 Aug '24

09 Aug '24

Attention is currently required from: Aarya, Peter Marheine. Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83846?usp=email ) Change subject: flashrom.c: Delete legacy erase and write logic ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: I was for some reasons under impression this change will need to wait until removing makefile... but actually there is no merge conflict! So this is ready for review. Also, I think unit tests are adequate testing for this type of change. Please tell me if you disagree. -- To view, visit https://review.coreboot.org/c/flashrom/+/83846?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I08fd686fecf6a5313eea2d66b368661c664f4800 Gerrit-Change-Number: 83846 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Fri, 09 Aug 2024 10:10:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in flashrom[main]: flashrom.c: Delete legacy erase and write logic
by Anastasia Klimchuk (Code Review) 09 Aug '24

09 Aug '24

Anastasia Klimchuk has uploaded a new patch set (#3). ( https://review.coreboot.org/c/flashrom/+/83846?usp=email ) Change subject: flashrom.c: Delete legacy erase and write logic ...................................................................... flashrom.c: Delete legacy erase and write logic Current code path for erase and write has been enabled in the tree since May 2023, which is more than 1 year ago (15 months ago), and legacy path has been disabled since the same time. Current logic has been officially released in v1.4.0 in July 2024. Change-Id: I08fd686fecf6a5313eea2d66b368661c664f4800 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M erasure_layout.c M flashrom.c 2 files changed, 1 insertion(+), 369 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/46/83846/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/83846?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I08fd686fecf6a5313eea2d66b368661c664f4800 Gerrit-Change-Number: 83846 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>

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[L] Change in flashrom[main]: flashrom.c: Delete legacy erase and write logic
by Anastasia Klimchuk (Code Review) 09 Aug '24

09 Aug '24

Anastasia Klimchuk has uploaded a new patch set (#2). ( https://review.coreboot.org/c/flashrom/+/83846?usp=email ) Change subject: flashrom.c: Delete legacy erase and write logic ...................................................................... flashrom.c: Delete legacy erase and write logic Current code path for erase and write has been enabled in the tree since May 2023, which is more than 1 year ago (15 months ago), and legacy path has been disabled since the same time. Current logic has been officially released in v1.4.0 in July 2024. Change-Id: I08fd686fecf6a5313eea2d66b368661c664f4800 Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M flashrom.c 1 file changed, 0 insertions(+), 368 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/46/83846/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83846?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I08fd686fecf6a5313eea2d66b368661c664f4800 Gerrit-Change-Number: 83846 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>

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