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Change subject: flashrom.c:Add function to get a flattened view of the chip erase blocks
......................................................................
Patch Set 36: Code-Review+2
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Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/66717 )
Change subject: flashrom.c: Update check_block_eraser function to use probe opcode
......................................................................
Patch Set 17: Code-Review+2
(6 comments)
Patchset:
PS3:
> Maybe add the `const` in a separate commit ahead.
.
File dummyflasher.c:
https://review.coreboot.org/c/flashrom/+/66717/comment/204c542e_6cec248a
PS17, Line 125: const
This should not be done in this patch
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/66717/comment/0e01d523_e52ef6ab
PS17, Line 1652: const
this
File include/programmer.h:
https://review.coreboot.org/c/flashrom/+/66717/comment/9152b137_c66bbcc0
PS17, Line 316: const
this
https://review.coreboot.org/c/flashrom/+/66717/comment/b7fc4709_e80fc20c
PS17, Line 326: const
this
File spi.c:
https://review.coreboot.org/c/flashrom/+/66717/comment/d26a9121_81fbd715
PS17, Line 137: const
this
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Change subject: spi25.c: Rename spi_get_erasefn_from_opcode to spi25_get_erasefn_from_opcode
......................................................................
Patch Set 4: Code-Review+2
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Change subject: spi25.c: Move spi_get_opcode_from_erasefn() to spi.c
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
File spi.c:
https://review.coreboot.org/c/flashrom/+/67715/comment/ea24f1ec_148cdc56
PS4, Line 202: }
Need newline at the end
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Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68247 )
Change subject: util: add bash completion script
......................................................................
Patch Set 9: Code-Review+1
(3 comments)
File Makefile:
https://review.coreboot.org/c/flashrom/+/68247/comment/e0dc52d7_29d87f82
PS9, Line 1041: .bash
IIRC there should be no `.bash` suffix
File meson.build:
https://review.coreboot.org/c/flashrom/+/68247/comment/03a7a3c0_be91b777
PS9, Line 624: if get_option('classic_cli').disabled()
When `get_option('bash_completion').auto()` and `get_option('classic_cli').disabled()` are true, there should be no action.
`get_option('bash_completion').auto()` equals `get_option('classic_cli').auto()` in the behavior. So if I disable the cli, the bash_completion is also disabled.
https://review.coreboot.org/c/flashrom/+/68247/comment/5bd340f3_7da26838
PS9, Line 646: .bash
same here
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Alexander Goncharov has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70027 )
Change subject: libflashrom: Define macro to detect v1.3 header
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Heres what SDL does, […]
The current macro looks like a stub. As far as I know, nothing prevents us from adding a normal version system, so +1 for Evan's ideas.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69195 )
Change subject: ichspi.c: Read chip ID and use it to populate `flash->chip`
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/69195/comment/c586b5b9_0e0ca9a4
PS2, Line 7: ichspi.c: Read chip ID and use it to identify chip
> > Maybe we should just print a warning if >1 chip is detected?
> >
> > Subrata, do you have any thoughts on this?
>
> Ideally as per descriptor, there can be 2 SPI flash and we need to drive CS PIN low to initiate the READ JEDEC ID (0x9F) HW seq command for each SPI flash chip to capture the response.
looking at the all latest platform, I don't see the usage of dual chips and mostly I could see the descriptor is set to 0 aka 1 chip.
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Change subject: ichspi.c: Read chip ID and use it to populate `flash->chip`
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/69195/comment/11eb0f42_f6d40c02
PS2, Line 7: ichspi.c: Read chip ID and use it to identify chip
> Maybe we should just print a warning if >1 chip is detected?
>
> Subrata, do you have any thoughts on this?
Ideally as per descriptor, there can be 2 SPI flash and we need to drive CS PIN low to initiate the READ JEDEC ID (0x9F) HW seq command for each SPI flash chip to capture the response.
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Hello build bot (Jenkins), Edward O'Callaghan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/70126
to look at the new patch set (#2).
Change subject: programmer: Add get_region to spi/opaque masters
......................................................................
programmer: Add get_region to spi/opaque masters
Add a get_region function to spi and opaque masters so that they can
expose access permissions for multiple regions within the flash.
A get_region() implementation is added for the ichspi driver in a
following patch.
Finally, another patch uses get_region() to make read_flash() and
write_flash() skip inaccessable regions, making read, write, and erase
operations work on Intel platforms with active an CSME coprocessor.
This logic will be integrated with layout in the future, but for now
this moves ichspi support forward without making refactoring too hard
later on.
BUG=b:260440773
BRANCH=none
TEST=ninja test
Change-Id: I8c43f6b705f36ef18842a04ba6241d3a0b36b232
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M include/programmer.h
1 file changed, 39 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/26/70126/2
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