Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69992 )
Change subject: ichspi: Clear Fast SPI HSFC register before HW seq operation
......................................................................
ichspi: Clear Fast SPI HSFC register before HW seq operation
This patch fixes a regression introduced with
commit 7ed1337309d3fe74f5af09520970f0f1d417399a (ichspi: Factor out
common hwseq_xfer logic into helpers).
The reason for the regression is ignoring the fact that the Fast SPI
controller MMIO register HSFC (0x06) might not hold the default zero
value before initiating the HW sequencing operation.
Having a `1b` value in the HSFC.FDBC (bits 24-29) field would represent
a byte that needs to be transfered.
While debugging the regression, we have observed that the default value
in the FDBC (prior to initiate any operation) is 0x3f (instead of
zero) which represents 64-byte transfer.
localhost ~ # iotools mmio_read32 0x92d16006
0x3f00
<Fast SPI MMIO BAR: 0x92d16000 and HSFC offset: 0x06>
FDBC offset during `--wp-disable` operation represents higher numbers of
bytes than the actual and eventually results in the error.
Additionally, dropped unused variable (struct hwseq_data *hwseq_data).
BUG=b:258280679
TEST=Able to build flashrom and perform below operations on Google, Rex
and Google, Kano/Taeko.
Without this patch:
HSFC register value inside ich_start_hwseq_xfer() before initiating
the HW seq operations: 0x3f00
HSFC register value inside ich_start_hwseq_xfer() during the HW seq
operations (Read Status): 0x3f11
With this patch:
HSFC register value inside ich_start_hwseq_xfer() before initiating
the HW seq operations: 0x0
HSFC register value inside ich_start_hwseq_xfer() during the HW seq
operations (Read Status): 0x11
Additionally, verified other HW sequencing operations (like read, write,
erase, read status, write status, read ID) working fine without any
error.
Change-Id: I4cc3f24f880d1d621f1f48a6e6b276449fa46f98
Original-Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69788
Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com>
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Change-Id: I086750f8bbdc0c95c4c067412b9b3d23fecdbe9d
---
M ichspi.c
1 file changed, 66 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/92/69992/1
diff --git a/ichspi.c b/ichspi.c
index cd6e802..29dcd25 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1349,8 +1349,8 @@
uint32_t hsfc_cycle, uint32_t flash_addr, size_t len,
uint32_t addr_mask)
{
- uint16_t hsfc;
- struct hwseq_data *hwseq_data = get_hwseq_data_from_context(flash);
+ /* make sure HSFC register is cleared before initiate any operation */
+ uint16_t hsfc = 0;
/* Sets flash_addr in FADDR */
ich_hwseq_set_addr(flash_addr, addr_mask);
@@ -1359,8 +1359,6 @@
REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
/* Set up transaction parameters. */
- hsfc = REGREAD16(ICH9_REG_HSFC);
- hsfc &= ~hwseq_data->hsfc_fcycle; /* clear operation */
hsfc |= hsfc_cycle;
hsfc |= HSFC_FDBC_VAL(len - 1);
hsfc |= HSFC_FGO; /* start */
--
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Gerrit-Change-Id: I086750f8bbdc0c95c4c067412b9b3d23fecdbe9d
Gerrit-Change-Number: 69992
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Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69990 )
Change subject: linux_mtd: Mark Opaque chip as tested for WP
......................................................................
linux_mtd: Mark Opaque chip as tested for WP
Since linux_mtd supports write-protect, its probe function needs
to mark Opaque chip as tested for WP. Programmers which are
opaque masters are responsible for populating flashchip#tested
struct in probe function.
Without the patch, any operation running via linux_mtd displays
a message "This flash part has status UNTESTED for operations: WP".
With the patch, the message is not displayed anymore.
BUG=b:258755442
BRANCH=none
TEST=flashrom -p host on ARM dut
Found Programmer flash chip "Opaque flash chip"
(8192 kB, Programmer-specific) on host.
No operations were specified.
Change-Id: Icc0521c28555a93f26ce66bdbeaa68590f10c358
Original-Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69518
Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Original-Reviewed-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Change-Id: Ic4017511dd953204f9de86beaecf2ab80c50b754
---
M linux_mtd.c
1 file changed, 34 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/90/69990/1
diff --git a/linux_mtd.c b/linux_mtd.c
index 5a1360e..c49b14a 100644
--- a/linux_mtd.c
+++ b/linux_mtd.c
@@ -179,7 +179,7 @@
if (data->no_erase)
flash->chip->feature_bits |= FEATURE_NO_ERASE;
- flash->chip->tested = TEST_OK_PREW;
+ flash->chip->tested = TEST_OK_PREWB;
flash->chip->total_size = data->total_size / 1024; /* bytes -> kB */
flash->chip->block_erasers[0].eraseblocks[0].size = data->erasesize;
flash->chip->block_erasers[0].eraseblocks[0].count =
--
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Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69989 )
Change subject: cli_classic.c: Be consistent with pointer types
......................................................................
cli_classic.c: Be consistent with pointer types
With `i586-pc-msdosdjgpp-gcc (GCC) 12.2.0`, `uint32_t` is defined as
`long unsigned int`, which is not the same as `unsigned int`. As the
`flashrom_layout_get_region_range()` function is part of libflashrom
API, adjust `cli_classic.c` instead to avoid type mismatches.
Change-Id: Ie8f5bc0d9296f7c6b8f8a351b53052f5fe86b09d
Original-Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69451
Original-Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Original-Reviewed-by: Evan Benn <evanbenn(a)google.com>
Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com>
Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Change-Id: I51c1a84885d3e5c375be5365e0e2f1d5b98156f2
---
M cli_classic.c
1 file changed, 25 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/89/69989/1
diff --git a/cli_classic.c b/cli_classic.c
index a77422e..4649c73 100644
--- a/cli_classic.c
+++ b/cli_classic.c
@@ -126,7 +126,7 @@
return true;
}
-static int parse_wp_range(uint32_t *start, uint32_t *len)
+static int parse_wp_range(unsigned int *start, unsigned int *len)
{
char *endptr = NULL, *token = NULL;
@@ -568,7 +568,7 @@
int namelen, opt, i, j;
int startchip = -1, chipcount = 0, option_index = 0;
int operation_specified = 0;
- uint32_t wp_start = 0, wp_len = 0;
+ unsigned int wp_start = 0, wp_len = 0;
bool force = false, ifd = false, fmap = false;
#if CONFIG_PRINT_WIKI == 1
bool list_supported_wiki = false;
--
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Change subject: cli, manpage: Clean up occurrences of old image argument
......................................................................
Patch Set 2: Code-Review+1
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69988 )
Change subject: libpayload: Fix compiling bugs
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/69988/comment/819b8a59_15619cc4
PS1, Line 9: ((
Should we fix the double parentheses?
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Change subject: libflashrom.c: Invert if conditions to improve the readability
......................................................................
Patch Set 3: Code-Review+2
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69984 )
Change subject: linux_mtd: Mark Opaque chip as tested for WP
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/69984/comment/d0201746_50bb6711
PS2, Line 9: Since linux_mtd supports write-protect, its probe function needs
(Reposted from CB:69518) What happens if the chip doesn't support write-protect?
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