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Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by build bot (Jenkins) (Code Review) 23 Mar '17

23 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18937 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/44/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/60/ : SUCCESS -- To view, visit https://review.coreboot.org/18937 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I79d0c6284397ca382ce8e531c6f9490c74d31cc1 Gerrit-PatchSet: 2 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by build bot (Jenkins) (Code Review) 23 Mar '17

23 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18938 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/45/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/61/ : SUCCESS -- To view, visit https://review.coreboot.org/18938 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0ad46f7944d92d3381975c5e10af0918ec163782 Gerrit-PatchSet: 2 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by build bot (Jenkins) (Code Review) 23 Mar '17

23 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18935 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/42/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/58/ : SUCCESS -- To view, visit https://review.coreboot.org/18935 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iab0a8b71a7680b8dee4f7c6c5dabc05c8436d97e Gerrit-PatchSet: 2 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by build bot (Jenkins) (Code Review) 23 Mar '17

23 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18936 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/43/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/59/ : SUCCESS -- To view, visit https://review.coreboot.org/18936 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If122368e852d83f0b04d58840ee3bbeccec1e36b Gerrit-PatchSet: 2 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by build bot (Jenkins) (Code Review) 23 Mar '17

23 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18934 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/41/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/57/ : SUCCESS -- To view, visit https://review.coreboot.org/18934 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I1b43c189cd19c573935fa553ae3ff23f2aa7e251 Gerrit-PatchSet: 2 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by build bot (Jenkins) (Code Review) 23 Mar '17

23 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18933 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/40/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/55/ : SUCCESS -- To view, visit https://review.coreboot.org/18933 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ibeddffc2de6ee8384d7bf493cfb5f7d6174b31bc Gerrit-PatchSet: 2 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in flashrom[staging]: flashrom: Add Skylake platform support
by build bot (Jenkins) (Code Review) 23 Mar '17

23 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18932 ) Change subject: flashrom: Add Skylake platform support ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/flashrom_gerrit/56/ : FAILURE https://qa.coreboot.org/job/flashrom-customrules/39/ : SUCCESS -- To view, visit https://review.coreboot.org/18932 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0e8ad2d3281c148414fd357427fcd445afc7d045 Gerrit-PatchSet: 2 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by Nico Huber (Code Review) 23 Mar '17

23 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18958 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... fixup! flashrom: Add Skylake platform support Correctly abstract over PR0 register location Change-Id: I91ef5ad2c055593bd40ecfc17dcd71b8ef27aeee Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ichspi.c 1 file changed, 17 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/58/18958/1 diff --git a/ichspi.c b/ichspi.c index e8fb74d..ed14338 100644 --- a/ichspi.c +++ b/ichspi.c @@ -70,7 +70,8 @@ #define DLOCK_SSEQ_LOCKDN_OFF 16 #define DLOCK_SSEQ_LOCKDN (0x1 << DLOCK_SSEQ_LOCKDN_OFF) -#define PCH100_REG_FPR0 0x84 /* 32 Bytes Protected Range 0 */ +#define PCH100_REG_FPR0 0x84 /* 32 Bits Protected Range 0 */ +#define PCH100_REG_GPR0 0x98 /* 32 Bits Global Protected Range 0 */ #define PCH100_REG_SSFSC 0xA0 /* 32 Bits Status (8) + Control (24) */ #define PCH100_REG_PREOP 0xA4 /* 16 Bits */ @@ -1563,20 +1564,12 @@ ((~((pr) >> PR_WP_OFF) & 1) << 1)) /* returns 0 if range is unused (i.e. r/w) */ -static int ich9_handle_pr(int i, int chipset) +static int ich9_handle_pr(const size_t reg_pr0, int i) { static const char *const access_names[3] = { "locked", "read-only", "write-only" }; - uint8_t off; - switch (chipset) { - case CHIPSET_100_SERIES_SUNRISE_POINT: - off = PCH100_REG_FPR0 + (i * 4); - break; - default: - off = ICH9_REG_PR0 + (i * 4); - break; - } + uint8_t off = reg_pr0 + (i * 4); uint32_t pr = mmio_readl(ich_spibar + off); unsigned int rwperms = ICH_PR_PERMS(pr); @@ -1593,17 +1586,9 @@ /* Set/Clear the read and write protection enable bits of PR register @i * according to @read_prot and @write_prot. */ -static void ich9_set_pr(int i, int read_prot, int write_prot, int chipset) +static void ich9_set_pr(const size_t reg_pr0, int i, int read_prot, int write_prot) { - void *addr; - switch (chipset) { - case CHIPSET_100_SERIES_SUNRISE_POINT: - addr = ich_spibar + PCH100_REG_FPR0 + (i * 4); - break; - default: - addr = ich_spibar + ICH9_REG_PR0 + (i * 4); - break; - } + void *addr = ich_spibar + reg_pr0 + (i * 4); uint32_t old = mmio_readl(addr); uint32_t new; @@ -1668,12 +1653,16 @@ ich_hwseq, ich_swseq } ich_spi_mode = ich_auto; + size_t num_freg, num_pr, reg_pr0; ich_generation = ich_gen; ich_spibar = spibar; /* Moving registers / bits */ if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) { + num_freg = 6; + num_pr = 6; /* PR5 is actually GPR0 */ + reg_pr0 = PCH100_REG_FPR0; swseq_data.reg_ssfsc = PCH100_REG_SSFSC; swseq_data.reg_preop = PCH100_REG_PREOP; swseq_data.reg_optype = PCH100_REG_OPTYPE; @@ -1682,6 +1671,9 @@ hwseq_data.only_4k = true; hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE; } else { + num_freg = 5; + num_pr = 5; + reg_pr0 = ICH9_REG_PR0; swseq_data.reg_ssfsc = ICH9_REG_SSFS; swseq_data.reg_preop = ICH9_REG_PREOP; swseq_data.reg_optype = ICH9_REG_OPTYPE; @@ -1805,7 +1797,7 @@ msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); /* Handle FREGx and FRAP registers */ - for (i = 0; i < 5; i++) + for (i = 0; i < num_freg; i++) ich_spi_rw_restricted |= ich9_handle_frap(tmp, i); if (ich_spi_rw_restricted) msg_pwarn("Not all flash regions are freely accessible by flashrom. This is " @@ -1814,11 +1806,11 @@ } /* Handle PR registers */ - for (i = 0; i < 5; i++) { + for (i = 0; i < num_pr; i++) { /* if not locked down try to disable PR locks first */ if (!ichspi_lock) - ich9_set_pr(i, 0, 0, ich_gen); - ich_spi_rw_restricted |= ich9_handle_pr(i, ich_gen); + ich9_set_pr(reg_pr0, i, 0, 0); + ich_spi_rw_restricted |= ich9_handle_pr(reg_pr0, i); } if (ich_spi_rw_restricted) { -- To view, visit https://review.coreboot.org/18958 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I91ef5ad2c055593bd40ecfc17dcd71b8ef27aeee Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by Nico Huber (Code Review) 23 Mar '17

23 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18959 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... fixup! flashrom: Add Skylake platform support Update pretty-print functions Change-Id: Ie1d34b3907ab91cce513b0f6b36e1459f91839f6 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ichspi.c 1 file changed, 23 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/59/18959/1 diff --git a/ichspi.c b/ichspi.c index ed14338..746b100 100644 --- a/ichspi.c +++ b/ichspi.c @@ -37,14 +37,17 @@ /* Added HSFS Status bits */ #define HSFS_WRSDIS_OFF 11 /* 11: Flash Configuration Lock-Down */ -#define HSFS_WRSDIS (0x1 << HSFSC_WRSDIS_OFF) -#define HSFS_PRR34LCKDN_OFF 12 /* 12: PRR3 PRR4 Lock-Down */ -#define HSFS_PRR34LCKDN (0x1 << HSFSC_PRR34LCKDN_OFF) +#define HSFS_WRSDIS (0x1 << HSFS_WRSDIS_OFF) +#define HSFS_PRR34_LOCKDN_OFF 12 /* 12: PRR3 PRR4 Lock-Down */ +#define HSFS_PRR34_LOCKDN (0x1 << HSFS_PRR34_LOCKDN_OFF) /* HSFS_BERASE vanished */ /* Changed HSFC Control bits */ #define PCH100_HSFC_FCYCLE_OFF 1 /* 1-4: FLASH Cycle */ #define PCH100_HSFC_FCYCLE (0xf << PCH100_HSFC_FCYCLE_OFF) +/* New HSFC Control bit */ +#define HSFC_WET_OFF 5 /* 5: Write Enable Type */ +#define HSFC_WET (0x1 << HSFC_WET_OFF) #define PCH100_FADDR_FLA 0x07ffffff @@ -371,7 +374,8 @@ ops->preop[1]); } -#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +#define _pprint_reg(bit, mask, off, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & mask) >> off) +#define pprint_reg(reg, bit, val, sep) _pprint_reg(bit, reg##_##bit, reg##_##bit##_OFF, val, sep) static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) { @@ -379,8 +383,14 @@ pprint_reg(HSFS, FDONE, reg_val, ", "); pprint_reg(HSFS, FCERR, reg_val, ", "); pprint_reg(HSFS, AEL, reg_val, ", "); - pprint_reg(HSFS, BERASE, reg_val, ", "); + if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT) { + pprint_reg(HSFS, BERASE, reg_val, ", "); + } pprint_reg(HSFS, SCIP, reg_val, ", "); + if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) { + pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", "); + pprint_reg(HSFS, WRSDIS, reg_val, ", "); + } pprint_reg(HSFS, FDOPSS, reg_val, ", "); pprint_reg(HSFS, FDV, reg_val, ", "); pprint_reg(HSFS, FLOCKDN, reg_val, "\n"); @@ -390,7 +400,12 @@ { msg_pdbg("HSFC: "); pprint_reg(HSFC, FGO, reg_val, ", "); - pprint_reg(HSFC, FCYCLE, reg_val, ", "); + if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT) { + pprint_reg(HSFC, FCYCLE, reg_val, ", "); + } else { + _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", "); + pprint_reg(HSFC, WET, reg_val, ", "); + } pprint_reg(HSFC, FDBC, reg_val, ", "); pprint_reg(HSFC, SME, reg_val, "\n"); } @@ -422,12 +437,12 @@ pprint_reg(DLOCK, BMWAG_LOCKDN, reg_val, ", "); pprint_reg(DLOCK, BMRAG_LOCKDN, reg_val, ", "); pprint_reg(DLOCK, SBMWAG_LOCKDN, reg_val, ", "); - pprint_reg(DLOCK, SBMRAG_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, SBMRAG_LOCKDN, reg_val, ",\n "); pprint_reg(DLOCK, PR0_LOCKDN, reg_val, ", "); pprint_reg(DLOCK, PR1_LOCKDN, reg_val, ", "); pprint_reg(DLOCK, PR2_LOCKDN, reg_val, ", "); pprint_reg(DLOCK, PR3_LOCKDN, reg_val, ", "); - pprint_reg(DLOCK, PR4_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, PR4_LOCKDN, reg_val, ",\n "); pprint_reg(DLOCK, SSEQ_LOCKDN, reg_val, "\n"); } -- To view, visit https://review.coreboot.org/18959 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ie1d34b3907ab91cce513b0f6b36e1459f91839f6 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by Nico Huber (Code Review) 23 Mar '17

23 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18957 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... fixup! flashrom: Add Skylake platform support Change-Id: Iaae8542a7aa793df98385c6ccd118e1209336047 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ichspi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/57/18957/1 diff --git a/ichspi.c b/ichspi.c index b45c89f..e8fb74d 100644 --- a/ichspi.c +++ b/ichspi.c @@ -43,8 +43,8 @@ /* HSFS_BERASE vanished */ /* Changed HSFC Control bits */ -#define PCH100_HSFC_FCYCLE_OFF 1 /* 1-3: FLASH Cycle */ -#define PCH100_HSFC_FCYCLE (0x7 << PCH100_HSFC_FCYCLE_OFF) +#define PCH100_HSFC_FCYCLE_OFF 1 /* 1-4: FLASH Cycle */ +#define PCH100_HSFC_FCYCLE (0xf << PCH100_HSFC_FCYCLE_OFF) #define PCH100_FADDR_FLA 0x07ffffff -- To view, visit https://review.coreboot.org/18957 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Iaae8542a7aa793df98385c6ccd118e1209336047 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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