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Change in flashrom[staging]: flashrom: Add Skylake platform support
by build bot (Jenkins) (Code Review) 21 Mar '17

21 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18932 ) Change subject: flashrom: Add Skylake platform support ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/flashrom_gerrit/43/ : FAILURE https://qa.coreboot.org/job/flashrom-customrules/26/ : SUCCESS -- To view, visit https://review.coreboot.org/18932 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0e8ad2d3281c148414fd357427fcd445afc7d045 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by Nico Huber (Code Review) 21 Mar '17

21 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18940 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... fixup! flashrom: Add Skylake platform support ichspi: Decode DLOCK register Change-Id: Idc57fec7c2007926dafd8b84119d15e86c5e111d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ichspi.c 1 file changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/18940/1 diff --git a/ichspi.c b/ichspi.c index 413d97c..3ff0c55 100644 --- a/ichspi.c +++ b/ichspi.c @@ -48,6 +48,28 @@ #define PCH100_FADDR_FLA 0x07ffffff +#define PCH100_REG_DLOCK 0x0c /* 32 Bits Discrete Lock Bits */ +#define DLOCK_BMWAG_LOCKDN_OFF 0 +#define DLOCK_BMWAG_LOCKDN (0x1 << DLOCK_BMWAG_LOCKDN_OFF) +#define DLOCK_BMRAG_LOCKDN_OFF 1 +#define DLOCK_BMRAG_LOCKDN (0x1 << DLOCK_BMRAG_LOCKDN_OFF) +#define DLOCK_SBMWAG_LOCKDN_OFF 2 +#define DLOCK_SBMWAG_LOCKDN (0x1 << DLOCK_SBMWAG_LOCKDN_OFF) +#define DLOCK_SBMRAG_LOCKDN_OFF 3 +#define DLOCK_SBMRAG_LOCKDN (0x1 << DLOCK_SBMRAG_LOCKDN_OFF) +#define DLOCK_PR0_LOCKDN_OFF 8 +#define DLOCK_PR0_LOCKDN (0x1 << DLOCK_PR0_LOCKDN_OFF) +#define DLOCK_PR1_LOCKDN_OFF 9 +#define DLOCK_PR1_LOCKDN (0x1 << DLOCK_PR1_LOCKDN_OFF) +#define DLOCK_PR2_LOCKDN_OFF 10 +#define DLOCK_PR2_LOCKDN (0x1 << DLOCK_PR2_LOCKDN_OFF) +#define DLOCK_PR3_LOCKDN_OFF 11 +#define DLOCK_PR3_LOCKDN (0x1 << DLOCK_PR3_LOCKDN_OFF) +#define DLOCK_PR4_LOCKDN_OFF 12 +#define DLOCK_PR4_LOCKDN (0x1 << DLOCK_PR4_LOCKDN_OFF) +#define DLOCK_SSEQ_LOCKDN_OFF 16 +#define DLOCK_SSEQ_LOCKDN (0x1 << DLOCK_SSEQ_LOCKDN_OFF) + #define PCH100_REG_FPR0 0x84 /* 32 Bytes Protected Range 0 */ #define PCH100_REG_SSFSC 0xA0 /* 32 Bits Status (8) + Control (24) */ @@ -391,6 +413,21 @@ pprint_reg(SSFC, DBC, reg_val, ", "); pprint_reg(SSFC, SME, reg_val, ", "); pprint_reg(SSFC, SCF, reg_val, "\n"); +} + +static void prettyprint_pch100_reg_dlock(const uint32_t reg_val) +{ + msg_pdbg("DLOCK: "); + pprint_reg(DLOCK, BMWAG_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, BMRAG_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, SBMWAG_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, SBMRAG_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, PR0_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, PR1_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, PR2_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, PR3_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, PR4_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, SSEQ_LOCKDN, reg_val, "\n"); } static struct { @@ -1751,6 +1788,12 @@ tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR); msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp); + if (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT) { + const uint32_t dlock = mmio_readl(ich_spibar + PCH100_REG_DLOCK); + msg_pdbg("0x0c: 0x%08x (DLOCK)\n", dlock); + prettyprint_pch100_reg_dlock(dlock); + } + if (desc_valid) { tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); -- To view, visit https://review.coreboot.org/18940 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Idc57fec7c2007926dafd8b84119d15e86c5e111d Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by Nico Huber (Code Review) 21 Mar '17

21 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18939 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... fixup! flashrom: Add Skylake platform support ich_descriptors: Decode component density for Sunrise Point Change-Id: I825b3a6d33bc5dcf41fd58a71c666dfecad32809 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/39/18939/1 diff --git a/ich_descriptors.c b/ich_descriptors.c index 32cc804..92318df 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -829,6 +829,7 @@ case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: case CHIPSET_9_SERIES_WILDCAT_POINT: + case CHIPSET_100_SERIES_SUNRISE_POINT: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; } else { -- To view, visit https://review.coreboot.org/18939 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I825b3a6d33bc5dcf41fd58a71c666dfecad32809 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by Nico Huber (Code Review) 21 Mar '17

21 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18938 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... fixup! flashrom: Add Skylake platform support ichspi: Abstract over swseq register offsets and consolidate init. SSFS/C register offset is guessed. Change-Id: I0ad46f7944d92d3381975c5e10af0918ec163782 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ichspi.c 1 file changed, 64 insertions(+), 160 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/38/18938/1 diff --git a/ichspi.c b/ichspi.c index 3b7e5d8..413d97c 100644 --- a/ichspi.c +++ b/ichspi.c @@ -50,9 +50,10 @@ #define PCH100_REG_FPR0 0x84 /* 32 Bytes Protected Range 0 */ -#define PCH100_REG_PREOP_OPTYPE 0xA4 /* 32 Bits */ -#define PCH100_REG_OPMENU_LOWER 0xA8 /* 32 Bits */ -#define PCH100_REG_OPMENU_UPPER 0xAC /* 32 Bits */ +#define PCH100_REG_SSFSC 0xA0 /* 32 Bits Status (8) + Control (24) */ +#define PCH100_REG_PREOP 0xA4 /* 16 Bits */ +#define PCH100_REG_OPTYPE 0xA6 /* 16 Bits */ +#define PCH100_REG_OPMENU 0xA8 /* 64 Bits */ /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ @@ -392,6 +393,13 @@ pprint_reg(SSFC, SCF, reg_val, "\n"); } +static struct { + size_t reg_ssfsc; + size_t reg_preop; + size_t reg_optype; + size_t reg_opmenu; +} swseq_data; + static uint8_t lookup_spi_type(uint8_t opcode) { int a; @@ -495,18 +503,12 @@ opmenu[0] = REGREAD32(ICH7_REG_OPMENU); opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4); break; - case CHIPSET_100_SERIES_SUNRISE_POINT: - preop = REGREAD16(PCH100_REG_PREOP_OPTYPE); - optype = REGREAD16(PCH100_REG_PREOP_OPTYPE + 2); - opmenu[0] = REGREAD32(PCH100_REG_OPMENU_LOWER); - opmenu[1] = REGREAD32(PCH100_REG_OPMENU_UPPER); - break; case CHIPSET_ICH8: default: /* Future version might behave the same */ - preop = REGREAD16(ICH9_REG_PREOP); - optype = REGREAD16(ICH9_REG_OPTYPE); - opmenu[0] = REGREAD32(ICH9_REG_OPMENU); - opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4); + preop = REGREAD16(swseq_data.reg_preop); + optype = REGREAD16(swseq_data.reg_optype); + opmenu[0] = REGREAD32(swseq_data.reg_opmenu); + opmenu[1] = REGREAD32(swseq_data.reg_opmenu + 4); break; } @@ -582,32 +584,19 @@ mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU); mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); break; - case CHIPSET_100_SERIES_SUNRISE_POINT: - /* Register undo only for enable_undo=1, i.e. first call. */ - if (enable_undo) { - rmmio_valw(ich_spibar + PCH100_REG_PREOP_OPTYPE); - rmmio_valw(ich_spibar + PCH100_REG_PREOP_OPTYPE + 2); - rmmio_vall(ich_spibar + PCH100_REG_OPMENU_LOWER); - rmmio_vall(ich_spibar + PCH100_REG_OPMENU_UPPER); - } - mmio_writew(preop, ich_spibar + PCH100_REG_PREOP_OPTYPE); - mmio_writew(optype, ich_spibar + PCH100_REG_PREOP_OPTYPE + 2); - mmio_writel(opmenu[0], ich_spibar + PCH100_REG_OPMENU_LOWER); - mmio_writel(opmenu[1], ich_spibar + PCH100_REG_OPMENU_UPPER); - break; case CHIPSET_ICH8: default: /* Future version might behave the same */ /* Register undo only for enable_undo=1, i.e. first call. */ if (enable_undo) { - rmmio_valw(ich_spibar + ICH9_REG_PREOP); - rmmio_valw(ich_spibar + ICH9_REG_OPTYPE); - rmmio_vall(ich_spibar + ICH9_REG_OPMENU); - rmmio_vall(ich_spibar + ICH9_REG_OPMENU + 4); + rmmio_valw(ich_spibar + swseq_data.reg_preop); + rmmio_valw(ich_spibar + swseq_data.reg_optype); + rmmio_vall(ich_spibar + swseq_data.reg_opmenu); + rmmio_vall(ich_spibar + swseq_data.reg_opmenu + 4); } - mmio_writew(preop, ich_spibar + ICH9_REG_PREOP); - mmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE); - mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU); - mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); + mmio_writew(preop, ich_spibar + swseq_data.reg_preop); + mmio_writew(optype, ich_spibar + swseq_data.reg_optype); + mmio_writel(opmenu[0], ich_spibar + swseq_data.reg_opmenu); + mmio_writel(opmenu[1], ich_spibar + swseq_data.reg_opmenu + 4); break; } @@ -894,7 +883,7 @@ } timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ - while ((REGREAD8(ICH9_REG_SSFS) & SSFS_SCIP) && --timeout) { + while ((REGREAD8(swseq_data.reg_ssfsc) & SSFS_SCIP) && --timeout) { programmer_delay(10); } if (!timeout) { @@ -912,12 +901,12 @@ ich_fill_data(data, datalength, ICH9_REG_FDATA0); /* Assemble SSFS + SSFC */ - temp32 = REGREAD32(ICH9_REG_SSFS); + temp32 = REGREAD32(swseq_data.reg_ssfsc); /* Keep reserved bits only */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* Clear cycle done and cycle error status registers */ temp32 |= (SSFS_FDONE | SSFS_FCERR); - REGWRITE32(ICH9_REG_SSFS, temp32); + REGWRITE32(swseq_data.reg_ssfsc, temp32); /* Use 20 MHz */ temp32 |= SSFC_SCF_20MHZ; @@ -971,21 +960,21 @@ temp32 |= SSFC_SCGO; /* write it */ - REGWRITE32(ICH9_REG_SSFS, temp32); + REGWRITE32(swseq_data.reg_ssfsc, temp32); /* Wait for Cycle Done Status or Flash Cycle Error. */ - while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_FDONE | SSFS_FCERR)) == 0) && + while (((REGREAD32(swseq_data.reg_ssfsc) & (SSFS_FDONE | SSFS_FCERR)) == 0) && --timeout) { programmer_delay(10); } if (!timeout) { - msg_perr("timeout, ICH9_REG_SSFS=0x%08x\n", - REGREAD32(ICH9_REG_SSFS)); + msg_perr("timeout, REG_SSFS=0x%08x\n", + REGREAD32(swseq_data.reg_ssfsc)); return 1; } /* FIXME make sure we do not needlessly cause transaction errors. */ - temp32 = REGREAD32(ICH9_REG_SSFS); + temp32 = REGREAD32(swseq_data.reg_ssfsc); if (temp32 & SSFS_FCERR) { msg_perr("Transaction error!\n"); prettyprint_ich9_reg_ssfs(temp32); @@ -993,7 +982,7 @@ /* keep reserved bits */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* Clear the transaction error. */ - REGWRITE32(ICH9_REG_SSFS, temp32 | SSFS_FCERR); + REGWRITE32(swseq_data.reg_ssfsc, temp32 | SSFS_FCERR); return 1; } @@ -1644,6 +1633,25 @@ ich_generation = ich_gen; ich_spibar = spibar; + /* Moving registers / bits */ + if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) { + swseq_data.reg_ssfsc = PCH100_REG_SSFSC; + swseq_data.reg_preop = PCH100_REG_PREOP; + swseq_data.reg_optype = PCH100_REG_OPTYPE; + swseq_data.reg_opmenu = PCH100_REG_OPMENU; + hwseq_data.addr_mask = PCH100_FADDR_FLA; + hwseq_data.only_4k = true; + hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE; + } else { + swseq_data.reg_ssfsc = ICH9_REG_SSFS; + swseq_data.reg_preop = ICH9_REG_PREOP; + swseq_data.reg_optype = ICH9_REG_OPTYPE; + swseq_data.reg_opmenu = ICH9_REG_OPMENU; + hwseq_data.addr_mask = ICH9_FADDR_FLA; + hwseq_data.only_4k = false; + hwseq_data.hsfc_fcycle = HSFC_FCYCLE; + } + switch (ich_generation) { case CHIPSET_ICH7: case CHIPSET_TUNNEL_CREEK: @@ -1679,112 +1687,8 @@ ich_set_bbar(0); register_spi_master(&spi_master_ich7); break; - case CHIPSET_100_SERIES_SUNRISE_POINT: - hwseq_data.addr_mask = PCH100_FADDR_FLA; - hwseq_data.only_4k = true; - hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE; - - arg = extract_programmer_param("ich_spi_mode"); - if (arg && !strcmp(arg, "hwseq")) { - ich_spi_mode = ich_hwseq; - msg_pspew("user selected hwseq\n"); - } else if (arg && !strcmp(arg, "swseq")) { - ich_spi_mode = ich_swseq; - msg_pspew("user selected swseq\n"); - } else if (arg && !strcmp(arg, "auto")) { - msg_pspew("user selected auto\n"); - ich_spi_mode = ich_auto; - } else if (arg && !strlen(arg)) { - msg_perr("Missing argument for ich_spi_mode.\n"); - free(arg); - return ERROR_FATAL; - } else if (arg) { - msg_perr("Unknown argument for ich_spi_mode: %s\n", - arg); - free(arg); - return ERROR_FATAL; - } - free(arg); - tmp = mmio_readl(ich_spibar + ICH9_REG_HSFS); - msg_pdbg("0x04: 0x%04x (HSFSC)\n", tmp); - if (tmp & HSFS_FLOCKDN) { - msg_perr("WARNING: SPI Configuration " - "Lockdown activated.\n"); - ichspi_lock = 1; - } - if (tmp & HSFS_FDV) - desc_valid = 1; - - if (!(tmp & HSFS_FDOPSS) && desc_valid) - msg_perr("The Flash Descriptor Security Override " - "Strap-Pin is set. Restrictions implied\n" - "by the FRAP and FREG registers are NOT in " - "effect. Please note that Protected\n" - "Range (PR) restrictions still apply.\n"); - ich_init_opcodes(); - - tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR); - msg_pdbg("0x08: 0x%08x (FADDR)\n", tmp); - if (desc_valid) { - tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); - msg_cdbg("0x50: 0x%08x (FRAP)\n", tmp); - msg_cdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); - msg_cdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); - msg_cdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); - msg_cdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); - - /* Decode and print FREGx and FRAP registers */ - for (i = 0; i < 5; i++) - ich9_handle_frap(tmp, i); - } - /* try to disable PR locks before printing them */ - if (!ichspi_lock) - for (i = 0; i < 5; i++) - ich9_set_pr(i, 0, 0, ich_generation); - for (i = 0; i < 5; i++) - ich9_handle_pr(i, ich_generation); - if (desc_valid) { - if (read_ich_descriptors_via_fdo(ich_gen, ich_spibar, &desc) == ICH_RET_OK) - prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, - &desc); - /* If the descriptor is valid and indicates multiple - * flash devices we need to use hwseq to be able to - * access the second flash device. - */ - if (ich_spi_mode == ich_auto && desc.content.NC != 0) { - msg_pinfo("Enabling hardware sequencing due to " - "multiple flash chips detected.\n"); - ich_spi_mode = ich_hwseq; - } - } - - if (ich_spi_mode == ich_auto && ichspi_lock && - ich_missing_opcodes()) { - msg_pinfo("Enabling hardware sequencing because " - "some important opcode is locked.\n"); - ich_spi_mode = ich_hwseq; - } - - if (ich_spi_mode == ich_hwseq) { - if (!desc_valid) { - msg_perr("Hardware sequencing was requested " - "but the flash descriptor is not " - "valid. Aborting.\n"); - return ERROR_FATAL; - } - hwseq_data.size_comp0 = getFCBA_component_density(ich_gen, &desc, 0); - hwseq_data.size_comp1 = getFCBA_component_density(ich_gen, &desc, 1); - register_opaque_master(&opaque_master_ich_hwseq); - } else { - register_spi_master(&spi_master_ich9); - } - break; case CHIPSET_ICH8: default: /* Future version might behave the same */ - hwseq_data.addr_mask = ICH9_FADDR_FLA; - hwseq_data.only_4k = false; - hwseq_data.hsfc_fcycle = HSFC_FCYCLE; - arg = extract_programmer_param("ich_spi_mode"); if (arg && !strcmp(arg, "hwseq")) { ich_spi_mode = ich_hwseq; @@ -1884,30 +1788,30 @@ msg_pinfo("Continuing with write support because the user forced us to!\n"); } - tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS); - msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); + tmp = mmio_readl(ich_spibar + swseq_data.reg_ssfsc); + msg_pdbg("0x%zx: 0x%02x (SSFS)\n", swseq_data.reg_ssfsc, tmp & 0xff); prettyprint_ich9_reg_ssfs(tmp); if (tmp & SSFS_FCERR) { msg_pdbg("Clearing SSFS.FCERR\n"); - mmio_writeb(SSFS_FCERR, ich_spibar + ICH9_REG_SSFS); + mmio_writeb(SSFS_FCERR, ich_spibar + swseq_data.reg_ssfsc); } - msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8); + msg_pdbg("0x%zx: 0x%06x (SSFC)\n", swseq_data.reg_ssfsc + 1, tmp >> 8); prettyprint_ich9_reg_ssfc(tmp); - msg_pdbg("0x94: 0x%04x (PREOP)\n", - mmio_readw(ich_spibar + ICH9_REG_PREOP)); - msg_pdbg("0x96: 0x%04x (OPTYPE)\n", - mmio_readw(ich_spibar + ICH9_REG_OPTYPE)); - msg_pdbg("0x98: 0x%08x (OPMENU)\n", - mmio_readl(ich_spibar + ICH9_REG_OPMENU)); - msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", - mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); + msg_pdbg("0x%zx: 0x%04x (PREOP)\n", + swseq_data.reg_preop, mmio_readw(ich_spibar + swseq_data.reg_preop)); + msg_pdbg("0x%zx: 0x%04x (OPTYPE)\n", + swseq_data.reg_optype, mmio_readw(ich_spibar + swseq_data.reg_optype)); + msg_pdbg("0x%zx: 0x%08x (OPMENU)\n", + swseq_data.reg_opmenu, mmio_readl(ich_spibar + swseq_data.reg_opmenu)); + msg_pdbg("0x%zx: 0x%08x (OPMENU+4)\n", + swseq_data.reg_opmenu + 4, mmio_readl(ich_spibar + swseq_data.reg_opmenu + 4)); if (ich_generation == CHIPSET_ICH8 && desc_valid) { tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); msg_pdbg("VSCC: "); prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, true); - } else { + } else if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT) { if (ich_generation != CHIPSET_BAYTRAIL && desc_valid) { ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", -- To view, visit https://review.coreboot.org/18938 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I0ad46f7944d92d3381975c5e10af0918ec163782 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by Nico Huber (Code Review) 21 Mar '17

21 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18937 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... fixup! flashrom: Add Skylake platform support ichspi: Consolidate copy-pasta hwseq code Change-Id: I79d0c6284397ca382ce8e531c6f9490c74d31cc1 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ichspi.c 1 file changed, 31 insertions(+), 234 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/37/18937/1 diff --git a/ichspi.c b/ichspi.c index 81da495..3b7e5d8 100644 --- a/ichspi.c +++ b/ichspi.c @@ -46,6 +46,8 @@ #define PCH100_HSFC_FCYCLE_OFF 1 /* 1-3: FLASH Cycle */ #define PCH100_HSFC_FCYCLE (0x7 << PCH100_HSFC_FCYCLE_OFF) +#define PCH100_FADDR_FLA 0x07ffffff + #define PCH100_REG_FPR0 0x84 /* 32 Bytes Protected Range 0 */ #define PCH100_REG_PREOP_OPTYPE 0xA4 /* 32 Bits */ @@ -85,6 +87,7 @@ #define HSFC_SME (0x1 << HSFC_SME_OFF) #define ICH9_REG_FADDR 0x08 /* 32 Bits */ +#define ICH9_FADDR_FLA 0x01ffffff #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ #define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */ @@ -1155,13 +1158,16 @@ static struct hwseq_data { uint32_t size_comp0; uint32_t size_comp1; + uint32_t addr_mask; + bool only_4k; + uint32_t hsfc_fcycle; } hwseq_data; -/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ +/* Sets FLA in FADDR to (addr & hwseq_data.addr_mask) without touching other bits. */ static void ich_hwseq_set_addr(uint32_t addr) { - uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; - REGWRITE32(ICH9_REG_FADDR, (addr & 0x01FFFFFF) | addr_old); + uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~hwseq_data.addr_mask; + REGWRITE32(ICH9_REG_FADDR, (addr & hwseq_data.addr_mask) | addr_old); } /* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes @@ -1173,17 +1179,18 @@ */ static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr) { - uint8_t enc_berase; static const uint32_t dec_berase[4] = { 256, 4 * 1024, 8 * 1024, 64 * 1024 }; + const uint8_t enc_berase = + hwseq_data.only_4k ? 1 : + (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> HSFS_BERASE_OFF; ich_hwseq_set_addr(addr); - enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> - HSFS_BERASE_OFF; + return dec_berase[enc_berase]; } @@ -1205,7 +1212,7 @@ } REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); if (!timeout) { - addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask; msg_perr("Timeout error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); @@ -1215,7 +1222,7 @@ } if (hsfs & HSFS_FCERR) { - addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask; msg_perr("Transaction error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); @@ -1243,7 +1250,10 @@ flash->chip->total_size = total_size / 1024; eraser = &(flash->chip->block_erasers[0]); - boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + if (!hwseq_data.only_4k) + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + else + boundary = 0; size_high = total_size - boundary; erase_size_high = ich_hwseq_get_erase_block_size(boundary); @@ -1317,7 +1327,7 @@ REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); hsfc = REGREAD16(ICH9_REG_HSFC); - hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ hsfc |= HSFC_FGO; /* start */ msg_pdbg("HSFC used for block erasing: "); @@ -1354,7 +1364,7 @@ ich_hwseq_set_addr(addr); hsfc = REGREAD16(ICH9_REG_HSFC); - hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~hwseq_data.hsfc_fcycle; /* set read operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); @@ -1395,7 +1405,7 @@ block_len = min(block_len, 256 - (addr & 0xFF)); ich_fill_data(buf, block_len, ICH9_REG_FDATA0); hsfc = REGREAD16(ICH9_REG_HSFC); - hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ @@ -1404,218 +1414,6 @@ REGWRITE16(ICH9_REG_HSFC, hsfc); if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) - return -1; - addr += block_len; - buf += block_len; - len -= block_len; - } - return 0; -} - -/* Routines for PCH */ - -/* Sets FLA in FADDR to (addr & 0x07FFFFFF) without touching other bits. */ -static void pch_hwseq_set_addr(uint32_t addr) -{ - uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x07FFFFFF; - REGWRITE32(ICH9_REG_FADDR, (addr & 0x07FFFFFF) | addr_old); -} - -/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes - * of the block containing this address. May return nonsense if the address is - * not valid. The erase block size for a specific address depends on the flash - * partition layout as specified by FPB and the partition properties as defined - * by UVSCC and LVSCC respectively. An alternative to implement this method - * would be by querying FPB and the respective VSCC register directly. - */ -static uint32_t pch_hwseq_get_erase_block_size(unsigned int addr) -{ - pch_hwseq_set_addr(addr); - return 4 * 1024; -} - -/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. - Resets all error flags in HSFS. - Returns 0 if the cycle completes successfully without errors within - timeout us, 1 on errors. */ -static int pch_hwseq_wait_for_cycle_complete(unsigned int timeout, - unsigned int len) -{ - uint16_t hsfs; - uint32_t addr; - - timeout /= 8; /* scale timeout duration to counter */ - while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & - (HSFS_FDONE | HSFS_FCERR)) == 0) && - --timeout) { - programmer_delay(8); - } - REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); - if (!timeout) { - addr = REGREAD32(ICH9_REG_FADDR) & 0x07FFFFFF; - msg_perr("Timeout error between offset 0x%08x and " - "0x%08x (= 0x%08x + %d)!\n", - addr, addr + len - 1, addr, len - 1); - return 1; - } - - if (hsfs & HSFS_FCERR) { - addr = REGREAD32(ICH9_REG_FADDR) & 0x07FFFFFF; - msg_perr("Transaction error between offset 0x%08x and " - "0x%08x (= 0x%08x + %d)!\n", - addr, addr + len - 1, addr, len - 1); - return 1; - } - return 0; -} - - -int pch_hwseq_probe(struct flashctx *flash) -{ - uint32_t total_size, boundary = 0; /*There are no partitions in flash*/ - uint32_t erase_size_high, size_high; - struct block_eraser *eraser; - - total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1; - msg_cdbg("Found %d attached SPI flash chip", - (hwseq_data.size_comp1 != 0) ? 2 : 1); - if (hwseq_data.size_comp1 != 0) - msg_cdbg("s with a combined"); - else - msg_cdbg(" with a"); - msg_cdbg(" density of %d kB.\n", total_size / 1024); - flash->chip->total_size = total_size / 1024; - eraser = &(flash->chip->block_erasers[0]); - size_high = total_size - boundary; - erase_size_high = pch_hwseq_get_erase_block_size(boundary); - eraser->eraseblocks[0].size = erase_size_high; - eraser->eraseblocks[0].count = size_high / erase_size_high; - msg_cdbg("There are %d erase blocks with %d B each.\n", - size_high / erase_size_high, erase_size_high); - flash->chip->tested = TEST_OK_PREW; - return 1; -} - -int pch_hwseq_block_erase(struct flashctx *flash, - unsigned int addr, - unsigned int len) -{ - uint32_t erase_block; - uint16_t hsfc; - uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ - - erase_block = pch_hwseq_get_erase_block_size(addr); - if (len != erase_block) { - msg_cerr("Erase block size for address 0x%06x is %d B, " - "but requested erase block size is %d B. " - "Not erasing anything.\n", addr, erase_block, len); - return -1; - } - - /* Although the hardware supports this (it would erase the whole block - * containing the address) we play safe here. */ - if (addr % erase_block != 0) { - msg_cerr("Erase address 0x%06x is not aligned to the erase " - "block boundary (any multiple of %d). " - "Not erasing anything.\n", addr, erase_block); - return -1; - } - - if (addr + len > flash->chip->total_size * 1024) { - msg_perr("Request to erase some inaccessible memory address(es)" - " (addr=0x%x, len=%d). " - "Not erasing anything.\n", addr, len); - return -1; - } - - msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); - - /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ - REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); - - hsfc = REGREAD16(ICH9_REG_HSFC); - hsfc &= ~PCH100_HSFC_FCYCLE; /* clear operation */ - hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ - hsfc |= HSFC_FGO; /* start */ - msg_pdbg("HSFC used for block erasing: "); - REGWRITE16(ICH9_REG_HSFC, hsfc); - - if (pch_hwseq_wait_for_cycle_complete(timeout, len)) - return -1; - return 0; -} - -int pch_hwseq_read(struct flashctx *flash, uint8_t *buf, unsigned int addr, - unsigned int len) -{ - uint16_t hsfc; - uint16_t timeout = 100 * 60; - uint8_t block_len; - - - if ((addr + len) > (flash->chip->total_size * 1024)) { - msg_perr("Request to read from an inaccessible memory address " - "(addr=0x%x, len=%d).\n", addr, len); - return -1; - } - - msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); - /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - - REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); - - while (len > 0) { - block_len = min(len, flash->mst->opaque.max_data_read); - pch_hwseq_set_addr(addr); - hsfc = REGREAD16(ICH9_REG_HSFC); - hsfc &= ~PCH100_HSFC_FCYCLE; /* set read operation */ - hsfc &= ~HSFC_FDBC; /* clear byte count */ - /* set byte count */ - hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); - hsfc |= HSFC_FGO; /* start */ - REGWRITE16(ICH9_REG_HSFC, hsfc); - - if (pch_hwseq_wait_for_cycle_complete(timeout, block_len)) - return 1; - ich_read_data(buf, block_len, ICH9_REG_FDATA0); - addr += block_len; - buf += block_len; - len -= block_len; - } - return 0; -} - -int pch_hwseq_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, - unsigned int len) -{ - uint16_t hsfc; - uint16_t timeout = 100 * 60; - uint8_t block_len; - - if ((addr + len) > (flash->chip->total_size * 1024)) { - msg_perr("Request to write to an inaccessible memory address " - "(addr=0x%x, len=%d).\n", addr, len); - return -1; - } - - msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); - /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); - - while (len > 0) { - pch_hwseq_set_addr(addr); - block_len = min(len, flash->mst->opaque.max_data_write); - ich_fill_data(buf, block_len, ICH9_REG_FDATA0); - hsfc = REGREAD16(ICH9_REG_HSFC); - hsfc &= ~PCH100_HSFC_FCYCLE; /* clear operation */ - hsfc |= (0x2 << PCH100_HSFC_FCYCLE_OFF); /* set write operation */ - hsfc &= ~HSFC_FDBC; /* clear byte count */ - /* set byte count */ - hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); - hsfc |= HSFC_FGO; /* start */ - REGWRITE16(ICH9_REG_HSFC, hsfc); - - if (pch_hwseq_wait_for_cycle_complete(timeout, block_len)) return -1; addr += block_len; buf += block_len; @@ -1818,15 +1616,6 @@ .write_aai = default_spi_write_aai, }; -static struct opaque_master opaque_master_pch_hwseq = { - .max_data_read = 64, - .max_data_write = 64, - .probe = pch_hwseq_probe, - .read = pch_hwseq_read, - .write = pch_hwseq_write, - .erase = pch_hwseq_block_erase, -}; - static const struct opaque_master opaque_master_ich_hwseq = { .max_data_read = 64, .max_data_write = 64, @@ -1891,6 +1680,10 @@ register_spi_master(&spi_master_ich7); break; case CHIPSET_100_SERIES_SUNRISE_POINT: + hwseq_data.addr_mask = PCH100_FADDR_FLA; + hwseq_data.only_4k = true; + hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE; + arg = extract_programmer_param("ich_spi_mode"); if (arg && !strcmp(arg, "hwseq")) { ich_spi_mode = ich_hwseq; @@ -1981,13 +1774,17 @@ } hwseq_data.size_comp0 = getFCBA_component_density(ich_gen, &desc, 0); hwseq_data.size_comp1 = getFCBA_component_density(ich_gen, &desc, 1); - register_opaque_master(&opaque_master_pch_hwseq); + register_opaque_master(&opaque_master_ich_hwseq); } else { register_spi_master(&spi_master_ich9); } break; case CHIPSET_ICH8: default: /* Future version might behave the same */ + hwseq_data.addr_mask = ICH9_FADDR_FLA; + hwseq_data.only_4k = false; + hwseq_data.hsfc_fcycle = HSFC_FCYCLE; + arg = extract_programmer_param("ich_spi_mode"); if (arg && !strcmp(arg, "hwseq")) { ich_spi_mode = ich_hwseq; -- To view, visit https://review.coreboot.org/18937 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I79d0c6284397ca382ce8e531c6f9490c74d31cc1 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by Nico Huber (Code Review) 21 Mar '17

21 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18936 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... fixup! flashrom: Add Skylake platform support Clean up register redefinitions Change-Id: If122368e852d83f0b04d58840ee3bbeccec1e36b Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.h M ichspi.c 2 files changed, 57 insertions(+), 82 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/36/18936/1 diff --git a/ich_descriptors.h b/ich_descriptors.h index dbf73e2..df4dd76 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -34,7 +34,7 @@ #define ICH_RET_OOB -4 #define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ -#define PCH100_REG_FDOC 0xB4 /* 32 bits FDOC in PCH */ +#define PCH100_REG_FDOC 0xB4 /* New offset from Sunrise Point on */ /* 0-1: reserved */ #define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ #define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) @@ -43,7 +43,7 @@ /* 15-31: reserved */ #define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ -#define PCH100_REG_FDOD 0xB8 /* 32 bits FDOD in PCH */ +#define PCH100_REG_FDOD 0xB8 /* New offset from Sunrise Point on */ /* Field locations and semantics for LVSCC, UVSCC and related words in the flash * descriptor are equal therefore they all share the same macros below. */ diff --git a/ichspi.c b/ichspi.c index ac859e0..81da495 100644 --- a/ichspi.c +++ b/ichspi.c @@ -33,6 +33,25 @@ #include "spi.h" #include "ich_descriptors.h" +/* Sunrise Point */ + +/* Added HSFS Status bits */ +#define HSFS_WRSDIS_OFF 11 /* 11: Flash Configuration Lock-Down */ +#define HSFS_WRSDIS (0x1 << HSFSC_WRSDIS_OFF) +#define HSFS_PRR34LCKDN_OFF 12 /* 12: PRR3 PRR4 Lock-Down */ +#define HSFS_PRR34LCKDN (0x1 << HSFSC_PRR34LCKDN_OFF) +/* HSFS_BERASE vanished */ + +/* Changed HSFC Control bits */ +#define PCH100_HSFC_FCYCLE_OFF 1 /* 1-3: FLASH Cycle */ +#define PCH100_HSFC_FCYCLE (0x7 << PCH100_HSFC_FCYCLE_OFF) + +#define PCH100_REG_FPR0 0x84 /* 32 Bytes Protected Range 0 */ + +#define PCH100_REG_PREOP_OPTYPE 0xA4 /* 32 Bits */ +#define PCH100_REG_OPMENU_LOWER 0xA8 /* 32 Bits */ +#define PCH100_REG_OPMENU_UPPER 0xAC /* 32 Bits */ + /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ #define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */ @@ -169,50 +188,6 @@ #define ICH7_REG_PREOP 0x54 /* 16 Bits */ #define ICH7_REG_OPTYPE 0x56 /* 16 Bits */ #define ICH7_REG_OPMENU 0x58 /* 64 Bits */ - -/*SUNRISE point*/ -/* 32 Bits Hardware Sequencing Flash Status */ -#define PCH100_REG_HSFSC 0x04 -/*Status bits*/ -#define HSFSC_FDONE_OFF 0 /* 0: Flash Cycle Done */ -#define HSFSC_FDONE (0x1 << HSFSC_FDONE_OFF) -#define HSFSC_FCERR_OFF 1 /* 1: Flash Cycle Error */ -#define HSFSC_FCERR (0x1 << HSFSC_FCERR_OFF) -#define HSFSC_AEL_OFF 2 /* 2: Access Error Log */ -#define HSFSC_AEL (0x1 << HSFSC_AEL_OFF) -#define HSFSC_SCIP_OFF 5 /* 5: SPI Cycle In Progress */ -#define HSFSC_SCIP (0x1 << HSFSC_SCIP_OFF) - /* 6-10: reserved */ -/* 11: Flash Configuration Lock-Down WRSDIS */ -#define HSFSC_WRSDIS_OFF 11 -#define HSFSC_WRSDIS (0x1 << HSFSC_WRSDIS_OFF) -#define HSFSC_PRR34LCKDN_OFF 12 -#define HSFSC_PRR34LCKDN (0x1 << HSFSC_PRR34LCKDN_OFF) -/* 13: Flash Descriptor Override Pin-Strap Status */ -#define HSFSC_FDOPSS_OFF 13 -#define HSFSC_FDOPSS (0x1 << HSFSC_FDOPSS_OFF) -#define HSFSC_FDV_OFF 14 /* 14: Flash Descriptor Valid */ -#define HSFSC_FDV (0x1 << HSFSC_FDV_OFF) -#define HSFSC_FLOCKDN_OFF 15 /* 11: Flash Configuration Lock-Down */ -#define HSFSC_FLOCKDN (0x1 << HSFSC_FLOCKDN_OFF) -/*Control bits*/ -#define HSFSC_FGO_OFF 0 /* 0: Flash Cycle Go */ -#define HSFSC_FGO (0x1 << HSFSC_FGO_OFF) -#define HSFSC_FCYCLE_OFF 1 /* 1-3: FLASH Cycle */ -#define HSFSC_FCYCLE (0x3 << HSFSC_FCYCLE_OFF) -#define HSFSC_FDBC_OFF 8 /*8-13 : Flash Data Byte Count */ -#define HSFSC_FDBC (0x3f << HSFSC_FDBC_OFF) - -#define PCH100_REG_FADDR 0x08 /* 32 Bits */ -#define PCH100_REG_FDATA0 0x10 /* 64 Bytes */ - -#define PCH100_REG_FPR0 0x84 /* 32 Bytes Protected Range 0 */ -#define PCH_WP_OFF 31 /* 31: write protection enable */ -#define PCH_RP_OFF 15 /* 15: read protection enable */ - -#define PCH100_REG_PREOP_OPTYPE 0xA4 /* 32 Bits */ -#define PCH100_REG_OPMENU_LOWER 0xA8 /* 32 Bits */ -#define PCH100_REG_OPMENU_UPPER 0xAC /* 32 Bits */ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ static int ichspi_lock = 0; @@ -1442,8 +1417,8 @@ /* Sets FLA in FADDR to (addr & 0x07FFFFFF) without touching other bits. */ static void pch_hwseq_set_addr(uint32_t addr) { - uint32_t addr_old = REGREAD32(PCH100_REG_FADDR) & ~0x07FFFFFF; - REGWRITE32(PCH100_REG_FADDR, (addr & 0x07FFFFFF) | addr_old); + uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x07FFFFFF; + REGWRITE32(ICH9_REG_FADDR, (addr & 0x07FFFFFF) | addr_old); } /* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes @@ -1470,22 +1445,22 @@ uint32_t addr; timeout /= 8; /* scale timeout duration to counter */ - while ((((hsfs = REGREAD16(PCH100_REG_HSFSC)) & - (HSFSC_FDONE | HSFSC_FCERR)) == 0) && + while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && --timeout) { programmer_delay(8); } - REGWRITE16(PCH100_REG_HSFSC, REGREAD16(PCH100_REG_HSFSC)); + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); if (!timeout) { - addr = REGREAD32(PCH100_REG_FADDR) & 0x07FFFFFF; + addr = REGREAD32(ICH9_REG_FADDR) & 0x07FFFFFF; msg_perr("Timeout error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); return 1; } - if (hsfs & HSFSC_FCERR) { - addr = REGREAD32(PCH100_REG_FADDR) & 0x07FFFFFF; + if (hsfs & HSFS_FCERR) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x07FFFFFF; msg_perr("Transaction error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); @@ -1556,14 +1531,14 @@ msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ - REGWRITE16(PCH100_REG_HSFSC, REGREAD16(PCH100_REG_HSFSC)); + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); - hsfc = REGREAD16(PCH100_REG_HSFSC + 2); - hsfc &= ~HSFSC_FCYCLE; /* clear operation */ - hsfc |= (0x3 << HSFSC_FCYCLE_OFF); /* set erase operation */ - hsfc |= HSFSC_FGO; /* start */ + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~PCH100_HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ msg_pdbg("HSFC used for block erasing: "); - REGWRITE16(PCH100_REG_HSFSC + 2, hsfc); + REGWRITE16(ICH9_REG_HSFC, hsfc); if (pch_hwseq_wait_for_cycle_complete(timeout, len)) return -1; @@ -1587,22 +1562,22 @@ msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - REGWRITE16(PCH100_REG_HSFSC, REGREAD16(PCH100_REG_HSFSC)); + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); while (len > 0) { block_len = min(len, flash->mst->opaque.max_data_read); pch_hwseq_set_addr(addr); - hsfc = REGREAD16(PCH100_REG_HSFSC + 2); - hsfc &= ~HSFSC_FCYCLE; /* set read operation */ - hsfc &= ~HSFSC_FDBC; /* clear byte count */ + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~PCH100_HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ - hsfc |= (((block_len - 1) << HSFSC_FDBC_OFF) & HSFSC_FDBC); - hsfc |= HSFSC_FGO; /* start */ - REGWRITE16(PCH100_REG_HSFSC + 2, hsfc); + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); if (pch_hwseq_wait_for_cycle_complete(timeout, block_len)) return 1; - ich_read_data(buf, block_len, PCH100_REG_FDATA0); + ich_read_data(buf, block_len, ICH9_REG_FDATA0); addr += block_len; buf += block_len; len -= block_len; @@ -1625,20 +1600,20 @@ msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - REGWRITE16(PCH100_REG_HSFSC, REGREAD16(PCH100_REG_HSFSC)); + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); while (len > 0) { pch_hwseq_set_addr(addr); block_len = min(len, flash->mst->opaque.max_data_write); - ich_fill_data(buf, block_len, PCH100_REG_FDATA0); - hsfc = REGREAD16(PCH100_REG_HSFSC + 2); - hsfc &= ~HSFSC_FCYCLE; /* clear operation */ - hsfc |= (0x2 << HSFSC_FCYCLE_OFF); /* set write operation */ - hsfc &= ~HSFSC_FDBC; /* clear byte count */ + ich_fill_data(buf, block_len, ICH9_REG_FDATA0); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~PCH100_HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << PCH100_HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ - hsfc |= (((block_len - 1) << HSFSC_FDBC_OFF) & HSFSC_FDBC); - hsfc |= HSFSC_FGO; /* start */ - REGWRITE16(PCH100_REG_HSFSC + 2, hsfc); + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); if (pch_hwseq_wait_for_cycle_complete(timeout, block_len)) return -1; @@ -1937,17 +1912,17 @@ return ERROR_FATAL; } free(arg); - tmp = mmio_readl(ich_spibar + PCH100_REG_HSFSC); + tmp = mmio_readl(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFSC)\n", tmp); - if (tmp & HSFSC_FLOCKDN) { + if (tmp & HSFS_FLOCKDN) { msg_perr("WARNING: SPI Configuration " "Lockdown activated.\n"); ichspi_lock = 1; } - if (tmp & HSFSC_FDV) + if (tmp & HSFS_FDV) desc_valid = 1; - if (!(tmp & HSFSC_FDOPSS) && desc_valid) + if (!(tmp & HSFS_FDOPSS) && desc_valid) msg_perr("The Flash Descriptor Security Override " "Strap-Pin is set. Restrictions implied\n" "by the FRAP and FREG registers are NOT in " @@ -1955,7 +1930,7 @@ "Range (PR) restrictions still apply.\n"); ich_init_opcodes(); - tmp = mmio_readl(ich_spibar + PCH100_REG_FADDR); + tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR); msg_pdbg("0x08: 0x%08x (FADDR)\n", tmp); if (desc_valid) { tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); -- To view, visit https://review.coreboot.org/18936 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: If122368e852d83f0b04d58840ee3bbeccec1e36b Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by Nico Huber (Code Review) 21 Mar '17

21 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18934 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... fixup! flashrom: Add Skylake platform support ich_descriptors: Clean up chipset-gen parameter * Make it the first parameter to comply with other functions. * Use the correct type `enum ich_chipset` instead of `int`. Change-Id: I1b43c189cd19c573935fa553ae3ff23f2aa7e251 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h M ichspi.c 3 files changed, 17 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/18934/1 diff --git a/ich_descriptors.c b/ich_descriptors.c index 07cea8a..32cc804 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -852,13 +852,12 @@ return (1 << (19 + size_enc)); } -static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, - void *spibar, int chipset) +static uint32_t read_descriptor_reg(enum ich_chipset cs, uint8_t section, uint16_t offset, void *spibar) { uint32_t control = 0; control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; - if (chipset == CHIPSET_100_SERIES_SUNRISE_POINT) { + if (cs == CHIPSET_100_SERIES_SUNRISE_POINT) { mmio_le_writel(control, spibar + PCH100_REG_FDOC); return mmio_le_readl(spibar + PCH100_REG_FDOD); } else { @@ -868,8 +867,7 @@ } -int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc, - int chipset) +int read_ich_descriptors_via_fdo(enum ich_chipset cs, void *spibar, struct ich_descriptors *desc) { uint8_t i; uint8_t nr; @@ -899,15 +897,15 @@ msg_pdbg2("Reading flash descriptors mapped by the chipset via FDOC/FDOD..."); /* content section */ - desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar, chipset); - desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar, chipset); - desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar, chipset); - desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar, chipset); + desc->content.FLVALSIG = read_descriptor_reg(cs, 0, 0, spibar); + desc->content.FLMAP0 = read_descriptor_reg(cs, 0, 1, spibar); + desc->content.FLMAP1 = read_descriptor_reg(cs, 0, 2, spibar); + desc->content.FLMAP2 = read_descriptor_reg(cs, 0, 3, spibar); /* component section */ - desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar, chipset); - desc->component.FLILL = read_descriptor_reg(1, 1, spibar, chipset); - desc->component.FLPB = read_descriptor_reg(1, 2, spibar, chipset); + desc->component.FLCOMP = read_descriptor_reg(cs, 1, 0, spibar); + desc->component.FLILL = read_descriptor_reg(cs, 1, 1, spibar); + desc->component.FLPB = read_descriptor_reg(cs, 1, 2, spibar); /* region section */ nr = desc->content.NR + 1; @@ -917,12 +915,12 @@ return ICH_RET_ERR; } for (i = 0; i <= nr; i++) - desc->region.FLREGs[i] = read_descriptor_reg(2, i, spibar, chipset); + desc->region.FLREGs[i] = read_descriptor_reg(cs, 2, i, spibar); /* master section */ - desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar, chipset); - desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar, chipset); - desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar, chipset); + desc->master.FLMSTR1 = read_descriptor_reg(cs, 3, 0, spibar); + desc->master.FLMSTR2 = read_descriptor_reg(cs, 3, 1, spibar); + desc->master.FLMSTR3 = read_descriptor_reg(cs, 3, 2, spibar); /* Accessing the strap section via FDOC/D is only possible on ICH8 and * reading the upper map is impossible on all chipsets, so don't bother. diff --git a/ich_descriptors.h b/ich_descriptors.h index a53f397..dbf73e2 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -592,7 +592,7 @@ #else /* ICH_DESCRIPTORS_FROM_DUMP */ -int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc, int chipset); +int read_ich_descriptors_via_fdo(enum ich_chipset cs, void *spibar, struct ich_descriptors *desc); int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx); #endif /* ICH_DESCRIPTORS_FROM_DUMP */ diff --git a/ichspi.c b/ichspi.c index 47b019a..16bb2b5 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1991,8 +1991,7 @@ for (i = 0; i < 5; i++) ich9_handle_pr(i, ich_generation); if (desc_valid) { - if (read_ich_descriptors_via_fdo(ich_spibar, &desc, - ich_generation) == ICH_RET_OK) + if (read_ich_descriptors_via_fdo(ich_gen, ich_spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, &desc); /* If the descriptor is valid and indicates multiple @@ -2176,7 +2175,7 @@ } if (desc_valid) { - if (read_ich_descriptors_via_fdo(ich_spibar, &desc, ich_gen) == ICH_RET_OK) + if (read_ich_descriptors_via_fdo(ich_gen, ich_spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(ich_gen, &desc); /* If the descriptor is valid and indicates multiple -- To view, visit https://review.coreboot.org/18934 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I1b43c189cd19c573935fa553ae3ff23f2aa7e251 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by Nico Huber (Code Review) 21 Mar '17

21 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18935 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... fixup! flashrom: Add Skylake platform support ichspi: Drop odd, constant erase block size mapping Change-Id: Iab0a8b71a7680b8dee4f7c6c5dabc05c8436d97e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ichspi.c 1 file changed, 1 insertion(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/35/18935/1 diff --git a/ichspi.c b/ichspi.c index 16bb2b5..ac859e0 100644 --- a/ichspi.c +++ b/ichspi.c @@ -214,15 +214,6 @@ #define PCH100_REG_OPMENU_LOWER 0xA8 /* 32 Bits */ #define PCH100_REG_OPMENU_UPPER 0xAC /* 32 Bits */ -/* The minimum erase block size in PCH which is 4k -* 256, -* 4 * 1024, -* 8 * 1024, -* 64 * 1024 -*/ -#define ERASE_BLOCK_SIZE 1 - - /* ICH SPI configuration lock-down. May be set during chipset enabling. */ static int ichspi_lock = 0; @@ -1464,14 +1455,8 @@ */ static uint32_t pch_hwseq_get_erase_block_size(unsigned int addr) { - static const uint32_t dec_berase[4] = { - 256, - 4 * 1024, - 8 * 1024, - 64 * 1024 - }; pch_hwseq_set_addr(addr); - return dec_berase[ERASE_BLOCK_SIZE]; + return 4 * 1024; } /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. -- To view, visit https://review.coreboot.org/18935 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Iab0a8b71a7680b8dee4f7c6c5dabc05c8436d97e Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in flashrom[staging]: flashrom: Add Skylake platform support
by Nico Huber (Code Review) 21 Mar '17

21 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18932 ) Change subject: flashrom: Add Skylake platform support ...................................................................... flashrom: Add Skylake platform support This is a rebase of the commit in the chromium repo. Changes to `chipset_enable.c` were skipped due to many conflicts and rewritten (see parent commit). The old test doesn't apply any more. Original commit message: This patch does the below: 1. Adds Skylake PCI device ID to flashrom. 2. Maps registers from ICH to PCH BUG=chrome-os-partner:37711 TEST=On B1 SKL-Y verified, 'flashrom -p internal:ich_spi_mode=hwseq -w <coreboot image>' Change-Id: I0e8ad2d3281c148414fd357427fcd445afc7d045 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Original-Change-Id: I790617e7c1cdeefe1d476341afb25fe71a98b033 Original-Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Original-Signed-off-by: Ramya Vijaykumar <ramya.vijaykumar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265818 Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> --- M ich_descriptors.c M ich_descriptors.h M ichspi.c 3 files changed, 447 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/32/18932/1 diff --git a/ich_descriptors.c b/ich_descriptors.c index 593a375..07cea8a 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -852,16 +852,24 @@ return (1 << (19 + size_enc)); } -static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, + void *spibar, int chipset) { uint32_t control = 0; control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; - mmio_le_writel(control, spibar + ICH9_REG_FDOC); - return mmio_le_readl(spibar + ICH9_REG_FDOD); + if (chipset == CHIPSET_100_SERIES_SUNRISE_POINT) { + mmio_le_writel(control, spibar + PCH100_REG_FDOC); + return mmio_le_readl(spibar + PCH100_REG_FDOD); + } else { + mmio_le_writel(control, spibar + ICH9_REG_FDOC); + return mmio_le_readl(spibar + ICH9_REG_FDOD); + } + } -int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc) +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc, + int chipset) { uint8_t i; uint8_t nr; @@ -891,15 +899,15 @@ msg_pdbg2("Reading flash descriptors mapped by the chipset via FDOC/FDOD..."); /* content section */ - desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar); - desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar); - desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar); - desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar); + desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar, chipset); + desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar, chipset); + desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar, chipset); + desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar, chipset); /* component section */ - desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar); - desc->component.FLILL = read_descriptor_reg(1, 1, spibar); - desc->component.FLPB = read_descriptor_reg(1, 2, spibar); + desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar, chipset); + desc->component.FLILL = read_descriptor_reg(1, 1, spibar, chipset); + desc->component.FLPB = read_descriptor_reg(1, 2, spibar, chipset); /* region section */ nr = desc->content.NR + 1; @@ -908,13 +916,13 @@ __func__, nr); return ICH_RET_ERR; } - for (i = 0; i < 5; i++) - desc->region.FLREGs[i] = read_descriptor_reg(2, i, spibar); + for (i = 0; i <= nr; i++) + desc->region.FLREGs[i] = read_descriptor_reg(2, i, spibar, chipset); /* master section */ - desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar); - desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar); - desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar); + desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar, chipset); + desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar, chipset); + desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar, chipset); /* Accessing the strap section via FDOC/D is only possible on ICH8 and * reading the upper map is impossible on all chipsets, so don't bother. diff --git a/ich_descriptors.h b/ich_descriptors.h index 2c21598..a53f397 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -34,6 +34,7 @@ #define ICH_RET_OOB -4 #define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ +#define PCH100_REG_FDOC 0xB4 /* 32 bits FDOC in PCH */ /* 0-1: reserved */ #define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ #define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) @@ -42,6 +43,7 @@ /* 15-31: reserved */ #define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ +#define PCH100_REG_FDOD 0xB8 /* 32 bits FDOD in PCH */ /* Field locations and semantics for LVSCC, UVSCC and related words in the flash * descriptor are equal therefore they all share the same macros below. */ @@ -590,7 +592,7 @@ #else /* ICH_DESCRIPTORS_FROM_DUMP */ -int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc, int chipset); int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx); #endif /* ICH_DESCRIPTORS_FROM_DUMP */ diff --git a/ichspi.c b/ichspi.c index e1395ee..3c26406 100644 --- a/ichspi.c +++ b/ichspi.c @@ -170,6 +170,59 @@ #define ICH7_REG_OPTYPE 0x56 /* 16 Bits */ #define ICH7_REG_OPMENU 0x58 /* 64 Bits */ +/*SUNRISE point*/ +/* 32 Bits Hardware Sequencing Flash Status */ +#define PCH100_REG_HSFSC 0x04 +/*Status bits*/ +#define HSFSC_FDONE_OFF 0 /* 0: Flash Cycle Done */ +#define HSFSC_FDONE (0x1 << HSFSC_FDONE_OFF) +#define HSFSC_FCERR_OFF 1 /* 1: Flash Cycle Error */ +#define HSFSC_FCERR (0x1 << HSFSC_FCERR_OFF) +#define HSFSC_AEL_OFF 2 /* 2: Access Error Log */ +#define HSFSC_AEL (0x1 << HSFSC_AEL_OFF) +#define HSFSC_SCIP_OFF 5 /* 5: SPI Cycle In Progress */ +#define HSFSC_SCIP (0x1 << HSFSC_SCIP_OFF) + /* 6-10: reserved */ +/* 11: Flash Configuration Lock-Down WRSDIS */ +#define HSFSC_WRSDIS_OFF 11 +#define HSFSC_WRSDIS (0x1 << HSFSC_WRSDIS_OFF) +#define HSFSC_PRR34LCKDN_OFF 12 +#define HSFSC_PRR34LCKDN (0x1 << HSFSC_PRR34LCKDN_OFF) +/* 13: Flash Descriptor Override Pin-Strap Status */ +#define HSFSC_FDOPSS_OFF 13 +#define HSFSC_FDOPSS (0x1 << HSFSC_FDOPSS_OFF) +#define HSFSC_FDV_OFF 14 /* 14: Flash Descriptor Valid */ +#define HSFSC_FDV (0x1 << HSFSC_FDV_OFF) +#define HSFSC_FLOCKDN_OFF 15 /* 11: Flash Configuration Lock-Down */ +#define HSFSC_FLOCKDN (0x1 << HSFSC_FLOCKDN_OFF) +/*Control bits*/ +#define HSFSC_FGO_OFF 0 /* 0: Flash Cycle Go */ +#define HSFSC_FGO (0x1 << HSFSC_FGO_OFF) +#define HSFSC_FCYCLE_OFF 1 /* 1-3: FLASH Cycle */ +#define HSFSC_FCYCLE (0x3 << HSFSC_FCYCLE_OFF) +#define HSFSC_FDBC_OFF 8 /*8-13 : Flash Data Byte Count */ +#define HSFSC_FDBC (0x3f << HSFSC_FDBC_OFF) + +#define PCH100_REG_FADDR 0x08 /* 32 Bits */ +#define PCH100_REG_FDATA0 0x10 /* 64 Bytes */ + +#define PCH100_REG_FPR0 0x84 /* 32 Bytes Protected Range 0 */ +#define PCH_WP_OFF 31 /* 31: write protection enable */ +#define PCH_RP_OFF 15 /* 15: read protection enable */ + +#define PCH100_REG_PREOP_OPTYPE 0xA4 /* 32 Bits */ +#define PCH100_REG_OPMENU_LOWER 0xA8 /* 32 Bits */ +#define PCH100_REG_OPMENU_UPPER 0xAC /* 32 Bits */ + +/* The minimum erase block size in PCH which is 4k +* 256, +* 4 * 1024, +* 8 * 1024, +* 64 * 1024 +*/ +#define ERASE_BLOCK_SIZE 1 + + /* ICH SPI configuration lock-down. May be set during chipset enabling. */ static int ichspi_lock = 0; @@ -473,6 +526,12 @@ opmenu[0] = REGREAD32(ICH7_REG_OPMENU); opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4); break; + case CHIPSET_100_SERIES_SUNRISE_POINT: + preop = REGREAD16(PCH100_REG_PREOP_OPTYPE); + optype = REGREAD16(PCH100_REG_PREOP_OPTYPE + 2); + opmenu[0] = REGREAD32(PCH100_REG_OPMENU_LOWER); + opmenu[1] = REGREAD32(PCH100_REG_OPMENU_UPPER); + break; case CHIPSET_ICH8: default: /* Future version might behave the same */ preop = REGREAD16(ICH9_REG_PREOP); @@ -553,6 +612,19 @@ mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE); mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU); mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); + break; + case CHIPSET_100_SERIES_SUNRISE_POINT: + /* Register undo only for enable_undo=1, i.e. first call. */ + if (enable_undo) { + rmmio_valw(ich_spibar + PCH100_REG_PREOP_OPTYPE); + rmmio_valw(ich_spibar + PCH100_REG_PREOP_OPTYPE + 2); + rmmio_vall(ich_spibar + PCH100_REG_OPMENU_LOWER); + rmmio_vall(ich_spibar + PCH100_REG_OPMENU_UPPER); + } + mmio_writew(preop, ich_spibar + PCH100_REG_PREOP_OPTYPE); + mmio_writew(optype, ich_spibar + PCH100_REG_PREOP_OPTYPE + 2); + mmio_writel(opmenu[0], ich_spibar + PCH100_REG_OPMENU_LOWER); + mmio_writel(opmenu[1], ich_spibar + PCH100_REG_OPMENU_UPPER); break; case CHIPSET_ICH8: default: /* Future version might behave the same */ @@ -1374,6 +1446,225 @@ return 0; } +/* Routines for PCH */ + +/* Sets FLA in FADDR to (addr & 0x07FFFFFF) without touching other bits. */ +static void pch_hwseq_set_addr(uint32_t addr) +{ + uint32_t addr_old = REGREAD32(PCH100_REG_FADDR) & ~0x07FFFFFF; + REGWRITE32(PCH100_REG_FADDR, (addr & 0x07FFFFFF) | addr_old); +} + +/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes + * of the block containing this address. May return nonsense if the address is + * not valid. The erase block size for a specific address depends on the flash + * partition layout as specified by FPB and the partition properties as defined + * by UVSCC and LVSCC respectively. An alternative to implement this method + * would be by querying FPB and the respective VSCC register directly. + */ +static uint32_t pch_hwseq_get_erase_block_size(unsigned int addr) +{ + uint8_t enc_berase; + static const uint32_t dec_berase[4] = { + 256, + 4 * 1024, + 8 * 1024, + 64 * 1024 + }; + pch_hwseq_set_addr(addr); + return dec_berase[ERASE_BLOCK_SIZE]; +} + +/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. + Resets all error flags in HSFS. + Returns 0 if the cycle completes successfully without errors within + timeout us, 1 on errors. */ +static int pch_hwseq_wait_for_cycle_complete(unsigned int timeout, + unsigned int len) +{ + uint16_t hsfs; + uint32_t addr; + + timeout /= 8; /* scale timeout duration to counter */ + while ((((hsfs = REGREAD16(PCH100_REG_HSFSC)) & + (HSFSC_FDONE | HSFSC_FCERR)) == 0) && + --timeout) { + programmer_delay(8); + } + REGWRITE16(PCH100_REG_HSFSC, REGREAD16(PCH100_REG_HSFSC)); + if (!timeout) { + addr = REGREAD32(PCH100_REG_FADDR) & 0x07FFFFFF; + msg_perr("Timeout error between offset 0x%08x and " + "0x%08x (= 0x%08x + %d)!\n", + addr, addr + len - 1, addr, len - 1); + return 1; + } + + if (hsfs & HSFSC_FCERR) { + addr = REGREAD32(PCH100_REG_FADDR) & 0x07FFFFFF; + msg_perr("Transaction error between offset 0x%08x and " + "0x%08x (= 0x%08x + %d)!\n", + addr, addr + len - 1, addr, len - 1); + return 1; + } + return 0; +} + + +int pch_hwseq_probe(struct flashctx *flash) +{ + uint32_t total_size, boundary = 0; /*There are no partitions in flash*/ + uint32_t erase_size_low, size_low, erase_size_high, size_high; + struct block_eraser *eraser; + + total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1; + msg_cdbg("Found %d attached SPI flash chip", + (hwseq_data.size_comp1 != 0) ? 2 : 1); + if (hwseq_data.size_comp1 != 0) + msg_cdbg("s with a combined"); + else + msg_cdbg(" with a"); + msg_cdbg(" density of %d kB.\n", total_size / 1024); + flash->chip->total_size = total_size / 1024; + eraser = &(flash->chip->block_erasers[0]); + size_high = total_size - boundary; + erase_size_high = pch_hwseq_get_erase_block_size(boundary); + eraser->eraseblocks[0].size = erase_size_high; + eraser->eraseblocks[0].count = size_high / erase_size_high; + msg_cdbg("There are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + flash->chip->tested = TEST_OK_PREW; + return 1; +} + +int pch_hwseq_block_erase(struct flashctx *flash, + unsigned int addr, + unsigned int len) +{ + uint32_t erase_block; + uint16_t hsfc; + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + + erase_block = pch_hwseq_get_erase_block_size(addr); + if (len != erase_block) { + msg_cerr("Erase block size for address 0x%06x is %d B, " + "but requested erase block size is %d B. " + "Not erasing anything.\n", addr, erase_block, len); + return -1; + } + + /* Although the hardware supports this (it would erase the whole block + * containing the address) we play safe here. */ + if (addr % erase_block != 0) { + msg_cerr("Erase address 0x%06x is not aligned to the erase " + "block boundary (any multiple of %d). " + "Not erasing anything.\n", addr, erase_block); + return -1; + } + + if (addr + len > flash->chip->total_size * 1024) { + msg_perr("Request to erase some inaccessible memory address(es)" + " (addr=0x%x, len=%d). " + "Not erasing anything.\n", addr, len); + return -1; + } + + msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); + + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + REGWRITE16(PCH100_REG_HSFSC, REGREAD16(PCH100_REG_HSFSC)); + + hsfc = REGREAD16(PCH100_REG_HSFSC + 2); + hsfc &= ~HSFSC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFSC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFSC_FGO; /* start */ + msg_pdbg("HSFC used for block erasing: "); + REGWRITE16(PCH100_REG_HSFSC + 2, hsfc); + + if (pch_hwseq_wait_for_cycle_complete(timeout, len)) + return -1; + return 0; +} + +int pch_hwseq_read(struct flashctx *flash, uint8_t *buf, unsigned int addr, + unsigned int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + + if ((addr + len) > (flash->chip->total_size * 1024)) { + msg_perr("Request to read from an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + + REGWRITE16(PCH100_REG_HSFSC, REGREAD16(PCH100_REG_HSFSC)); + + while (len > 0) { + block_len = min(len, flash->mst->opaque.max_data_read); + pch_hwseq_set_addr(addr); + hsfc = REGREAD16(PCH100_REG_HSFSC + 2); + hsfc &= ~HSFSC_FCYCLE; /* set read operation */ + hsfc &= ~HSFSC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFSC_FDBC_OFF) & HSFSC_FDBC); + hsfc |= HSFSC_FGO; /* start */ + REGWRITE16(PCH100_REG_HSFSC + 2, hsfc); + + if (pch_hwseq_wait_for_cycle_complete(timeout, block_len)) + return 1; + ich_read_data(buf, block_len, PCH100_REG_FDATA0); + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + +int pch_hwseq_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, + unsigned int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if ((addr + len) > (flash->chip->total_size * 1024)) { + msg_perr("Request to write to an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(PCH100_REG_HSFSC, REGREAD16(PCH100_REG_HSFSC)); + + while (len > 0) { + pch_hwseq_set_addr(addr); + block_len = min(len, flash->mst->opaque.max_data_write); + ich_fill_data(buf, block_len, PCH100_REG_FDATA0); + hsfc = REGREAD16(PCH100_REG_HSFSC + 2); + hsfc &= ~HSFSC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFSC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFSC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFSC_FDBC_OFF) & HSFSC_FDBC); + hsfc |= HSFSC_FGO; /* start */ + REGWRITE16(PCH100_REG_HSFSC + 2, hsfc); + + if (pch_hwseq_wait_for_cycle_complete(timeout, block_len)) + return -1; + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + static int ich_spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds) { @@ -1487,12 +1778,20 @@ ((~((pr) >> PR_WP_OFF) & 1) << 1)) /* returns 0 if range is unused (i.e. r/w) */ -static int ich9_handle_pr(int i) +static int ich9_handle_pr(int i, int chipset) { static const char *const access_names[3] = { "locked", "read-only", "write-only" }; - uint8_t off = ICH9_REG_PR0 + (i * 4); + uint8_t off; + switch (chipset) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + off = PCH100_REG_FPR0 + (i * 4); + break; + default: + off = ICH9_REG_PR0 + (i * 4); + break; + } uint32_t pr = mmio_readl(ich_spibar + off); unsigned int rwperms = ICH_PR_PERMS(pr); @@ -1509,9 +1808,17 @@ /* Set/Clear the read and write protection enable bits of PR register @i * according to @read_prot and @write_prot. */ -static void ich9_set_pr(int i, int read_prot, int write_prot) +static void ich9_set_pr(int i, int read_prot, int write_prot, int chipset) { - void *addr = ich_spibar + ICH9_REG_PR0 + (i * 4); + void *addr; + switch (chipset) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + addr = ich_spibar + PCH100_REG_FPR0 + (i * 4); + break; + default: + addr = ich_spibar + ICH9_REG_PR0 + (i * 4); + break; + } uint32_t old = mmio_readl(addr); uint32_t new; @@ -1550,6 +1857,15 @@ .read = default_spi_read, .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, +}; + +static struct opaque_master opaque_master_pch_hwseq = { + .max_data_read = 64, + .max_data_write = 64, + .probe = pch_hwseq_probe, + .read = pch_hwseq_read, + .write = pch_hwseq_write, + .erase = pch_hwseq_block_erase, }; static const struct opaque_master opaque_master_ich_hwseq = { @@ -1614,6 +1930,103 @@ ich_init_opcodes(); ich_set_bbar(0); register_spi_master(&spi_master_ich7); + break; + case CHIPSET_100_SERIES_SUNRISE_POINT: + arg = extract_programmer_param("ich_spi_mode"); + if (arg && !strcmp(arg, "hwseq")) { + ich_spi_mode = ich_hwseq; + msg_pspew("user selected hwseq\n"); + } else if (arg && !strcmp(arg, "swseq")) { + ich_spi_mode = ich_swseq; + msg_pspew("user selected swseq\n"); + } else if (arg && !strcmp(arg, "auto")) { + msg_pspew("user selected auto\n"); + ich_spi_mode = ich_auto; + } else if (arg && !strlen(arg)) { + msg_perr("Missing argument for ich_spi_mode.\n"); + free(arg); + return ERROR_FATAL; + } else if (arg) { + msg_perr("Unknown argument for ich_spi_mode: %s\n", + arg); + free(arg); + return ERROR_FATAL; + } + free(arg); + tmp = mmio_readl(ich_spibar + PCH100_REG_HSFSC); + msg_pdbg("0x04: 0x%04x (HSFSC)\n", tmp); + if (tmp & HSFSC_FLOCKDN) { + msg_perr("WARNING: SPI Configuration " + "Lockdown activated.\n"); + ichspi_lock = 1; + } + if (tmp & HSFSC_FDV) + desc_valid = 1; + + if (!(tmp & HSFSC_FDOPSS) && desc_valid) + msg_perr("The Flash Descriptor Security Override " + "Strap-Pin is set. Restrictions implied\n" + "by the FRAP and FREG registers are NOT in " + "effect. Please note that Protected\n" + "Range (PR) restrictions still apply.\n"); + ich_init_opcodes(); + + tmp = mmio_readl(ich_spibar + PCH100_REG_FADDR); + msg_pdbg("0x08: 0x%08x (FADDR)\n", tmp); + if (desc_valid) { + tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); + msg_cdbg("0x50: 0x%08x (FRAP)\n", tmp); + msg_cdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); + msg_cdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); + msg_cdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); + msg_cdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); + + /* Decode and print FREGx and FRAP registers */ + for (i = 0; i < 5; i++) + ich9_handle_frap(tmp, i); + } + /* try to disable PR locks before printing them */ + if (!ichspi_lock) + for (i = 0; i < 5; i++) + ich9_set_pr(i, 0, 0, ich_generation); + for (i = 0; i < 5; i++) + ich9_handle_pr(i, ich_generation); + if (desc_valid) { + if (read_ich_descriptors_via_fdo(ich_spibar, &desc, + ich_generation) == ICH_RET_OK) + prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, + &desc); + /* If the descriptor is valid and indicates multiple + * flash devices we need to use hwseq to be able to + * access the second flash device. + */ + if (ich_spi_mode == ich_auto && desc.content.NC != 0) { + msg_pinfo("Enabling hardware sequencing due to " + "multiple flash chips detected.\n"); + ich_spi_mode = ich_hwseq; + } + } + + if (ich_spi_mode == ich_auto && ichspi_lock && + ich_missing_opcodes()) { + msg_pinfo("Enabling hardware sequencing because " + "some important opcode is locked.\n"); + ich_spi_mode = ich_hwseq; + } + + if (ich_spi_mode == ich_hwseq) { + if (!desc_valid) { + msg_perr("Hardware sequencing was requested " + "but the flash descriptor is not " + "valid. Aborting.\n"); + return ERROR_FATAL; + } + hwseq_data.size_comp0 = getFCBA_component_density(ich_gen, &desc, 0); + hwseq_data.size_comp1 = getFCBA_component_density(ich_gen, &desc, 1); + register_opaque_master(&opaque_master_pch_hwseq); + } else { + register_spi_master(&spi_master_ich9); + } break; case CHIPSET_ICH8: default: /* Future version might behave the same */ @@ -1700,8 +2113,8 @@ for (i = 0; i < 5; i++) { /* if not locked down try to disable PR locks first */ if (!ichspi_lock) - ich9_set_pr(i, 0, 0); - ich_spi_rw_restricted |= ich9_handle_pr(i); + ich9_set_pr(i, 0, 0, ich_gen); + ich_spi_rw_restricted |= ich9_handle_pr(i, ich_gen); } if (ich_spi_rw_restricted) { @@ -1764,7 +2177,7 @@ } if (desc_valid) { - if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) + if (read_ich_descriptors_via_fdo(ich_spibar, &desc, ich_gen) == ICH_RET_OK) prettyprint_ich_descriptors(ich_gen, &desc); /* If the descriptor is valid and indicates multiple -- To view, visit https://review.coreboot.org/18932 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I0e8ad2d3281c148414fd357427fcd445afc7d045 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support
by Nico Huber (Code Review) 21 Mar '17

21 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18933 ) Change subject: fixup! flashrom: Add Skylake platform support ...................................................................... fixup! flashrom: Add Skylake platform support Fix `unused variable` warnings. Change-Id: Ibeddffc2de6ee8384d7bf493cfb5f7d6174b31bc Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ichspi.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/33/18933/1 diff --git a/ichspi.c b/ichspi.c index 3c26406..47b019a 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1464,7 +1464,6 @@ */ static uint32_t pch_hwseq_get_erase_block_size(unsigned int addr) { - uint8_t enc_berase; static const uint32_t dec_berase[4] = { 256, 4 * 1024, @@ -1514,7 +1513,7 @@ int pch_hwseq_probe(struct flashctx *flash) { uint32_t total_size, boundary = 0; /*There are no partitions in flash*/ - uint32_t erase_size_low, size_low, erase_size_high, size_high; + uint32_t erase_size_high, size_high; struct block_eraser *eraser; total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1; -- To view, visit https://review.coreboot.org/18933 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ibeddffc2de6ee8384d7bf493cfb5f7d6174b31bc Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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