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Change in flashrom[staging]: Move register decodes into enable_flash_ich_handle_gcs()
by build bot (Jenkins) (Code Review) 17 Mar '17

17 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18882 ) Change subject: Move register decodes into enable_flash_ich_handle_gcs() ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/21/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/40/ : SUCCESS -- To view, visit https://review.coreboot.org/18882 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I40addec98cb6840763adad30f9d0e27dadce6d1e Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in flashrom[staging]: hwaccess: Constify `addr` argument of MMIO read functions
by build bot (Jenkins) (Code Review) 17 Mar '17

17 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18881 ) Change subject: hwaccess: Constify `addr` argument of MMIO read functions ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/20/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/39/ : SUCCESS -- To view, visit https://review.coreboot.org/18881 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I1419241a8332b74103b3921df2c615bdf91346a7 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in flashrom[staging]: Move register decodes into enable_flash_ich_handle_gcs()
by Nico Huber (Code Review) 17 Mar '17

17 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18882 ) Change subject: Move register decodes into enable_flash_ich_handle_gcs() ...................................................................... Move register decodes into enable_flash_ich_handle_gcs() GCS was decoded partly inside, partly outside this function. The decoding of `top_swap` was off, since passing a `uint8_t` as `bool` doesn't magically check bit0 only. While we are at it, rename this void function to enable_flash_ich_ report_gcs() as it's not doing anything. Beside debug output it doesn't have any side effects. Change-Id: I40addec98cb6840763adad30f9d0e27dadce6d1e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c 1 file changed, 18 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/82/18882/1 diff --git a/chipset_enable.c b/chipset_enable.c index b181b93..1191a4c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -584,8 +584,23 @@ return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8); } -static void enable_flash_ich_handle_gcs(struct pci_dev *dev, enum ich_chipset ich_generation, uint32_t gcs, bool top_swap) +static void enable_flash_ich_report_gcs(struct pci_dev *const dev, const enum ich_chipset ich_generation, + const uint8_t *const rcrb) { + uint32_t gcs; + bool top_swap; + + switch (ich_generation) { + case CHIPSET_BAYTRAIL: + gcs = mmio_readl(rcrb + 0); + top_swap = (gcs & 2) >> 1; + break; + default: + gcs = mmio_readl(rcrb + 0x3410); + top_swap = mmio_readb(rcrb + 0x3414) & 1; + break; + } + msg_pdbg("GCS = 0x%x: ", gcs); msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); @@ -673,7 +688,7 @@ if (rcrb == ERROR_PTR) return ERROR_FATAL; - enable_flash_ich_handle_gcs(dev, ich_generation, mmio_readl(rcrb + 0x3410), mmio_readb(rcrb + 0x3414)); + enable_flash_ich_report_gcs(dev, ich_generation, rcrb); /* Handle FWH-related parameters and initialization */ int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl); @@ -803,8 +818,7 @@ /* Handle GCS (in RCRB) */ void *rcrb = physmap("BYT RCRB", rcba, 4); - uint32_t gcs = mmio_readl(rcrb + 0); - enable_flash_ich_handle_gcs(dev, ich_generation, gcs, gcs & 0x2); + enable_flash_ich_report_gcs(dev, ich_generation, rcrb); physunmap(rcrb, 4); /* Handle fwh_idsel parameter */ -- To view, visit https://review.coreboot.org/18882 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I40addec98cb6840763adad30f9d0e27dadce6d1e Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: Handle Intel Wildcat Point _LP_ like Lynx Point LP
by Nico Huber (Code Review) 17 Mar '17

17 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18883 ) Change subject: Handle Intel Wildcat Point _LP_ like Lynx Point LP ...................................................................... Handle Intel Wildcat Point _LP_ like Lynx Point LP The subtle difference was ignored when adding these chipsets. I'm not sure how to accound for "Broadwell H" which seems not publicly documented. Maybe it's an unreleased HM9*, in which case the non-LP path should be correct. Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M ich_descriptors.c M programmer.h 3 files changed, 18 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/18883/1 diff --git a/chipset_enable.c b/chipset_enable.c index 1191a4c..c40e10f 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -643,6 +643,7 @@ straps_names = straps_names_pch89_baytrail; break; case CHIPSET_8_SERIES_LYNX_POINT_LP: + case CHIPSET_9_SERIES_WILDCAT_POINT_LP: straps_names = straps_names_pch8_lp; break; case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet @@ -661,6 +662,7 @@ bbs = (gcs >> 1) & 0x1; break; case CHIPSET_8_SERIES_LYNX_POINT_LP: + case CHIPSET_9_SERIES_WILDCAT_POINT_LP: /* Lynx Point LP uses a single bit for BBS */ bbs = (gcs >> 10) & 0x1; break; @@ -796,6 +798,12 @@ static int enable_flash_pch9(struct pci_dev *dev, const char *name) { return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc); +} + +/* Wildcat Point LP */ +static int enable_flash_pch9_lp(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc); } /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. @@ -1787,13 +1795,13 @@ {0x8086, 0x9c43, NT, "Intel", "Lynx Point LP Premium", enable_flash_pch8_lp}, {0x8086, 0x9c45, NT, "Intel", "Lynx Point LP Mainstream", enable_flash_pch8_lp}, {0x8086, 0x9c47, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp}, - {0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9}, - {0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9}, - {0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium", enable_flash_pch9}, - {0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base", enable_flash_pch9}, - {0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9}, - {0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9}, - {0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9}, + {0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp}, + {0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp}, + {0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium", enable_flash_pch9_lp}, + {0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, + {0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp}, + {0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, + {0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp}, {0x8086, 0x9ccb, NT, "Intel", "Broadwell H", enable_flash_pch9}, {0x8086, 0x9d41, BAD, "Intel", "Sunrise Point (Skylake LP Sample)", NULL}, {0x8086, 0x9d43, BAD, "Intel", "Sunrise Point (Skylake-U Base)", NULL}, diff --git a/ich_descriptors.c b/ich_descriptors.c index 90f70ee..593a375 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -142,7 +142,8 @@ case CHIPSET_8_SERIES_LYNX_POINT: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: - case CHIPSET_9_SERIES_WILDCAT_POINT: { + case CHIPSET_9_SERIES_WILDCAT_POINT: + case CHIPSET_9_SERIES_WILDCAT_POINT_LP: { uint8_t size_enc; if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; diff --git a/programmer.h b/programmer.h index 667f6d4..52ed9a9 100644 --- a/programmer.h +++ b/programmer.h @@ -649,6 +649,7 @@ CHIPSET_8_SERIES_LYNX_POINT_LP, CHIPSET_8_SERIES_WELLSBURG, CHIPSET_9_SERIES_WILDCAT_POINT, + CHIPSET_9_SERIES_WILDCAT_POINT_LP, }; /* ichspi.c */ -- To view, visit https://review.coreboot.org/18883 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: hwaccess: Constify `addr` argument of MMIO read functions
by Nico Huber (Code Review) 17 Mar '17

17 Mar '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18881 ) Change subject: hwaccess: Constify `addr` argument of MMIO read functions ...................................................................... hwaccess: Constify `addr` argument of MMIO read functions Change-Id: I1419241a8332b74103b3921df2c615bdf91346a7 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M hwaccess.c M programmer.h 2 files changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/18881/1 diff --git a/hwaccess.c b/hwaccess.c index 1901ee6..aede7e3 100644 --- a/hwaccess.c +++ b/hwaccess.c @@ -147,22 +147,22 @@ sync_primitive(); } -uint8_t mmio_readb(void *addr) +uint8_t mmio_readb(const void *addr) { - return *(volatile uint8_t *) addr; + return *(volatile const uint8_t *) addr; } -uint16_t mmio_readw(void *addr) +uint16_t mmio_readw(const void *addr) { - return *(volatile uint16_t *) addr; + return *(volatile const uint16_t *) addr; } -uint32_t mmio_readl(void *addr) +uint32_t mmio_readl(const void *addr) { - return *(volatile uint32_t *) addr; + return *(volatile const uint32_t *) addr; } -void mmio_readn(void *addr, uint8_t *buf, size_t len) +void mmio_readn(const void *addr, uint8_t *buf, size_t len) { memcpy(buf, addr, len); return; @@ -183,17 +183,17 @@ mmio_writel(cpu_to_le32(val), addr); } -uint8_t mmio_le_readb(void *addr) +uint8_t mmio_le_readb(const void *addr) { return le_to_cpu8(mmio_readb(addr)); } -uint16_t mmio_le_readw(void *addr) +uint16_t mmio_le_readw(const void *addr) { return le_to_cpu16(mmio_readw(addr)); } -uint32_t mmio_le_readl(void *addr) +uint32_t mmio_le_readl(const void *addr) { return le_to_cpu32(mmio_readl(addr)); } diff --git a/programmer.h b/programmer.h index bd8e98d..667f6d4 100644 --- a/programmer.h +++ b/programmer.h @@ -351,16 +351,16 @@ void mmio_writeb(uint8_t val, void *addr); void mmio_writew(uint16_t val, void *addr); void mmio_writel(uint32_t val, void *addr); -uint8_t mmio_readb(void *addr); -uint16_t mmio_readw(void *addr); -uint32_t mmio_readl(void *addr); -void mmio_readn(void *addr, uint8_t *buf, size_t len); +uint8_t mmio_readb(const void *addr); +uint16_t mmio_readw(const void *addr); +uint32_t mmio_readl(const void *addr); +void mmio_readn(const void *addr, uint8_t *buf, size_t len); void mmio_le_writeb(uint8_t val, void *addr); void mmio_le_writew(uint16_t val, void *addr); void mmio_le_writel(uint32_t val, void *addr); -uint8_t mmio_le_readb(void *addr); -uint16_t mmio_le_readw(void *addr); -uint32_t mmio_le_readl(void *addr); +uint8_t mmio_le_readb(const void *addr); +uint16_t mmio_le_readw(const void *addr); +uint32_t mmio_le_readl(const void *addr); #define pci_mmio_writeb mmio_le_writeb #define pci_mmio_writew mmio_le_writew #define pci_mmio_writel mmio_le_writel -- To view, visit https://review.coreboot.org/18881 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I1419241a8332b74103b3921df2c615bdf91346a7 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: trivial change to test jenkins
by gerrit code review 16 Mar '17

16 Mar '17

>From Patrick Georgi <pgeorgi(a)google.com>: Patrick Georgi has abandoned this change. ( https://review.coreboot.org/18812 ) Change subject: trivial change to test jenkins ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/18812 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: abandon Gerrit-Change-Id: I49e4cca56938b9f945de2ccd2d0a4ec6acdb0a30 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in flashrom[staging]: trivial change to test jenkins
by gerrit code review 16 Mar '17

16 Mar '17

>From Patrick Georgi <pgeorgi(a)google.com>: Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/18812 ) Change subject: trivial change to test jenkins ...................................................................... Patch Set 1: test uhm... 10? -- To view, visit https://review.coreboot.org/18812 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I49e4cca56938b9f945de2ccd2d0a4ec6acdb0a30 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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