Hello Stefan Tauner, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18925
to look at the new patch set (#2).
Change subject: chipset_enable: Add support for Intel Skylake
......................................................................
chipset_enable: Add support for Intel Skylake
All publicly known Skylake / Sunrise Point PCH variants share the same
register interface [1..4]. Although all SPI configuration is now done
through the SPI PCI device 1f.5, we can't probe for it directly since
its PCI vendor and device IDs are usually hidden.
To work around the hidden IDs, we use another PCI accessor that doesn't
rely on the OS seeing the PCI device.
TEST=Compiled with B150 set to NT (instead of BAD) and checked for
sane register readings.
[1] 6th Generation Intel® Core(TM) Processor Families I/O Platform
Datasheet - Volume 1 of 2
Revision 002EN
Document Number 332995
[2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms
Volume 2 of 2
Revision 001EN
Document Number 332996
[3] Intel® 100 Series and Intel® C230 Series Chipset Family Platform
Controller Hub (PCH)
Datasheet - Volume 1 of 2
Revision 004EN
Document Number 332690
[4] Intel® 100 Series Chipset Family Platform Controller Hub (PCH)
Datasheet - Volume 2 of 2
Revision 001EN
Document Number 332691
Change-Id: I000819aff25fbe9764f33df85f040093b82cd948
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M chipset_enable.c
M programmer.h
2 files changed, 91 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/25/18925/2
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I000819aff25fbe9764f33df85f040093b82cd948
Gerrit-PatchSet: 2
Gerrit-Project: flashrom
Gerrit-Branch: staging
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at>
Gerrit-Reviewer: build bot (Jenkins)
David Hendricks has posted comments on this change. ( https://review.coreboot.org/18883 )
Change subject: Handle Intel Wildcat Point *LP* like Lynx Point LP
......................................................................
Patch Set 3: Code-Review+2
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To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: comment
Gerrit-Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c
Gerrit-PatchSet: 3
Gerrit-Project: flashrom
Gerrit-Branch: staging
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: David Hendricks <dhendrix(a)chromium.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-HasComments: No