Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18962
to look at the new patch set (#2).
Change subject: ichspi: Add support for Intel Skylake
......................................................................
ichspi: Add support for Intel Skylake
The Sunrise Point PCH, paired with Skylake, has some minor changes
in the HW sequencing interface:
* Support for more flash regions moved PR* registers
* Only 4KiB erase blocks are supported by the primary erase command
* A second erase command for 64KiB pages was added
* More commands were added for status register access etc.
* A "Dedicated Lock Bits" register was added
No support for the new commands was added.
The SW sequencing interface seems to have moved register location and
is not supported any more officially. It's also untested.
Changes are loosely based on the Skylake support commit in Chromium OS
by Ramya Vijaykumar:
commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1
Author: Ramya Vijaykumar <ramya.vijaykumar(a)intel.com>
flashrom: Add Skylake platform support
Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M ich_descriptors.c
M ich_descriptors.h
M ichspi.c
3 files changed, 221 insertions(+), 86 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/18962/2
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee
Gerrit-PatchSet: 2
Gerrit-Project: flashrom
Gerrit-Branch: staging
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: David Hendricks <dhendrix(a)chromium.org>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at>
Gerrit-Reviewer: build bot (Jenkins)
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18973
to look at the new patch set (#4).
Change subject: ich_descriptors: Update for Intel Skylake
......................................................................
ich_descriptors: Update for Intel Skylake
Interpretation of component clocks changed. Also more regions and more
masters are supported now. The number of regions (NR) is now static per
chipset (10 in the 100 Series case) and not coded into the descriptor
any more.
TEST=Run `ich_descriptors_tool` over a 100 Series dump and checked
that output looks sane. Run `ich_descriptors_tool` over dumps
of five different older systems (1 x Sandy Bridge, 3 x Ivy Bridge,
1 x Haswell). Beside whitespace changes, regions not accounted
by `NR` are not printed any more.
Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M ich_descriptors.c
M ich_descriptors.h
M util/ich_descriptors_tool/ich_descriptors_tool.c
3 files changed, 228 insertions(+), 143 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/18973/4
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To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8
Gerrit-PatchSet: 4
Gerrit-Project: flashrom
Gerrit-Branch: staging
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)