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Hello Thomas Heijligen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/78203?usp=email
to look at the new patch set (#2).
Change subject: doc: Add first version of code of conduct
......................................................................
doc: Add first version of code of conduct
As a starting point, copying coreboot's one in the absence
of our own.
coreboot's CoC exists for some time and is known to work, so
it's a good starting point. We can iterate on this and make
upgrades and amendments that make sense for flashrom community.
Meanwhile we can share code of conduct with coreboot. We
do have the same servers and infrastructure anyway.
Change-Id: Icd82ba79687da3a2698d84f5cbfe824fbab0c426
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
A doc/about_flashrom/code_of_conduct.rst
M doc/about_flashrom/index.rst
M doc/about_flashrom/team.rst
3 files changed, 144 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/03/78203/2
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Gerrit-Change-Id: Icd82ba79687da3a2698d84f5cbfe824fbab0c426
Gerrit-Change-Number: 78203
Gerrit-PatchSet: 2
Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de>
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Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/78203?usp=email )
Change subject: doc: Add code of conduct
......................................................................
doc: Add code of conduct
For now link to coreboot's one, in the absence of our own.
It is always possible to create our own later, if desired,
but meanwhile we can share code of conduct with coreboot. We
do have the same servers and infrastructure anyway.
Change-Id: Icd82ba79687da3a2698d84f5cbfe824fbab0c426
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
A doc/about_flashrom/code_of_conduct.rst
M doc/about_flashrom/index.rst
M doc/about_flashrom/team.rst
3 files changed, 144 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/03/78203/1
diff --git a/doc/about_flashrom/code_of_conduct.rst b/doc/about_flashrom/code_of_conduct.rst
new file mode 100644
index 0000000..da94e29
--- /dev/null
+++ b/doc/about_flashrom/code_of_conduct.rst
@@ -0,0 +1,140 @@
+===============
+Code of Conduct
+===============
+
+This code of conduct outlines our rules and expectations for everybody
+participating in the flashrom community.
+
+flashrom community etiquette
+============================
+
+We have a friendly and productive atmosphere on our mailing lists,
+development / code review tools, real time chat rooms and when we meet in
+person. Our principles evolve around the following:
+
+* It's not the user's fault if something goes wrong.
+* Attempt collaboration before conflict.
+* People who intentionally insult others (users, developers, corporations,
+ other projects, or the flashrom project itself) will be dealt with. See
+ policy below.
+* We are dealing with hardware with lots of undocumented pitfalls. It is quite
+ possible that you did everything right, but flashrom still won't work for you.
+
+Refrain from insulting anyone or the group they belong to. Remember that
+people might be sensitive to other things than you are.
+
+Most of our community members are not native English speakers, thus
+misunderstandings can (and do) happen. Assume that others are friendly
+and may have picked less-than-stellar wording by accident as long as
+you possibly can.
+
+Reporting Issues
+================
+
+If you have a grievance due to conduct in this community, we're sorry
+that you have had a bad experience, and we want to hear about it so
+we can resolve the situation.
+
+Please contact members of our arbitration team (listed below) promptly
+and directly, in person (if available) or by email: They will listen
+to you and react in a timely fashion.
+
+If you feel uncomfortable, please don't wait it out, ask for help,
+so we can work on setting things right.
+
+For transparency there is no alias or private mailing list address for
+you to reach out to, since we want to make sure that you know who will
+and who won't read your message.
+
+However since people might be on travel or otherwise be unavailable
+at times, please reach out to multiple persons at once, especially
+when using email.
+
+The team will treat your messages confidential as far as the law permits.
+For the purpose of knowing what law applies, the list provides the usual
+country of residence of each team member.
+
+Unacceptable Behavior
+=====================
+
+Unacceptable behaviors include: intimidating, harassing, abusive,
+discriminatory, derogatory or demeaning speech or actions by any
+participant in our community online, at all related events and in
+one-on-one communications carried out in the context of community
+business. Community event venues may be shared with members of the public;
+please be respectful to all patrons of these locations.
+
+Examples of behaviors we do not accept in our community:
+
+* harmful or prejudicial verbal or written comments related to gender,
+ sexual orientation, race, religion, disability;
+* inappropriate physical contact, and unwelcome sexual advances;
+* deliberate intimidation, stalking or following;
+* harassing photography or recording;
+* sustained disruption of talks or other events.
+
+Using this code of conduct aggressively against other people in the
+community might also be harassment. Be considerate when enforcing the code
+of conduct and always try to listen to both sides before passing judgment.
+
+Consequences of Unacceptable Behavior
+=====================================
+
+Unacceptable behavior from any community member, including sponsors and
+those with decision-making authority, will not be tolerated.
+
+Anyone asked to stop unacceptable behavior is expected to comply
+immediately.
+
+If a community member engages in unacceptable behavior, the community
+organizers may take any action they deem appropriate, up to and including
+a temporary ban or permanent expulsion from the community without warning
+(and without refund in the case of a paid event).
+
+Community organizers can be members of the arbitration team, or organizers
+of events and online communities.
+
+Addressing Grievances
+=====================
+
+If you feel you have been falsely or unfairly accused of violating this
+Code of Conduct, you should notify the arbitration team with a concise
+description of your grievance.
+
+Legal action
+============
+
+Threatening or starting legal action against the project, sibling
+projects hosted on coreboot.org infrastructure, project or infrastructure
+maintainers leads to an immediate ban from coreboot.org and related
+systems.
+
+The ban can be reconsidered, but it's the default action because the
+people who pour lots of time and money into the projects aren't interested
+in seeing their resources used against them.
+
+Scope
+==========
+
+We expect all community participants (contributors, paid or otherwise;
+sponsors; and other guests) to abide by this Code of Conduct in all
+community venues, online and in-person, as well as in all one-on-one
+communications pertaining to community business.
+
+Contact info
+============
+
+Our arbitration team consists of the following people
+
+* Stefan Reinauer <stefan.reinauer(a)coreboot.org> (USA)
+* Patrick Georgi <patrick(a)coreboot.org> (Germany)
+* Ronald Minnich <rminnich(a)coreboot.org> (USA)
+* Martin Roth <martin(a)coreboot.org> (USA)
+
+License and attribution
+=======================
+
+This Code of Conduct is distributed under
+a `Creative Commons Attribution-ShareAlike
+license <http://creativecommons.org/licenses/by-sa/3.0/>`_. It is based
+on the `Citizen Code of Conduct <https://web.archive.org/web/20200330154000/http://citizencodeofconduct.org/>`_
diff --git a/doc/about_flashrom/index.rst b/doc/about_flashrom/index.rst
index de36fc2..49c9849 100644
--- a/doc/about_flashrom/index.rst
+++ b/doc/about_flashrom/index.rst
@@ -5,3 +5,4 @@
:maxdepth: 1
team
+ code_of_conduct
diff --git a/doc/about_flashrom/team.rst b/doc/about_flashrom/team.rst
index 9d002bb..2c593ec 100644
--- a/doc/about_flashrom/team.rst
+++ b/doc/about_flashrom/team.rst
@@ -6,8 +6,8 @@
All contributors and users who have a Gerrit account can send patches,
add comments to patches and vote +1..-1 on patches.
-All contributors and users are expected to follow Development guidelines,
-Code of Conduct and Friendliness guidelines.
+All contributors and users are expected to follow Development guidelines and
+:doc:`code_of_conduct`.
There are two special groups in Gerrit.
@@ -55,7 +55,7 @@
* From time to time show up in real-time channel(s) and/or dev meetings.
-* Follow the Code of Conduct and Friendliness guidelines, be a good example for others.
+* Follow the :doc:`code_of_conduct`, be a good example for others.
* Bonus point: if you work in a [software] company, educate and help contributors from your company
with upstream culture and dev guidelines.
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Attention is currently required from: Aarya, Alexander Goncharov, Sam McNally.
Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/77747?usp=email )
Change subject: erasure_layout: Fix double invocation of erasers
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
> I still encounter an error. Added comments and logs in the issue tracker.
Thank you! I added one comment to the ticket. If you give me the images I can debug too!
I think these are two different issues. The issue this patch is solving is that every block was erased twice: but the end result was correct, so end user would not notice the issues (and verification works too).
While I think there are two different issues, I would debug yours as well before deciding to submit this one: just in case.
In general, this patch is useful, and also the next one (unit test), I would really want to get it through and have the test running on jenkins.
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/78142?usp=email )
Change subject: flashchips: Test MXIC MX25U25643G wp
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/78142/comment/47607b27_17845925 :
PS2, Line 7: Test MXIC MX25U25643G wp
replace with:
flashchips: Add write-protect support for MXIC MX25U25643G
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Change subject: flashchips: Test MXIC MX25U25643G wp
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
Thank you for the patch! I have one comment, please see below.
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/78142/comment/c1e4167c_14bd3b74 :
PS2, Line 10308: STATUS2
Should this be CONFIG ? TB bit is defined in configuration register (Table 8).
I hope I am not mistaken.
Commit message says you tested WP, could you maybe give a detailed list of WP commands that you tested?
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Change subject: doc: Make Time of Meeting more consistent
......................................................................
Patch Set 1: Code-Review+2
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Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de>
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Gerrit-Attention: Thomas Heijligen <src(a)posteo.de>
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Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/78188?usp=email )
Change subject: doc: Make Time of Meeting more consistent
......................................................................
doc: Make Time of Meeting more consistent
Change-Id: I8b37d2913750946c71908e94fcd3041766f1b59d
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
M doc/contact.rst
1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/78188/1
diff --git a/doc/contact.rst b/doc/contact.rst
index 5bcac3f..57a9390 100644
--- a/doc/contact.rst
+++ b/doc/contact.rst
@@ -111,19 +111,19 @@
also known as
- | Wednesday 13.00-14.00 Pacific Standard Time UTC-8
- | Wednesday 22.00-23.00 Central European Time UTC+1
- | Thursday 8.00-9.00am Australian Eastern Daylight Time UTC+11
+ | Wednesday 13:00-14:00 Pacific Standard Time UTC-8
+ | Wednesday 22:00-23:00 Central European Time UTC+1
+ | Thursday 8:00-9:00 Australian Eastern Daylight Time UTC+11
Between April and September (inclusive)
- **Thursday 6.00-7.00am UTC+0**
+ **Thursday 6:00-7:00 UTC+0**
also known as
- | Wednesday 11pm-midnight Pacific Daylight Time UTC-7
- | Thursday 8.00-9.00am Central European Summer Time UTC+2
- | Thursday 16.00-17.00 Australian Eastern Standard Time UTC+10
+ | Wednesday 23:00-midnight Pacific Daylight Time UTC-7
+ | Thursday 8:00-9:00 Central European Summer Time UTC+2
+ | Thursday 16:00-17:00 Australian Eastern Standard Time UTC+10
The last week of March and 4 weeks of October there are no meetings
This is because daylight saving time changes are happening on different dates in different locations, and setting up meeting time becomes too complicated.
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/78186?usp=email )
Change subject: ichspi: Add support for C740 PCH
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
I only tested a back-ported patch against flashrom v1.21 using the linux_mtd driver.
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Gerrit-Owner: Patrick Rudolph <rudolphpatrick05(a)gmail.com>
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Hello Patrick Rudolph,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/flashrom/+/78186?usp=email
to review the following change.
Change subject: ichspi: Add support for C740 PCH
......................................................................
ichspi: Add support for C740 PCH
Add Intel Emmitsburg detection support.
Change-Id: I80eebc0fcc14de9df823aceaee77870ad136f94a
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M include/programmer.h
4 files changed, 25 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/86/78186/1
diff --git a/chipset_enable.c b/chipset_enable.c
index 3846ecf..8da0e6d 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -601,6 +601,7 @@
break;
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -712,6 +713,7 @@
break;
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_METEOR_LAKE:
boot_straps = boot_straps_pch500;
break;
diff --git a/ich_descriptors.c b/ich_descriptors.c
index a2a99bd..548e6ab 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -44,6 +44,7 @@
case CHIPSET_GEMINI_LAKE:
return 6;
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -75,6 +76,7 @@
{
switch (cs) {
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_600_SERIES_ALDER_POINT:
case CHIPSET_METEOR_LAKE:
@@ -117,9 +119,9 @@
"5 series Ibex Peak", "6 series Cougar Point", "7 series Panther Point",
"8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg",
"9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point",
- "C620 series Lewisburg", "300 series Cannon Point", "400 series Comet Point",
- "500 series Tiger Point", "600 series Alder Point", "Meteor Lake",
- "Apollo Lake", "Gemini Lake", "Jasper Lake", "Elkhart Lake",
+ "C620 series Lewisburg", "C740 series Emmitsburg", "300 series Cannon Point",
+ "400 series Comet Point", "500 series Tiger Point", "600 series Alder Point",
+ "Meteor Lake", "Apollo Lake", "Gemini Lake", "Jasper Lake", "Elkhart Lake",
};
if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names))
cs = 0;
@@ -211,6 +213,7 @@
case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -304,6 +307,7 @@
return freq_str[0][value];
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_JASPER_LAKE:
@@ -357,6 +361,7 @@
switch (cs) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -489,6 +494,7 @@
cs == CHIPSET_400_SERIES_COMET_POINT ||
cs == CHIPSET_500_SERIES_TIGER_POINT ||
cs == CHIPSET_600_SERIES_ALDER_POINT ||
+ cs == CHIPSET_C740_SERIES_EMMITSBURG ||
cs == CHIPSET_JASPER_LAKE || cs == CHIPSET_METEOR_LAKE) {
const char *const master_names[] = {
"BIOS", "ME", "GbE", "unknown", "EC",
@@ -1023,6 +1029,8 @@
}
if (content->ISL <= 80)
return CHIPSET_C620_SERIES_LEWISBURG;
+ if (content->ISL == 0x50)
+ return CHIPSET_C740_SERIES_EMMITSBURG;
warn_peculiar_desc("Ibex Peak");
return CHIPSET_5_SERIES_IBEX_PEAK;
} else if (upper->MDTBA == 0x00) {
@@ -1095,6 +1103,7 @@
break;
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_APOLLO_LAKE:
if (component->modes.freq_read != 6) {
msg_pwarn("\nThe flash descriptor looks like a Skylake/Sunrise Point descriptor.\n"
@@ -1242,6 +1251,7 @@
case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -1287,6 +1297,7 @@
switch (cs) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
diff --git a/ichspi.c b/ichspi.c
index 2e38ff1..d2e0322 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -457,6 +457,7 @@
switch (ich_gen) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -470,6 +471,7 @@
switch (ich_gen) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -492,6 +494,7 @@
switch (ich_gen) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -2050,6 +2053,7 @@
switch (ich_gen) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -2087,6 +2091,7 @@
*num_freg = 10;
break;
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
*num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */
break;
case CHIPSET_300_SERIES_CANNON_POINT:
@@ -2150,6 +2155,7 @@
switch (ich_gen) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -2230,6 +2236,7 @@
case CHIPSET_ICH8:
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -2269,6 +2276,7 @@
case CHIPSET_ICH8:
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
diff --git a/include/programmer.h b/include/programmer.h
index 562f58a..15df0d4 100644
--- a/include/programmer.h
+++ b/include/programmer.h
@@ -354,6 +354,7 @@
CHIPSET_9_SERIES_WILDCAT_POINT_LP,
CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */
CHIPSET_C620_SERIES_LEWISBURG,
+ CHIPSET_C740_SERIES_EMMITSBURG,
CHIPSET_300_SERIES_CANNON_POINT,
CHIPSET_400_SERIES_COMET_POINT,
CHIPSET_500_SERIES_TIGER_POINT,
--
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Gerrit-Project: flashrom
Gerrit-Branch: main
Gerrit-Change-Id: I80eebc0fcc14de9df823aceaee77870ad136f94a
Gerrit-Change-Number: 78186
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <rudolphpatrick05(a)gmail.com>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newchange