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Change subject: flashchips: Add GD25Q128E name to the GD25Q127C/GD25Q128C entry
......................................................................
Patch Set 2:
(5 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/78348/comment/3734bd01_fb32eaa1 :
PS1, Line 9: Q128E and Q127C/Q128C have compatible main functions, their differences
: are
> Do you have a link to datasheet? Thank you!
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-0… (added to the comment)
https://review.coreboot.org/c/flashrom/+/78348/comment/7340a796_43437544 :
PS1, Line 31: flashrom_tester with flashrom binary could pass with Q128E
> Which specifically flashrom commands did that run? Probe/read/write/erase/write-protect ?
Yes, all of them are tested. Updated.
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/78348/comment/eb066b2c_3f4f3b96 :
PS1, Line 6802: /* FIXME: 128E's OTP: 3072B total and doesn't support QPI */
> QPI part of this might be an issue. […]
I have two questions about these:
1. According to the [GD25Q128C datasheet](https://www.endrich.com/sixcms/media.php/2/GD25Q128C-Rev2.pdf) page 8, GD25Q128C has QPI, [GD25Q127C datasheet](https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00220-GD25Q127C-Rev2.3.pdf) page 4, GD25Q127C doesn't has QPI. So the best solution might be: separate to "GD25Q128C" and "GD25Q127C/GD25Q128E" instead?
(And I think there was already some discussion about it: https://review.coreboot.org/c/flashrom/+/52883/2/flashchips.c#6274)
2. Could you help me understand what will happen if there are 3 different chip entries? Will we always get the very first match with `flashrom --flash-name`?
https://review.coreboot.org/c/flashrom/+/78348/comment/f2cad5c8_c6f3c61d :
PS1, Line 6833: .reg_bits =
: {
: .srp = {STATUS1, 7, RW},
: .srl = {STATUS2, 0, RW},
: .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
: .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */
: .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */
: .cmp = {STATUS2, 6, RW},
: }
> Are all these registers the same for new chip you are adding
Yes, they are exactly the same, based on the datasheet.
> and have you tested write-protect operations? (current chip definition marks write-protect as tested).
Yes, we've tested.
File include/flashchips.h:
https://review.coreboot.org/c/flashrom/+/78348/comment/09fd21c0_3e337dc0 :
PS1, Line 393: Same as GD25Q128B, GD25B128B, GD25Q127C, and GD25Q128E, can be distinguished by SFDP
> With this patch, the same model id GIGADEVICE_GD25Q128 will be used for 5 different chips, used to b […]
Done
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Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/78348?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: flashchips: Add GD25Q128E name to the GD25Q127C/GD25Q128C entry
......................................................................
flashchips: Add GD25Q128E name to the GD25Q127C/GD25Q128C entry
Datasheet for Q128E: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-0…
Q128E and Q127C/Q128C have compatible main functions, their differences
are:
* Q128E uses 55 nm process, while Q127C/Q128C use 65nm
* Q128E does not support QPI
* Q128E have OTP: 3072B, while Q127C/Q128C are 1536B
* Q128E's fast read clock frequency is 133MHz, while Q127C/Q128C are
104MHZ
We also tested that Q128E could pass flashrom_tester while probing it as
127C/128C, so the main functionalities are compatible.
Change the chip name from GD25Q127C/GD25Q128C to
GD25Q127C/GD25Q128C/GD25Q128E to make it more accurate.
Chip revision history:
- The 'GD25Q127C/GD25Q128C' definition was added in
`commit e0c7abf219b81ad049d09a4671ebc9196153d308` as 'GD25Q128C' and
later renamed to 'GD25Q127C/GD25Q128C'
BUG=b:304863141, b:293545382
BRANCH=none
TEST=flashrom_tester with flashrom binary could pass with Q128E,
which contains probe, read, write, erase, and write protect
Signed-off-by: Hsuan Ting Chen <roccochen(a)google.com>
Change-Id: I3300671b1cf74b3ea0469b9c5a833489ab4914f5
---
M flashchips.c
M include/flashchips.h
2 files changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/48/78348/2
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Change subject: flashchips: Add GD25Q128E name to the GD25Q127C/GD25Q128C entry
......................................................................
Abandoned
Duplicate of 78348
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Change subject: flashchips: Add GD25Q128E name to the GD25Q127C/GD25Q128C entry
......................................................................
flashchips: Add GD25Q128E name to the GD25Q127C/GD25Q128C entry
Datasheet for Q128E: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-0…
Q128E and Q127C/Q128C have compatible main functions, their differences
are:
* Q128E uses 55 nm process, while Q127C/Q128C use 65nm
* Q128E does not support QPI
* Q128E have OTP: 3072B, while Q127C/Q128C are 1536B
* Q128E's fast read clock frequency is 133MHz, while Q127C/Q128C are
104MHZ
We also tested that Q128E could pass flashrom_tester while probing it as
127C/128C, so the main functionalities are compatible.
Change the chip name from GD25Q127C/GD25Q128C to
GD25Q127C/GD25Q128C/GD25Q128E to make it more accurate.
Chip revision history:
- The 'GD25Q127C/GD25Q128C' definition was added in
`commit e0c7abf219b81ad049d09a4671ebc9196153d308` as 'GD25Q128C' and
later renamed to 'GD25Q127C/GD25Q128C'
BUG=b:304863141, b:293545382
BRANCH=none
TEST=flashrom_tester with flashrom binary could pass with Q128E,
which contains probe, read, write, erase, and write protect
Signed-off-by: Hsuan Ting Chen <roccochen(a)google.com>
Change-Id: I5ab797bfa8f08e54cb29ed2d82eeef6604ac944d
---
M flashchips.c
M include/flashchips.h
2 files changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/05/78505/1
diff --git a/flashchips.c b/flashchips.c
index e156ffb..3b73ba9 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -6792,13 +6792,14 @@
{
.vendor = "GigaDevice",
- .name = "GD25Q127C/GD25Q128C",
+ .name = "GD25Q127C/GD25Q128C/GD25Q128E",
.bustype = BUS_SPI,
.manufacture_id = GIGADEVICE_ID,
.model_id = GIGADEVICE_GD25Q128,
.total_size = 16384,
.page_size = 256,
/* OTP: 1536B total; read 0x48; write 0x42, erase 0x44 */
+ /* FIXME: 128E's OTP: 3072B total and doesn't support QPI */
/* QPI: enable 0x38, disable 0xFF */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2,
.tested = TEST_OK_PREWB,
diff --git a/include/flashchips.h b/include/flashchips.h
index 962e65e..fa518c1 100644
--- a/include/flashchips.h
+++ b/include/flashchips.h
@@ -390,7 +390,7 @@
#define GIGADEVICE_GD25Q16 0x4015 /* Same as GD25Q16B (which has OTP) */
#define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */
#define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */
-#define GIGADEVICE_GD25Q128 0x4018 /* GD25Q128B and GD25Q128C only, can be distinguished by SFDP */
+#define GIGADEVICE_GD25Q128 0x4018 /* Same as GD25Q128B, GD25Q127C, GD25Q128C, and GD25Q128E, can be distinguished by SFDP */
#define GIGADEVICE_GD25Q256D 0x4019
#define GIGADEVICE_GD25VQ21B 0x4212
#define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/78186?usp=email )
Change subject: ichspi: Add support for C740 PCH
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/78186/comment/b5ea4a51_c1932956 :
PS4, Line 490: to be compatible with 500 Series PCH below
> Updated to code to make it more clear that nm=5 should be used and why it should be used.
Done
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Change subject: flashchips: Add support for PUYA P25Q40H
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Hello! My apologies, life came in the way the last few months. […]
Okay no worries! You can get back when you can.
I finished the other patch, CB:58134 and once it is merged it would be an example of adding Puya chip. And you won't need to add Puya id (it's added in the other patch).
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Change subject: flashchips: Add Puya P25Q21H/11H/06H
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
WereCatf, sorry that the patch was hanging for so long. You fixed all the comments long time ago!
I did a rebase because since end of last year we replaced function pointers with enums, and I think it's a bit unfair to place this change on you (the patch should have been merged earlier).
Thank you for contributing.
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Change subject: ichspi: Add support for C740 PCH
......................................................................
Patch Set 5:
(1 comment)
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/78186/comment/ff8b1ecd_ed783899 :
PS4, Line 490: to be compatible with 500 Series PCH below
> I really like your explanation, I understand now after reading it! Do you think you can put it into […]
Updated to code to make it more clear that nm=5 should be used and why it should be used.
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Hello Anastasia Klimchuk, David Hendricks, Patrick Georgi, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Code-Review+1 by David Hendricks, Verified-1 by build bot (Jenkins)
Change subject: ichspi: Add support for C740 PCH
......................................................................
ichspi: Add support for C740 PCH
Clean commit 51e1d0e4b7670e5822560acc724a6a8dd00b6af4
'Add support for Intel Emmitsburg PCH' which broke
CHIPSET_5_SERIES_IBEX_PEAK detection and which assumes C740 is the same
as C620, while its more a close relative to Intel's H570 PCH.
Based on Intel SPI Programming Guide #619386.
Test: Run on Intel ArcherCity CRB with Intel's C741 PCH
using the 'internal' programmer.
Test: Run on BMC and accessed the SPI flash chip over
'linux_mtd' programmer.
Change-Id: I80eebc0fcc14de9df823aceaee77870ad136f94a
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M include/programmer.h
4 files changed, 46 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/86/78186/5
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