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Hello Patrick Rudolph,
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Please visit
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to review the following change.
Change subject: ich_descriptors: Fix debug print
......................................................................
ich_descriptors: Fix debug print
Allow up nm to be qqual to ARRAY_SIZE(master_names).
The loop below makes sure that it doesn't access master_names
out of bounds.
Change-Id: Ib9276a6c29952487db6e60fb583942c0f24cd6ef
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M ich_descriptors.c
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/00/78300/1
diff --git a/ich_descriptors.c b/ich_descriptors.c
index a2a99bd..4b440ed 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -493,9 +493,9 @@
const char *const master_names[] = {
"BIOS", "ME", "GbE", "unknown", "EC",
};
- if (nm >= (ssize_t)ARRAY_SIZE(master_names)) {
- msg_pdbg2("%s: number of masters too high (%d).\n", __func__,
- desc->content.NM + 1);
+
+ if (nm > (ssize_t)ARRAY_SIZE(master_names)) {
+ msg_pdbg2("%s: number of masters too high (%zd).\n", __func__, nm);
return;
}
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Gerrit-Change-Number: 78300
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Hello Patrick Georgi, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/78186?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Code-Review+1 by Patrick Georgi, Verified+1 by build bot (Jenkins)
Change subject: ichspi: Add support for C740 PCH
......................................................................
ichspi: Add support for C740 PCH
Clean commit 51e1d0e4b7670e5822560acc724a6a8dd00b6af4
'Add support for Intel Emmitsburg PCH' which broke
CHIPSET_5_SERIES_IBEX_PEAK detection and which assumes C740 is the same
as C620, while its more a close relative to Intel's H570 PCH.
Based on Intel SPI Programming Guide #619386.
Test: Run on Intel ArcherCity CRB with Intel's C741 PCH
using the 'internal' programmer.
Test: Run on BMC and accessed the SPI flash chip over
'linux_mtd' programmer.
Change-Id: I80eebc0fcc14de9df823aceaee77870ad136f94a
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M include/programmer.h
4 files changed, 43 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/86/78186/2
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Jes Klinke has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/77999?usp=email )
Change subject: raiden: Support target index with generic REQ_ENABLE
......................................................................
Patch Set 2:
(3 comments)
Patchset:
PS2:
I will address the smaller comments, once we have settled on the way ahead wrt. the meaning of `request_enable` and the `get_target()` signature.
File raiden_debug_spi.c:
https://review.coreboot.org/c/flashrom/+/77999/comment/8065aaee_1d660c98 :
PS2, Line 1596: request_enable & 0xFF
> Does this still work for target values EC and AP ?
See below. Yes, the EC and AP values fit inside 8 bits. (The bRequest parameter here is `uint8_t`, so the `& 0xFF` is actually a no-op included for clarity, as with my change `request_enable` can for the first time be non-zero in the second byte.)
https://review.coreboot.org/c/flashrom/+/77999/comment/9cdbcfbd_03d2d743 :
PS2, Line 1596: request_enable & 0xFF,
: (request_enable >> 8) & 0xFF,
> A question: why do you initialise `request_enable` to a value that you never use by itself, just as […]
It was already the case that some Raiden devices had multiple SPI ports, or at least knew multiple ways of controlling electrical mux'es or buffers. These SPI ports would be known as "ap" or "ec", and particular values of bRequest was used to access one or the other.
I have been developing firmware for another debugger using the Raiden protocol, which has three or more SPI ports, and they do not have any particular names, just numbers. I have extended the Raiden protocol such that the lower byte of `wValue` can indicate which one of such an array of similar SPI ports to use (while bRequest is set to the "default" value), and the goal of this CL is to be able to access that functionality.
The `int get_target()` method used to return a 8-bit value to be passed in the `bRequest` field of the control request to "open" the SPI port (while the wValue field was always set to zero). In a somewhat hacky way, I used the upper bits of the return value from `get_target()` to convey the desired value of wValue. Perhaps I should instead change the signature into
`void get_target(const struct programmer_cfg *cfg, uint8_t *request_enable, uint16_t *request_parameter)`
such that the function can "return" two separate values.
Let me know if you prefer that, and I can modify my CL.
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Change subject: ichspi: Add support for C740 PCH
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
Besides the issue Kyösti pointed out, this looks reasonable.
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Change subject: ichspi: Add support for C740 PCH
......................................................................
Patch Set 1:
(1 comment)
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/78186/comment/9a7a6b03_62046655 :
PS1, Line 1032: if (content->ISL == 0x50)
That's 80 in decimal and is hit with <= 80 above?
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Change subject: flashchips: Add write-protect support for MXIC MX25U25643G
......................................................................
Patch Set 5: Code-Review+2
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Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, Thomas Heijligen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: flashchips: Add write-protect support for MXIC MX25U25643G
......................................................................
flashchips: Add write-protect support for MXIC MX25U25643G
The MX25U25643G has a WPSEL bit in the security register, but the MX25U25635F does not.
Therefore, take them apart.
We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.
The MX25U25643G has been tested by ch341a programmer : read, write,
erase and wp.
MX25U25643G datasheet is available at the following URL:
https://www.mxic.com.tw/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/spe…
MX25U25635F datasheet is available at the following URL:
https://www.macronix.com/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/sp…
Change-Id: I43de9ed123b9736c04d070754bcf9c32be5697ad
Signed-off-by: rogeryou <rogeryou(a)mxic.com.cn>
---
M flashchips.c
1 file changed, 58 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/42/78142/5
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Change subject: flashchips: Add write-protect support for MXIC MX25U25643G
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/78142/comment/ca23a22a_b57abdb6 :
PS2, Line 7: Test MXIC MX25U25643G wp
> replace with: […]
Done
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/78142/comment/dfaed97e_940a231b :
PS2, Line 10308: STATUS2
> Should this be CONFIG ? TB bit is defined in configuration register (Table 8). […]
Done
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Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, Thomas Heijligen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/78142?usp=email
to look at the new patch set (#4).
Change subject: flashchips: Add write-protect support for MXIC MX25U25643G
......................................................................
flashchips: Add write-protect support for MXIC MX25U25643G
The MX25U25643G has a WPSEL bit in the security register, but the MX25U25635F does not.
Therefore, take them apart.
The MX25U25643G has been tested by ch341a programmer : read, write, erase and wp.
The MX25U25643G has been tested by ch341a programmer : read, write,
erase and wp.
MX25U25643G datasheet is available at the following URL:
https://www.mxic.com.tw/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/spe…
MX25U25635F datasheet is available at the following URL:
https://www.macronix.com/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/sp…
Change-Id: I43de9ed123b9736c04d070754bcf9c32be5697ad
Signed-off-by: rogeryou <rogeryou(a)mxic.com.cn>
---
M flashchips.c
1 file changed, 58 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/42/78142/4
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Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/78142?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: flashchips: Add write-protect support for MXIC MX25U25643G
......................................................................
flashchips: Add write-protect support for MXIC MX25U25643G
The MX25U25643G has a WPSEL bit in the security register, but the MX25U25635F does not.
Therefore, take them apart.
The MX25U25643G has been tested by ch341a programmer : read, write, erase and wp.
We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.
MX25U25643G datasheet is available at the following URL:
https://www.mxic.com.tw/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/spe…
MX25U25635F datasheet is available at the following URL:
https://www.macronix.com/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/sp…
Change-Id: I43de9ed123b9736c04d070754bcf9c32be5697ad
Signed-off-by: rogeryou <rogeryou(a)mxic.com.cn>
---
M doc/contact.rst
M doc/dev_guide/development_guide.rst
M doc/index.rst
A doc/release_notes/index.rst
A doc/release_notes/v_1_3.rst
A doc/user_docs/example_partial_wp.rst
A doc/user_docs/fw_updates_vs_spi_wp.rst
A doc/user_docs/index.rst
M flashchips.c
9 files changed, 599 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/42/78142/3
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