May 2022 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: Global cleanup: Fix a few spelling errors
by Anastasia Klimchuk (Code Review) 03 May '22

03 May '22

Attention is currently required from: Martin L Roth, Edward O'Callaghan. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62840 ) Change subject: Global cleanup: Fix a few spelling errors ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/62840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4e3b277f220fa70dcab21912c30f1d26d9bd8749 Gerrit-Change-Number: 62840 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Tue, 03 May 2022 05:14:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: ichspi: Introduce HSFC CYCLE READ/WRITE/ERASE macros
by Anastasia Klimchuk (Code Review) 03 May '22

03 May '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62868 ) Change subject: ichspi: Introduce HSFC CYCLE READ/WRITE/ERASE macros ...................................................................... ichspi: Introduce HSFC CYCLE READ/WRITE/ERASE macros This patch introduces useful macros (read/write/erase) and uses these macros throughout the SPI operations. Additionally, implicitly using the HSFC_CYCLE_READ macro for the SPI read operation. BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Additionally, no difference in flashrom binary seen while comparing flashrom binary generated with CB:62888 and between CB:62888 to CB:62868 below: flashrom$ cmp flashrom flashrom_old <<none>> Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3ea74b668e5f8d8e4b3da2a8ad8b81f1813e1e80 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62868 Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M ichspi.c 1 file changed, 6 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/ichspi.c b/ichspi.c index ab3a350..667b18f 100644 --- a/ichspi.c +++ b/ichspi.c @@ -128,6 +128,9 @@ #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ #define HSFC_FCYCLE_MASK(n) ((n) << HSFC_FCYCLE_OFF) #define HSFC_FCYCLE HSFC_FCYCLE_MASK(ICH9_HSFC_FCYCLE_BIT_WIDTH) +#define HSFC_CYCLE_READ HSFC_FCYCLE_MASK(0) +#define HSFC_CYCLE_WRITE HSFC_FCYCLE_MASK(2) +#define HSFC_CYCLE_BLOCK_ERASE HSFC_FCYCLE_MASK(3) /* 3-7: reserved */ #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) @@ -1430,7 +1433,7 @@ hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */ - hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_CYCLE_BLOCK_ERASE; /* set erase operation */ hsfc |= HSFC_FGO; /* start */ msg_pdbg("HSFC used for block erasing: "); prettyprint_ich9_reg_hsfc(hsfc, ich_generation); @@ -1473,6 +1476,7 @@ hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~hwseq_data.hsfc_fcycle; /* set read operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ + hsfc |= HSFC_CYCLE_READ; /* set read operation */ /* set byte count */ hsfc |= HSFC_FDBC_VAL(block_len - 1); hsfc |= HSFC_FGO; /* start */ @@ -1518,7 +1522,7 @@ hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */ - hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc |= HSFC_CYCLE_WRITE; /* set write operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ hsfc |= HSFC_FDBC_VAL(block_len - 1); -- To view, visit https://review.coreboot.org/c/flashrom/+/62868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3ea74b668e5f8d8e4b3da2a8ad8b81f1813e1e80 Gerrit-Change-Number: 62868 Gerrit-PatchSet: 20 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-MessageType: merged

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Change in flashrom[master]: ichspi: Introduce HSFC_FDBC_VAL(n) macro
by Anastasia Klimchuk (Code Review) 03 May '22

03 May '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62892 ) Change subject: ichspi: Introduce HSFC_FDBC_VAL(n) macro ...................................................................... ichspi: Introduce HSFC_FDBC_VAL(n) macro This patch introduces HSFC_FDBC_VAL(n) macro to use in SPI read and write operations. BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie2512c85de9fc21286234b97f5842ecef1729787 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62892 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M ichspi.c 1 file changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/ichspi.c b/ichspi.c index ca72088..ab3a350 100644 --- a/ichspi.c +++ b/ichspi.c @@ -131,6 +131,7 @@ /* 3-7: reserved */ #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) +#define HSFC_FDBC_VAL(n) (((n) << HSFC_FDBC_OFF) & HSFC_FDBC) /* 14: reserved */ #define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */ #define HSFC_SME (0x1 << HSFC_SME_OFF) @@ -1473,7 +1474,7 @@ hsfc &= ~hwseq_data.hsfc_fcycle; /* set read operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ - hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FDBC_VAL(block_len - 1); hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); @@ -1520,7 +1521,7 @@ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ - hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FDBC_VAL(block_len - 1); hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); -- To view, visit https://review.coreboot.org/c/flashrom/+/62892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie2512c85de9fc21286234b97f5842ecef1729787 Gerrit-Change-Number: 62892 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: ichspi: Introduce HSFC_FCYCLE_MASK(n) macro
by Anastasia Klimchuk (Code Review) 03 May '22

03 May '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62891 ) Change subject: ichspi: Introduce HSFC_FCYCLE_MASK(n) macro ...................................................................... ichspi: Introduce HSFC_FCYCLE_MASK(n) macro This patch introduces HSFC_FCYCLE_MASK(n) macro to cover both ICH and PCH hardware sequencing FCYCLE Bit width. BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Id222304165610c7ae48e365d72ec8fdeea51c51d Reviewed-on: https://review.coreboot.org/c/flashrom/+/62891 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M ichspi.c 1 file changed, 21 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/ichspi.c b/ichspi.c index f8936ed..ca72088 100644 --- a/ichspi.c +++ b/ichspi.c @@ -46,8 +46,19 @@ */ /* Changed HSFC Control bits */ +/* + * 4 bits to represents the FCYCLE operation for PCH as: + * 0: SPI Read + * 2: SPI Write + * 3: SPI Erase 4K + * 4: SPI Erase 64K + * 6: SPI RDID + * 7: SPI Write Status + * 8: SPI Read Status + */ +#define PCH100_HSFC_FCYCLE_BIT_WIDTH 0xf #define PCH100_HSFC_FCYCLE_OFF (17 - 16) /* 1-4: FLASH Cycle */ -#define PCH100_HSFC_FCYCLE (0xf << PCH100_HSFC_FCYCLE_OFF) +#define PCH100_HSFC_FCYCLE HSFC_FCYCLE_MASK(PCH100_HSFC_FCYCLE_BIT_WIDTH) /* New HSFC Control bit */ #define PCH100_HSFC_WET_OFF (21 - 16) /* 5: Write Enable Type */ #define PCH100_HSFC_WET (0x1 << PCH100_HSFC_WET_OFF) @@ -107,8 +118,16 @@ #define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */ #define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */ #define HSFC_FGO (0x1 << HSFC_FGO_OFF) +/* + * 2 bits to represents the FCYCLE operation for ICH9 as: + * 0: SPI Read + * 2: SPI Write + * 3: SPI Block Erase + */ +#define ICH9_HSFC_FCYCLE_BIT_WIDTH 3 #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ -#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) +#define HSFC_FCYCLE_MASK(n) ((n) << HSFC_FCYCLE_OFF) +#define HSFC_FCYCLE HSFC_FCYCLE_MASK(ICH9_HSFC_FCYCLE_BIT_WIDTH) /* 3-7: reserved */ #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) -- To view, visit https://review.coreboot.org/c/flashrom/+/62891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id222304165610c7ae48e365d72ec8fdeea51c51d Gerrit-Change-Number: 62891 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-MessageType: merged

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Change in flashrom[master]: ichspi: Drop unused `_pprint_reg` macro
by Anastasia Klimchuk (Code Review) 03 May '22

03 May '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/63549 ) Change subject: ichspi: Drop unused `_pprint_reg` macro ...................................................................... ichspi: Drop unused `_pprint_reg` macro This patch drops `_pprint_reg` macro as `pprint_reg` macro is now able to call into msg_pdbg(). BUG=b:223630977 TEST=Able to display HSFS register offset properly as below BIOS_CNTL = 0x8b: BIOS Lock Enable: enabled, BIOS Write Enable: enabled Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed. New value is 0x8b. SPIBAR = 0x00007fce5a270000 (phys = 0xfe010000) 0x04: 0xf000 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=0, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Iee7a23447de38423b61008b3242d28ce553ae0a2 Reviewed-on: https://review.coreboot.org/c/flashrom/+/63549 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M ichspi.c 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved diff --git a/ichspi.c b/ichspi.c index 999249d..f8936ed 100644 --- a/ichspi.c +++ b/ichspi.c @@ -412,8 +412,7 @@ ops->preop[1]); } -#define _pprint_reg(bit, mask, off, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & mask) >> off) -#define pprint_reg(reg, bit, val, sep) _pprint_reg(bit, reg##_##bit, reg##_##bit##_OFF, val, sep) +#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit) >> reg##_##bit##_OFF) static void prettyprint_ich9_reg_hsfs(uint16_t reg_val, enum ich_chipset ich_gen) { -- To view, visit https://review.coreboot.org/c/flashrom/+/63549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iee7a23447de38423b61008b3242d28ce553ae0a2 Gerrit-Change-Number: 63549 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: ichspi: Use `pprint_reg` macro for PCH100 HSFC FCYCLE offset
by Anastasia Klimchuk (Code Review) 03 May '22

03 May '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/63470 ) Change subject: ichspi: Use `pprint_reg` macro for PCH100 HSFC FCYCLE offset ...................................................................... ichspi: Use `pprint_reg` macro for PCH100 HSFC FCYCLE offset This patch uses `pprint_reg` macro instead `_pprint_reg` with explicit register name and offset macros being passed as argument. BUG=b:223630977 TEST=Able to display PCH100_HSFC.FCYCLE offset properly. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I5a8d84639b7226bf82458a7310f306c5232cffe3 Reviewed-on: https://review.coreboot.org/c/flashrom/+/63470 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M ichspi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Arthur Heymans: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved diff --git a/ichspi.c b/ichspi.c index 36ee3b9..999249d 100644 --- a/ichspi.c +++ b/ichspi.c @@ -463,7 +463,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_ELKHART_LAKE: - _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", "); + pprint_reg(PCH100_HSFC, FCYCLE, reg_val, ", "); pprint_reg(PCH100_HSFC, WET, reg_val, ", "); break; default: -- To view, visit https://review.coreboot.org/c/flashrom/+/63470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5a8d84639b7226bf82458a7310f306c5232cffe3 Gerrit-Change-Number: 63470 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macros
by Anastasia Klimchuk (Code Review) 03 May '22

03 May '22

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62888 ) Change subject: ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macros ...................................................................... ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macros This patch renames the `WET` macro definitions based on its availability with PCH100 onwards chipset. HSFC_WET_OFF -> PCH100_HSFC_WET_OFF HSFC_WET -> PCH100_HSFC_WET BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f Reviewed-on: https://review.coreboot.org/c/flashrom/+/62888 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M ichspi.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Arthur Heymans: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved diff --git a/ichspi.c b/ichspi.c index 5d4d4d7..36ee3b9 100644 --- a/ichspi.c +++ b/ichspi.c @@ -49,8 +49,8 @@ #define PCH100_HSFC_FCYCLE_OFF (17 - 16) /* 1-4: FLASH Cycle */ #define PCH100_HSFC_FCYCLE (0xf << PCH100_HSFC_FCYCLE_OFF) /* New HSFC Control bit */ -#define HSFC_WET_OFF (21 - 16) /* 5: Write Enable Type */ -#define HSFC_WET (0x1 << HSFC_WET_OFF) +#define PCH100_HSFC_WET_OFF (21 - 16) /* 5: Write Enable Type */ +#define PCH100_HSFC_WET (0x1 << PCH100_HSFC_WET_OFF) #define PCH100_FADDR_FLA 0x07ffffff @@ -464,7 +464,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_ELKHART_LAKE: _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", "); - pprint_reg(HSFC, WET, reg_val, ", "); + pprint_reg(PCH100_HSFC, WET, reg_val, ", "); break; default: pprint_reg(HSFC, FCYCLE, reg_val, ", "); -- To view, visit https://review.coreboot.org/c/flashrom/+/62888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f Gerrit-Change-Number: 62888 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: flashrom.8.tmpl: Add raiden_debug_spi doc entry
by Anastasia Klimchuk (Code Review) 03 May '22

03 May '22

Attention is currently required from: Felix Singer, Nico Huber, Martin L Roth, Edward O'Callaghan, Nikolai Artemiev. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62768 ) Change subject: flashrom.8.tmpl: Add raiden_debug_spi doc entry ...................................................................... Patch Set 8: Code-Review+2 (1 comment) File flashrom.8.tmpl: https://review.coreboot.org/c/flashrom/+/62768/comment/4a6e3918_acdb4164 PS8, Line 1182: terminates at the end-point > It is undocumented behavior. […] Okay I got it thank you for explanation! -- To view, visit https://review.coreboot.org/c/flashrom/+/62768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I186920006bdfcc7a9f89542f84b452dfc72b18e4 Gerrit-Change-Number: 62768 Gerrit-PatchSet: 8 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Tue, 03 May 2022 02:28:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: flashrom.8.tmpl: Add raiden_debug_spi doc entry
by Edward O'Callaghan (Code Review) 03 May '22

03 May '22

Attention is currently required from: Felix Singer, Nico Huber, Martin L Roth, Anastasia Klimchuk, Nikolai Artemiev. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62768 ) Change subject: flashrom.8.tmpl: Add raiden_debug_spi doc entry ...................................................................... Patch Set 8: (1 comment) File flashrom.8.tmpl: https://review.coreboot.org/c/flashrom/+/62768/comment/c0d3fcef_e53a4496 PS8, Line 1182: terminates at the end-point > I have one question: does this mean unspecified target […] It is undocumented behavior. Some servo configurations may auto pick AP, sometimes just fail, previous state seems to impact it so ultimately the termination at the USB end-point is undefined from the looks of things. This is why on line 1170 I said "must be specified". Unfortunately there is some scripts that exist that relies on this non-explicit undocumented behavior so we cannot change the code to hard fail when "target" is unspecified so easily. Therefore we document here what is known and how it *should* be used. -- To view, visit https://review.coreboot.org/c/flashrom/+/62768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I186920006bdfcc7a9f89542f84b452dfc72b18e4 Gerrit-Change-Number: 62768 Gerrit-PatchSet: 8 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Tue, 03 May 2022 02:20:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: flashrom.8.tmpl: Add raiden_debug_spi doc entry
by Anastasia Klimchuk (Code Review) 03 May '22

03 May '22

Attention is currently required from: Felix Singer, Nico Huber, Martin L Roth, Edward O'Callaghan, Nikolai Artemiev. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62768 ) Change subject: flashrom.8.tmpl: Add raiden_debug_spi doc entry ...................................................................... Patch Set 8: Code-Review+1 (2 comments) Patchset: PS8: I went through all the comments, they look resolved, but let's see whether other people agree? From myself, only one comment. Thank you! File flashrom.8.tmpl: https://review.coreboot.org/c/flashrom/+/62768/comment/4f086a2a_e1d896e7 PS8, Line 1182: terminates at the end-point I have one question: does this mean unspecified target does nothing returns success or does nothing returns failure ? Thanks! -- To view, visit https://review.coreboot.org/c/flashrom/+/62768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I186920006bdfcc7a9f89542f84b452dfc72b18e4 Gerrit-Change-Number: 62768 Gerrit-PatchSet: 8 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Tue, 03 May 2022 02:07:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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