Attention is currently required from: Nico Huber, Thomas Heijligen.
Hello Nico Huber, Thomas Heijligen,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/flashrom/+/64424
to review the following change.
Change subject: flashchips.c: Drop incorrect `FEATURE_4BA_ENTER_EAR7` uses
......................................................................
flashchips.c: Drop incorrect `FEATURE_4BA_ENTER_EAR7` uses
Using `FEATURE_4BA_ENTER_EAR7` along with `FEATURE_4BA` does not make
sense, as `FEATURE_4BA` implies `FEATURE_4BA_ENTER` and the `spi25.c`
function `spi_enter_exit_4ba()` only handles `FEATURE_4BA_ENTER_EAR7`
if `FEATURE_4BA_ENTER` is not set.
Besides, the datasheet for the two affected chips says the following:
Note: The EN4B instruction will set the Bit 7 (EXTADD) of the
volatile Bank Address Register to "1", but will not change
the non-volatile Bank Address Register.
This means the chip itself will set the bit that flashrom would set to
enable 4BA mode when `FEATURE_4BA_ENTER_EAR7` is effective. This seems
to be some sort of backwards compatibility behavior with software that
uses the EXTADD bit to know whether the flash chip is in 4BA mode.
Change-Id: I5510bab25dbb04c12ef8d6bd3fcb6faa51d6a1e8
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M flashchips.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/24/64424/1
diff --git a/flashchips.c b/flashchips.c
index d155b24..dfa717b 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -7470,7 +7470,7 @@
/* supports SFDP */
/* OTP: 1024B total; read 0x68; write 0x62, erase 0x64, read ID 0x4B */
/* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_4BA_ENTER_EAR7,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA,
.tested = TEST_OK_PREW,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
@@ -7646,7 +7646,7 @@
/* supports SFDP */
/* OTP: 1024B total; read 0x68; write 0x62, erase 0x64, read ID 0x4B */
/* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_4BA_ENTER_EAR7,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA,
.tested = TEST_OK_PREW,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
--
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64384 )
Change subject: meson: use files() for srcs list
......................................................................
Patch Set 1: Code-Review+2
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Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64405 )
Change subject: Add W25Q512NW-IM ID to flashrom
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/64405/comment/77b26b18_5a50d549
PS1, Line 7: Add W25Q512NW-IM ID to flashrom
nit: `flashchips: Add W25Q512NW-IM`
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64405 )
Change subject: Add W25Q512NW-IM ID to flashrom
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/64405/comment/a2ebecd2_b078c987
PS1, Line 15: C
Original-
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64374 )
Change subject: flashrom.c: wrap chip->write() with a helper
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I agree
100% I forgot to add WIP/Private label to this with the other ones on top. Sorry for the noise.
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Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/64373 )
Change subject: include/flash.h: Drop dead struct members
......................................................................
include/flash.h: Drop dead struct members
These were part of the original wp implementation, now dead
code left over.
Change-Id: I43b25175c6ff833b822a93c4e752a28cf97d64b8
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64373
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-by: Thomas Heijligen <src(a)posteo.de>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M include/flash.h
1 file changed, 0 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
Thomas Heijligen: Looks good to me, approved
Angel Pons: Looks good to me, approved
diff --git a/include/flash.h b/include/flash.h
index 89d5737..27ade09 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -266,8 +266,6 @@
int (*unlock) (struct flashctx *flash);
int (*write) (struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
int (*read) (struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
- uint8_t (*read_status) (const struct flashctx *flash);
- int (*write_status) (const struct flashctx *flash, int status);
struct voltage {
uint16_t min;
uint16_t max;
--
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49643 )
Change subject: libflashrom: Return progress state to the library user
......................................................................
Patch Set 19: Code-Review+2
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