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Daniel Campello has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49643 )
Change subject: libflashrom: Return progress state to the library user
......................................................................
Patch Set 21:
(1 comment)
File cli_classic.c:
https://review.coreboot.org/c/flashrom/+/49643/comment/d069f6f9_790231d8
PS20, Line 941: flashrom_set_progress_callback(fill_flash, &flashrom_progress_cb, &progress_state);
:
:
> I think one last thing here is to put this behind a cli flag and remember to update the man page too […]
Done
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Daniel Campello has uploaded a new patch set (#21) to the change originally created by Richard Hughes. ( https://review.coreboot.org/c/flashrom/+/49643 )
Change subject: libflashrom: Return progress state to the library user
......................................................................
libflashrom: Return progress state to the library user
Projects using libflashrom like fwupd expect the user to wait for the
operation to complete. To avoid the user thinking the process has
"hung" or "got stuck" report back the progress complete of the erase,
write and read operations.
Add a new --progress flag to the CLI to report progress of operations.
Include a test for the dummy spi25 device.
TEST=./test_build.sh; ./flashrom -p lspcon_i2c_spi:bus=7 -r /dev/null --progress
Change-Id: I7197572bb7f19e3bdb2bde855d70a0f50fd3854c
Signed-off-by: Richard Hughes <richard(a)hughsie.com>
Signed-off-by: Daniel Campello <campello(a)chromium.org>
---
M 82802ab.c
M at45db.c
M cli_classic.c
M cli_output.c
M dediprog.c
M en29lv640b.c
M flashrom.8.tmpl
M include/flash.h
M include/libflashrom.h
M it87spi.c
M jedec.c
M libflashrom.c
M libflashrom.map
M linux_mtd.c
M lspcon_i2c_spi.c
M realtek_mst_i2c_spi.c
M spi.c
M spi25.c
M sst28sf040.c
M tests/spi25.c
M tests/tests.c
M tests/tests.h
22 files changed, 184 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/43/49643/21
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64440 )
Change subject: ft2232_spi.c: Add support for kt-link jtag interface
......................................................................
Patch Set 3:
(3 comments)
File ft2232_spi.c:
https://review.coreboot.org/c/flashrom/+/64440/comment/2efeb952_ac62a1c2
PS1, Line 80: {FTDI_VID, KT_LINK_PID, OK, "Kristech", "KT-LINK"},
> Move this line to the other FTDIs
still remaining
https://review.coreboot.org/c/flashrom/+/64440/comment/adcd9eb5_3c3713d0
PS1, Line 671:
> remove space
Done
https://review.coreboot.org/c/flashrom/+/64440/comment/cc145f32_6331de35
PS1, Line 684:
> remove space
Done
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64425 )
Change subject: flashchips.c: Fix 4BA for S25FL512S
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
NB. It's rather nuts how many different ways the manufacturers
invented to support 4-byte addresses. It makes flashrom annoyingly
complex in this area (I guess at least when one is not used to all
the different concepts). So far I had no good idea how to handle
things better. Maybe we could try to add missing feature flags
(like those 0x16/0x17 opcodes) and align the names better with
datasheets (if there are similarities; for instance, today I read
a lot "bank address register" instead of extended address register,
but this might be just coincidence).
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Change subject: flashchips.c: Fix 4BA for S25FL512S
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/64425/comment/43d56b98_ec289396
PS1, Line 9: any features
> _NATIVE is already a set of features, namely 4BA read (0x13), fast read (0x0c) […]
Re-read the sentence and this might be what's causing confusion: The "native"
commands don't need a mode. They are supposed to work in any state and always
take 4-byte addresses.
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Change subject: flashchips.c: Fix 4BA for S25FL512S
......................................................................
Patch Set 1:
(4 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/64425/comment/379403a8_cf5ba043
PS1, Line 9: any features
_NATIVE is already a set of features, namely 4BA read (0x13), fast read (0x0c)
and write (0x12) instructions.
https://review.coreboot.org/c/flashrom/+/64425/comment/d879a8a7_c84026d0
PS1, Line 12: so select them through `FEATURE_4BA_EAR7`. As it is not known how this
It looks like they use different opcodes, though (16/17 instead of
the supported c5/c8). Which might be the original reason why it was
left out :-/
It might not be worth to add support for this untested. Dunno. If
we decide against it, I can add a comment why the entry looks so odd.
https://review.coreboot.org/c/flashrom/+/64425/comment/2c676b85_747669f6
PS1, Line 13: chip definition could actually work, it has been marked as untested.
Only a programmer that can't send 4-byte addresses or restricts the
commands that can be send would have failed, AFAICS.
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/64425/comment/6f90734b_d956119a
PS1, Line 16732: }, {
Here is the actual issue why I put the entry on my release preparations
list. spi_block_erase_dc() would fail if the programmer doesn't support
4-byte addresses. Then, flashrom would automatically try to fall back
to the next eraser and erase the whole chip. It wouldn't be fatal,
just very inconvenient to wait for 64MiB to be erased.
Well, that was my assessment. It's not 100% correct. I guess flashrom
would bail out trying to read the chip already ;)
*scrolling noises*
The datasheet I found (Cypress, Document Number: 001-98284 Rev. *P,
Revised June 22, 2018) also mentions 0xd8 for the same block size
but as 3BA or 4BA command, depending on EAR7 (if we would support it
with the 0x16/0x17 commands).
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Change subject: libflashrom: Return progress state to the library user
......................................................................
Patch Set 20: Code-Review+2
(1 comment)
File cli_classic.c:
https://review.coreboot.org/c/flashrom/+/49643/comment/4314adee_3886b8e8
PS20, Line 941: flashrom_set_progress_callback(fill_flash, &flashrom_progress_cb, &progress_state);
:
:
I think one last thing here is to put this behind a cli flag and remember to update the man page too. That way people don't get this if they didn't want it by default.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64424 )
Change subject: flashchips.c: Drop incorrect `FEATURE_4BA_ENTER_EAR7` uses
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/64424/comment/45b092ae_1fe322fd
PS1, Line 12: if `FEATURE_4BA_ENTER` is not set.
This is true, but I don't see the problem (yet). The flash chip
entry describes what the chip can do, not what flashrom can do.
It seems possible that a future change or programmer addition
could make use of this additional information (for instance,
if the dedicated EN4B command can't be executed for whatever
reason).
I hope I interpreted this right: The flash chip entry is correct
by itself, just together with the code it looks wrong. Is that
the case?
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Hello Felix Singer, build bot (Jenkins), Thomas Heijligen, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/64259
to look at the new patch set (#2).
Change subject: flashchips: Add voltage data for several chips
......................................................................
flashchips: Add voltage data for several chips
The following flashchips are missing voltage data. Thus, add them.
* Intel 28F002BC/BL/BV/BX-T
* Intel 28F004B5/BE/BV/BX-B
* Intel 28F004B5/BE/BV/BX-T
* Intel 28F008S3/S5/SC
* Intel 28F400BV/BX/CE/CV-B
* Intel 28F400BV/BX/CE/CV-T
* Micron/Numonyx/ST M25P40-old
* SyncMOS/MoselVitelic {F,S,V}29C51002T
* Winbond W29C010(M)/W29C011A/W29EE011/W29EE012
* Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old
Signed-off-by: ChinmayLonkar <chinmay20220(a)gmail.com>
Change-Id: I796a0933570adbbd18e3e7852c420fee82666b13
---
M flashchips.c
1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/59/64259/2
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Hello Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/64440
to look at the new patch set (#3).
Change subject: ft2232_spi.c: Add support for kt-link jtag interface
......................................................................
ft2232_spi.c: Add support for kt-link jtag interface
Change tested writing, reading and erasing spi flashes
pinout:
jtag - spi
1 vcc - vcc, wp#, hold#
4 gnd - gnd
5 tdi - si
7 tms - cs#
9 tck - sck
13 tdo - so
Connect pins 9 and 12 in EXT connector for 3.3V power.
Signed-off-by: Jacek Naglak <jnaglak(a)tlen.pl>
Change-Id: Id58c675bc410ec3ef6d58603d13efc9ca53bb87c
---
M ft2232_spi.c
1 file changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/64440/3
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