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Change subject: dummyflasher: emulate SR2 and SR3 for W25Q128FV
......................................................................
dummyflasher: emulate SR2 and SR3 for W25Q128FV
Enable emulation of SR2 and SR3 for W25Q128FV and provide logic for
updating them (masks of read-only bits that can't be set from outside).
Change-Id: I79f9b4a0b604663d3288ad70dcbe3ea4075dede5
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M dummyflasher.c
1 file changed, 26 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/59073/32
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Nikolai Artemiev, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#32).
Change subject: dummyflasher: add SR2 and SR3 emulation harness
......................................................................
dummyflasher: add SR2 and SR3 emulation harness
Prepare everything for emulating SR2 and SR3 for chips that have it.
This is needed for accessing SRP1 and WPS bits which are involved in
write protection. The emulated register doesn't affect anything yet
and will be tested by write-protection tests.
Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M dummyflasher.c
M flashrom.8.tmpl
2 files changed, 109 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/59072/32
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I'd like you to reexamine a change. Please visit
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Change subject: flashchips: enable write-protection for W25Q{64,128}.V
......................................................................
flashchips: enable write-protection for W25Q{64,128}.V
Configuration for W25Q64 was tested on hardware (W25Q64FV).
Emulation of W25Q128 in dummyflasher will be extended to support WP.
Haven't tested this one on hardware, but it's the same configuration as
for W25Q64 except that it has WPS.
W25Q64JV chip was renamed to W25Q64JV-.M (those with QPI).
W25Q64.V chip was split into W25Q64BV/W25Q64CV/W25Q64FV (no SR3 and WPS)
and W25Q64JV-.Q (SR3 and WPS, but no QPI).
Change-Id: Iccb69a8d3a0dd2192e2c938caddaf07b1889ed35
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flashchips.c
1 file changed, 76 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/59071/28
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I'd like you to reexamine a change. Please visit
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Change subject: writeprotect: add WPS bit and always set it to zero
......................................................................
writeprotect: add WPS bit and always set it to zero
WPS bit controls use of individual block protection which is mutually
exclusive with protection based on ranges. Proper support requires
extension of the API as well as implementation, so here we're just
making sure that range-based protection is enabled and our WP
configuration is not ignored by the chip.
Change-Id: I2c26ec65d64a3b6fb1f1a73690bc771415db2744
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flash.h
M writeprotect.c
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/31/60231/12
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I'd like you to reexamine a change. Please visit
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Change subject: spi25_statusreg.c: add SR3 read/write support
......................................................................
spi25_statusreg.c: add SR3 read/write support
Adds support for reading and writing the third status register.
Feature flag is not needed because it would never on its own control
whether SR3 access occurs. If added, it would be in one of three
possible states: wrong, useless or redundant.
Change-Id: Id987c544c02da2b956e6ad2c525265cac8f15be1
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flash.h
M spi.h
M spi25_statusreg.c
3 files changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/60230/12
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63921 )
Change subject: flashchips.c: mark PM25LQ020 as TESTED_OK_PREW
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
From https://github.com/flashrom/flashrom/pull/205
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63920 )
Change subject: nic3com: mark PCI id 9006 as supported
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
From https://github.com/flashrom/flashrom/pull/219
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