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Change subject: raiden_debug_spi.c: Document where raiden_debug_spi_requests are handled
......................................................................
Patch Set 2:
(2 comments)
File raiden_debug_spi.c:
https://review.coreboot.org/c/flashrom/+/63902/comment/728571b0_3a8f8d89
PS2, Line 402: /* Corresponds with 'enum usb_spi_request' in platform/cr50/chip/g/usb_spi.h */
> Also partially with platform/ec/chip/stm32/usb_spi.h.
Done
https://review.coreboot.org/c/flashrom/+/63902/comment/7994f7d1_b98c6f2c
PS2, Line 1451: * by adapters that only support one target
> Yes, my mistake!
Done
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Hello Sam McNally, build bot (Jenkins), Peter Marheine,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/63902
to look at the new patch set (#3).
Change subject: raiden_debug_spi.c: Document where raiden_debug_spi_requests are handled
......................................................................
raiden_debug_spi.c: Document where raiden_debug_spi_requests are handled
Because the enum is a different name to the one within cr50 it
was entirely unclear where these values were handled at the end-point
and what a untargetted REQ_ENABLE actually did. Comment to avoid
needing to chase this again.
BUG=b:224358254
TEST=builds
Change-Id: I8cc78a85660190c9f750bf67994f0d59d69592d8
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M raiden_debug_spi.c
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/02/63902/3
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59071 )
Change subject: flashchips: enable write-protection for W25Q{64,128}.V
......................................................................
Patch Set 28:
(1 comment)
Patchset:
PS28:
This patch has not been rebased on the latest flashchips.c it seems, so it is now "Merge Conflict".
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Change subject: Introduce an `include` directory for header files
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
Patchset:
PS7:
I uploaded new patchset because flash.h has changed (SR3 support in CB:60230 and CB:60231) and gerrit marked this as conflict.
I downloaded this patch on the top of the tree locally, it got applied automatically, no conflict resolutions were needed. I also checked that flash.h in latest patchset is up-to-date (contains SR3 support).
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Anastasia Klimchuk has uploaded a new patch set (#7) to the change originally created by Felix Singer. ( https://review.coreboot.org/c/flashrom/+/58622 )
Change subject: Introduce an `include` directory for header files
......................................................................
Introduce an `include` directory for header files
Move all header files to the new `include` directory.
Adapt include directives and build systems to the new directory.
Change-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf
Signed-off-by: Felix Singer <felix.singer(a)secunet.com>
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
---
M Makefile
R include/chipdrivers.h
R include/coreboot_tables.h
R include/custom_baud.h
R include/edi.h
R include/ene.h
R include/flash.h
R include/flashchips.h
R include/fmap.h
R include/hwaccess_physmap.h
R include/hwaccess_x86_io.h
R include/hwaccess_x86_msr.h
R include/i2c_helper.h
R include/ich_descriptors.h
R include/layout.h
R include/libflashrom.h
R include/platform.h
R include/platform/pci.h
R include/programmer.h
R include/spi.h
R include/usb_device.h
R include/writeprotect.h
M meson.build
M platform/endian_big.c
M platform/endian_little.c
M platform/memaccess.c
M util/ich_descriptors_tool/Makefile
M util/ich_descriptors_tool/meson.build
28 files changed, 16 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/22/58622/7
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Change subject: Introduce an `include` directory for header files
......................................................................
Patch Set 6: Code-Review+2
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Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/60231 )
Change subject: writeprotect: add WPS bit and always set it to zero
......................................................................
writeprotect: add WPS bit and always set it to zero
WPS bit controls use of individual block protection which is mutually
exclusive with protection based on ranges. Proper support requires
extension of the API as well as implementation, so here we're just
making sure that range-based protection is enabled and our WP
configuration is not ignored by the chip.
Change-Id: I2c26ec65d64a3b6fb1f1a73690bc771415db2744
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60231
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com>
Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org>
---
M flash.h
M writeprotect.c
2 files changed, 9 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nikolai Artemiev: Looks good to me, but someone else must approve
Anastasia Klimchuk: Looks good to me, approved
diff --git a/flash.h b/flash.h
index 509f226..9493fd2 100644
--- a/flash.h
+++ b/flash.h
@@ -307,6 +307,9 @@
/* Complement bit (CMP) */
struct reg_bit_info cmp;
+
+ /* Write Protect Selection (per sector protection when set) */
+ struct reg_bit_info wps;
} reg_bits;
/* Function that takes a set of WP config bits (e.g. BP, SEC, TB, etc) */
diff --git a/writeprotect.c b/writeprotect.c
index 5893593..ab6b176 100644
--- a/writeprotect.c
+++ b/writeprotect.c
@@ -73,6 +73,8 @@
if (ret != FLASHROM_WP_OK)
return ret;
+ /* Note: WPS bit isn't read here, because it's not part of any range. */
+
for (i = 0; i < ARRAY_SIZE(bits->bp); i++) {
if (bit_map->bp[i].reg == INVALID_REG)
break;
@@ -115,6 +117,8 @@
set_reg_bit(reg_values, write_masks, reg_bits->cmp, bits.cmp);
set_reg_bit(reg_values, write_masks, reg_bits->srp, bits.srp);
set_reg_bit(reg_values, write_masks, reg_bits->srl, bits.srl);
+ /* Note: always setting WPS bit to zero until its fully supported. */
+ set_reg_bit(reg_values, write_masks, reg_bits->wps, 0);
/* Write each register */
for (enum flash_reg reg = STATUS1; reg < MAX_REGISTERS; reg++) {
@@ -253,6 +257,8 @@
*count = 1 << bit_count;
*ranges = calloc(*count, sizeof(struct wp_range_and_bits));
+ /* TODO: take WPS bit into account. */
+
for (size_t range_index = 0; range_index < *count; range_index++) {
/*
* Extract bits from the range index and assign them to members
9 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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