Sean Anderson has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43608 )
Change subject: buspirate: Add option for setting the aux pin
......................................................................
buspirate: Add option for setting the aux pin
This adds a parameter to drive the aux pin low (or high if you
explicitly want the previous behavior). Some boards need to have a reset
pin driven low before the firmware can be safely flashed. With the Bus
Pirate, this is most easily done with the auxiliary pin.
Change-Id: Ieeecfdf1afc06dadda9b8f99547cd74854ca6775
Signed-off-by: Sean Anderson <seanga2(a)gmail.com>
---
M buspirate_spi.c
M flashrom.8.tmpl
2 files changed, 33 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/43608/1
diff --git a/buspirate_spi.c b/buspirate_spi.c
index fdfc0e4..1ccb107 100644
--- a/buspirate_spi.c
+++ b/buspirate_spi.c
@@ -228,6 +228,7 @@
int serialspeed_index = -1;
int ret = 0;
int pullup = 0;
+ int aux = 1;
dev = extract_programmer_param("dev");
if (dev && !strlen(dev)) {
@@ -277,6 +278,17 @@
}
free(tmp);
+ tmp = extract_programmer_param("aux");
+ if (tmp) {
+ if (strcasecmp("high", tmp) == 0)
+ ; /* Default */
+ else if (strcasecmp("low", tmp) == 0)
+ aux = 0;
+ else
+ msg_perr("Invalid AUX state, driving high by default.\n");
+ }
+ free(tmp);
+
/* Default buffer size is 19: 16 bytes data, 3 bytes control. */
#define DEFAULT_BUFSIZE (16 + 3)
bp_commbuf = malloc(DEFAULT_BUFSIZE);
@@ -520,11 +532,18 @@
}
/* Initial setup (SPI peripherals config): Enable power, CS high, AUX */
- bp_commbuf[0] = 0x40 | 0x0b;
+ bp_commbuf[0] = 0x40 | 0x09;
if (pullup == 1) {
bp_commbuf[0] |= (1 << 2);
msg_pdbg("Enabling pull-up resistors.\n");
}
+ if (aux) {
+ bp_commbuf[0] |= (1 << 1);
+ msg_pdbg("Driving AUX high.\n");
+ } else {
+ msg_pdbg("Driving AUX low.\n");
+ }
+
ret = buspirate_sendrecv(bp_commbuf, 1, 1);
if (ret)
return 1;
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index db50d59..caf860c 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -902,6 +902,19 @@
.URLB "http://dangerousprototypes.com/docs/Practical_guide_to_Bus_Pirate_pull-up_r…" \
"in a guide by dangerousprototypes" .
Only the external supply voltage (Vpu) is supported as of this writing.
+.sp
+An optional aux parameter specifies the state of the Bus Pirate auxiliary pin.
+This may be used to drive the auxiliary pin high or low before a transfer.
+Syntax is
+.sp
+.B " flashrom -p buspirate_spi:aux=state"
+.sp
+where
+.B state
+can be
+.BR high " or " low .
+The default
+.BR state " is " high .
.SS
.BR "pickit2_spi " programmer
.IP
--
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Gerrit-Change-Id: Ieeecfdf1afc06dadda9b8f99547cd74854ca6775
Gerrit-Change-Number: 43608
Gerrit-PatchSet: 1
Gerrit-Owner: Sean Anderson <seanga2(a)gmail.com>
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Attention is currently required from: Felix Singer, Nico Huber, Paul Menzel, Angel Pons, Light.
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63130 )
Change subject: pony_spi.c: Extract out get_params to simplify init
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/63130/comment/cf0f5029_97fd7e36
PS5, Line 9: function pony_init_spi)`,
> I would appreciate if you move this to the next line. […]
Done
https://review.coreboot.org/c/flashrom/+/63130/comment/6be39e72_c863ea25
PS5, Line 10: number of
> same here
Done
--
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Attention is currently required from: Nico Huber, Paul Menzel, Edward O'Callaghan, Angel Pons, Light.
Hello Felix Singer, build bot (Jenkins), Light, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/63130
to look at the new patch set (#6).
Change subject: pony_spi.c: Extract out get_params to simplify init
......................................................................
pony_spi.c: Extract out get_params to simplify init
In light of `commit caa0335114a81`, extract out the get_param logic to
its own function to simplify the number of cleanup paths.
BUG=none
TEST=builds
Change-Id: I364febc05c870683cbad114583762b0c006f4bac
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M pony_spi.c
1 file changed, 55 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/63130/6
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Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/63902 )
Change subject: raiden_debug_spi.c: Document where raiden_debug_spi_requests are handled
......................................................................
raiden_debug_spi.c: Document where raiden_debug_spi_requests are handled
Because the enum is a different name to the one within cr50 it
was entirely unclear where these values were handled at the end-point
and what a untargetted REQ_ENABLE actually did. Comment to avoid
needing to chase this again.
BUG=b:224358254
TEST=builds
Change-Id: I8cc78a85660190c9f750bf67994f0d59d69592d8
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63902
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Sam McNally <sammc(a)google.com>
Reviewed-by: Peter Marheine <pmarheine(a)chromium.org>
---
M raiden_debug_spi.c
1 file changed, 8 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Sam McNally: Looks good to me, approved
Peter Marheine: Looks good to me, but someone else must approve
diff --git a/raiden_debug_spi.c b/raiden_debug_spi.c
index 521539f..f9ab3e0 100644
--- a/raiden_debug_spi.c
+++ b/raiden_debug_spi.c
@@ -399,6 +399,10 @@
USB_SPI_UNKNOWN_ERROR = 0x8000,
};
+/* Corresponds with 'enum usb_spi_request' in,
+ * platform/cr50/chip/g/usb_spi.h and,
+ * platform/ec/chip/stm32/usb_spi.h.
+ */
enum raiden_debug_spi_request {
RAIDEN_DEBUG_SPI_REQ_ENABLE = 0x0000,
RAIDEN_DEBUG_SPI_REQ_DISABLE = 0x0001,
@@ -1445,6 +1449,10 @@
static int get_target(void)
{
+ /**
+ * REQ_ENABLE doesn't specify a target bus, and will be rejected
+ * by adapters that support more than one target.
+ */
int request_enable = RAIDEN_DEBUG_SPI_REQ_ENABLE;
char *target_str = extract_programmer_param("target");
--
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Attention is currently required from: Nico Huber, Sergii Dmytruk.
Hello build bot (Jenkins), Nico Huber, Angel Pons, Nikolai Artemiev, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/59075
to look at the new patch set (#35).
Change subject: tests: test write protection
......................................................................
tests: test write protection
Tests both WP implementation and its emulation in dummy programmer.
Change-Id: I49af7f6d173eb4c56c22d80b01a473b8c499c0f8
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
A tests/chip_wp.c
M tests/meson.build
M tests/tests.c
M tests/tests.h
4 files changed, 338 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/75/59075/35
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