April 2022 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: ichspi: Rename HSFC FDBC offset macros
by Subrata Banik (Code Review) 15 Apr '22

15 Apr '22

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62894 ) Change subject: ichspi: Rename HSFC FDBC offset macros ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/62894/comment/5ffdbaff_79d4c295 PS6, Line 10: during the data portion of the SPI cycle. > That would work I think. Done -- To view, visit https://review.coreboot.org/c/flashrom/+/62894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia0ae9a586b5c12f0229334898426175ec246a70c Gerrit-Change-Number: 62894 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 18:16:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: ichspi: Rename HSFC FDBC offset macros
by Subrata Banik (Code Review) 15 Apr '22

15 Apr '22

Subrata Banik has abandoned this change. ( https://review.coreboot.org/c/flashrom/+/62894 ) Change subject: ichspi: Rename HSFC FDBC offset macros ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/flashrom/+/62894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia0ae9a586b5c12f0229334898426175ec246a70c Gerrit-Change-Number: 62894 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-MessageType: abandon

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Change in flashrom[master]: raiden_debug_spi.c: Allow custom_rst param value of 'false'
by Edward O'Callaghan (Code Review) 15 Apr '22

15 Apr '22

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/63601 ) Change subject: raiden_debug_spi.c: Allow custom_rst param value of 'false' ...................................................................... raiden_debug_spi.c: Allow custom_rst param value of 'false' As identified while documenting driver, allow for passing 'false' even though it is the default for custom_rst to be consistent. BUG=b:224358254 TEST=builds Change-Id: I25bfe6f8e3f7cfffb1a9c99ac90ec56a750d7f84 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/63601 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sam McNally <sammc(a)google.com> --- M raiden_debug_spi.c 1 file changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved diff --git a/raiden_debug_spi.c b/raiden_debug_spi.c index 3f35552..65ce32b 100644 --- a/raiden_debug_spi.c +++ b/raiden_debug_spi.c @@ -1412,9 +1412,11 @@ int ap_request = RAIDEN_DEBUG_SPI_REQ_ENABLE_AP; char *custom_rst_str = extract_programmer_param("custom_rst"); if (custom_rst_str) { - if (!strcasecmp(custom_rst_str, "true")) + if (!strcasecmp(custom_rst_str, "true")) { ap_request = RAIDEN_DEBUG_SPI_REQ_ENABLE_AP_CUSTOM; - else { + } else if (!strcasecmp(custom_rst_str, "false")) { + ap_request = RAIDEN_DEBUG_SPI_REQ_ENABLE_AP; + } else { msg_perr("Invalid custom rst param: %s\n", custom_rst_str); ap_request = -1; -- To view, visit https://review.coreboot.org/c/flashrom/+/63601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I25bfe6f8e3f7cfffb1a9c99ac90ec56a750d7f84 Gerrit-Change-Number: 63601 Gerrit-PatchSet: 4 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: meson: Add optimisation level s into meson build
by Thomas Heijligen (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Edward O'Callaghan, Angel Pons, Anastasia Klimchuk. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63606 ) Change subject: meson: Add optimisation level s into meson build ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Meson uses debug build as default. So the binary get a lot bigger than with make. If you disable debug and add optimizations the difference get smaller. -- To view, visit https://review.coreboot.org/c/flashrom/+/63606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4ca96a866529cac320e66516ef280d5100ceefab Gerrit-Change-Number: 63606 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 14 Apr 2022 15:01:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: Add -W options from Makefile into meson warning_flags
by Thomas Heijligen (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Anastasia Klimchuk. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58561 ) Change subject: Add -W options from Makefile into meson warning_flags ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/58561/comment/23510dca_0a132521 PS4, Line 13: warning_level=2 means -Wall and -Wextra as it is set in Needs update. This is now in the next patch. -- To view, visit https://review.coreboot.org/c/flashrom/+/58561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id401bfd642dc3c13d85bd9a2dba56ada38714c25 Gerrit-Change-Number: 58561 Gerrit-PatchSet: 4 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 14 Apr 2022 14:50:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: tests: Add and include headers with function prototypes
by Thomas Heijligen (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Nico Huber, Angel Pons, Anastasia Klimchuk. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63489 ) Change subject: tests: Add and include headers with function prototypes ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/63489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia1ff22deb2354569f277649c6575ef2d5ffbb6e0 Gerrit-Change-Number: 63489 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 14 Apr 2022 14:46:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: tests: Mark all static functions as static
by Thomas Heijligen (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Angel Pons, Anastasia Klimchuk. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63571 ) Change subject: tests: Mark all static functions as static ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/63571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic54da5ac1b2a46f55e3e3bee4ed952bdf59e8444 Gerrit-Change-Number: 63571 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 14 Apr 2022 14:40:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: ich_descriptors_tool: Fix -Wsign-compare warnings
by Thomas Heijligen (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Nico Huber, Angel Pons, Anastasia Klimchuk. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63488 ) Change subject: ich_descriptors_tool: Fix -Wsign-compare warnings ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/63488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1f9325e9cf89f57f18d63cc3906a0958b47286d7 Gerrit-Change-Number: 63488 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 14 Apr 2022 14:36:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: ichspi: Add Jasper Lake support
by Edward O'Callaghan (Code Review) 14 Apr '22

14 Apr '22

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62282 ) Change subject: ichspi: Add Jasper Lake support ...................................................................... ichspi: Add Jasper Lake support Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Jasper Lake is the same as Elkhart Lake. BUG=b:221175960 TEST=dedede with `flashrom -p internal --flash-size`. ``` $ flashrom -VVV -p internal --ifd -i fd -i bios -r /tmp/filename.rom <snip> Enabling hardware sequencing by default for 100+ series PCH. OK. No board enable found matching coreboot IDs vendor="Google", model="Magolor". The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Chip identified: GD25Q127C/GD25Q128C Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB. There is only one partition containing the whole address space (0x000000 - 0xffffff). There are 4096 erase blocks with 4096 B each. Added layout entry 00000000 - 00ffffff named complete flash Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading Status register Block protection is disabled. Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset 'Jasper Lake'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00381000 - 00ffffff named bios Added layout entry 00001000 - 00380fff named me restore_power_management: Re-enabling power management. Using regions: "bios", "fd". Reading Status register Block protection is disabled. Reading flash... 0x381000-0xffffff:R Reading 13103104 bytes starting at 0x381000. 000000-0x0fff:R Reading 4096 bytes starting at 0x000000. done. restore_power_management: Re-enabling power management. SUCCESS Restoring PCI config space for 00:1f:5 reg 0xdc restore_power_management: Re-enabling power management. ``` Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62282 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Sam McNally <sammc(a)google.com> --- M chipset_enable.c M ich_descriptors.c M ichspi.c M programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 5 files changed, 36 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/chipset_enable.c b/chipset_enable.c index 27ab126..a0bffa0 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -610,6 +610,7 @@ case CHIPSET_ELKHART_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: reg_name = "BIOS_SPI_BC"; gcs = pci_read_long(dev, 0xdc); bild = (gcs >> 7) & 1; @@ -717,6 +718,7 @@ break; case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: boot_straps = boot_straps_apl; break; @@ -749,6 +751,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: bbs = (gcs >> 6) & 0x1; break; @@ -1015,6 +1018,11 @@ return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE); } +static int enable_flash_jsl(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_JASPER_LAKE); +} + static int enable_flash_apl(struct pci_dev *const dev, const char *const name) { return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); @@ -2129,6 +2137,7 @@ {0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, {0x8086, 0x3197, B_S, NT, "Intel", "Gemini Lake", enable_flash_glk}, {0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk}, + {0x8086, 0x4da4, B_S, DEP, "Intel", "Jasper Lake", enable_flash_jsl}, {0x8086, 0x4b24, B_S, DEP, "Intel", "Elkhart Lake", enable_flash_mcc}, {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, diff --git a/ich_descriptors.c b/ich_descriptors.c index 4d85e08..0eabe95 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -49,6 +49,7 @@ case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: case CHIPSET_ELKHART_LAKE: + case CHIPSET_JASPER_LAKE: return 16; case CHIPSET_100_SERIES_SUNRISE_POINT: return 10; @@ -77,6 +78,7 @@ case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: if (cont->NM <= MAX_NUM_MASTERS) return cont->NM; @@ -115,7 +117,8 @@ "8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg", "9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point", "C620 series Lewisburg", "300 series Cannon Point", "400 series Comet Point", - "500 series Tiger Point", "600 series Alder Point", "Meteor Lake", "Apollo Lake", "Gemini Lake", "Elkhart Lake", + "500 series Tiger Point", "600 series Alder Point", "Meteor Lake", + "Apollo Lake", "Gemini Lake", "Jasper Lake", "Elkhart Lake", }; if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names)) cs = 0; @@ -214,6 +217,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: { uint8_t size_enc; if (idx == 0) { @@ -301,6 +305,7 @@ case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_400_SERIES_COMET_POINT: + case CHIPSET_JASPER_LAKE: return freq_str[1][value]; case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: @@ -358,6 +363,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: has_flill1 = true; break; @@ -482,7 +488,7 @@ cs == CHIPSET_400_SERIES_COMET_POINT || cs == CHIPSET_500_SERIES_TIGER_POINT || cs == CHIPSET_600_SERIES_ALDER_POINT || - cs == CHIPSET_METEOR_LAKE) { + cs == CHIPSET_JASPER_LAKE || cs == CHIPSET_METEOR_LAKE) { const char *const master_names[] = { "BIOS", "ME", "GbE", "unknown", "EC", }; @@ -1047,10 +1053,12 @@ if (content->CSSL == 0x14) return CHIPSET_600_SERIES_ALDER_POINT; if (content->CSSL == 0x03) { - if (content->CSSO == 0x70) - return CHIPSET_METEOR_LAKE; - else + if (content->CSSO == 0x58) return CHIPSET_ELKHART_LAKE; + else if (content->CSSO == 0x6c) + return CHIPSET_JASPER_LAKE; + else if (content->CSSO == 0x70) + return CHIPSET_METEOR_LAKE; } msg_pwarn("Unknown flash descriptor, assuming 500 series compatibility.\n"); return CHIPSET_500_SERIES_TIGER_POINT; @@ -1076,6 +1084,7 @@ case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_METEOR_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: /* `freq_read` was repurposed, so can't check on it any more. */ break; @@ -1235,6 +1244,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; @@ -1276,6 +1286,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: mmio_le_writel(control, spibar + PCH100_REG_FDOC); return mmio_le_readl(spibar + PCH100_REG_FDOD); diff --git a/ichspi.c b/ichspi.c index a377247..c25303e 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1802,6 +1802,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: *num_pr = 6; /* Includes GPR0 */ *reg_pr0 = PCH100_REG_FPR0; @@ -1840,6 +1841,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: *num_freg = 16; break; @@ -1900,6 +1902,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: tmp = mmio_readl(spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); @@ -1979,6 +1982,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_BAYTRAIL: case CHIPSET_ELKHART_LAKE: break; @@ -2017,6 +2021,7 @@ case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: break; default: @@ -2058,9 +2063,10 @@ if (ich_spi_mode == ich_auto && (ich_gen == CHIPSET_APOLLO_LAKE || ich_gen == CHIPSET_GEMINI_LAKE || + ich_gen == CHIPSET_JASPER_LAKE || ich_gen == CHIPSET_ELKHART_LAKE || ich_gen == CHIPSET_METEOR_LAKE)) { - msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Elkhart/Meteor Lake.\n"); + msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Jasper/Elkhart/Meteor Lake.\n"); ich_spi_mode = ich_hwseq; } diff --git a/programmer.h b/programmer.h index 86e45f7..5fb0626 100644 --- a/programmer.h +++ b/programmer.h @@ -353,6 +353,7 @@ CHIPSET_METEOR_LAKE, CHIPSET_APOLLO_LAKE, CHIPSET_GEMINI_LAKE, + CHIPSET_JASPER_LAKE, CHIPSET_ELKHART_LAKE, }; diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 13a1897..4951206 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -128,6 +128,7 @@ "\t- \"silvermont\" for chipsets from Intel's Silvermont architecture (e.g. Bay Trail),\n" "\t- \"apollo\" for Intel's Apollo Lake SoC.\n" "\t- \"gemini\" for Intel's Gemini Lake SoC.\n" +"\t- \"jasper\" for Intel's Jasper Lake SoC.\n" "\t- \"meteor\" for Intel's Meteor Lake SoC.\n" "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" @@ -242,6 +243,8 @@ cs = CHIPSET_APOLLO_LAKE; else if (strcmp(csn, "gemini") == 0) cs = CHIPSET_GEMINI_LAKE; + else if (strcmp(csn, "jasper") == 0) + cs = CHIPSET_JASPER_LAKE; else if (strcmp(csn, "elkhart") == 0) cs = CHIPSET_ELKHART_LAKE; else if (strcmp(csn, "meteor") == 0) 12 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/flashrom/+/62282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d Gerrit-Change-Number: 62282 Gerrit-PatchSet: 14 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: ichspi: Rename HSFC FDBC offset macros
by Nico Huber (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Subrata Banik, Angel Pons, Anastasia Klimchuk. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62894 ) Change subject: ichspi: Rename HSFC FDBC offset macros ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/62894/comment/4bb9a686_030deb91 PS6, Line 10: during the data portion of the SPI cycle. > > And only for `HSFC_FDBC -> HSFC_FDBC_MASK`, and not for the `_OFF` macro. […] That would work I think. -- To view, visit https://review.coreboot.org/c/flashrom/+/62894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia0ae9a586b5c12f0229334898426175ec246a70c Gerrit-Change-Number: 62894 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 14 Apr 2022 11:34:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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