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Daniel Campello has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62319 )
Change subject: tests/linux_spi: Validate param file path
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
File tests/init_shutdown.c:
https://review.coreboot.org/c/flashrom/+/62319/comment/83b38283_dab94616
PS4, Line 39: #define DEFAULT_MOCK_FD 0xC0FE
> Is there a specific meaning behind this number? We have already a NON_ZERO which is defined as […]
NON_ZERO is a negative int... I will fix this in another patch and we should be able to reuse instead of DEFAULT_MOCK_FD. It is currently being used by the wraps for open64 and friends...
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62764 )
Change subject: ich_descriptors.c: Ensure unsigned types >=0 on to prevent underflow
......................................................................
Patch Set 16: Code-Review+1
(1 comment)
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/62764/comment/79c230a2_c679301c
PS14, Line 501: for (j = 0; j < (size_t)min(num_regions, 12); j++)
> That was a question for Edward :) Let's wait for reply. […]
Not sure why you don't believe it is the max bounds in this case? Anastasia, the number of regions is initialised to 10 and 16 above but that isn't the *max* bound for the loop.
I am not overly concerned about the identifier name, `max_region_index` or something will do, the structure of the code is more important imho. The main thing here is that the static analyzer is alluding to a area of code that has a possibly overflow generally indicates poor structure that allows such subtle bugs to emerge.
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Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62761 )
Change subject: board_enable.c: Remove unnecessary assignment
......................................................................
board_enable.c: Remove unnecessary assignment
In function board_asus_p3b_f there were two consecutive lines which
modified the value of variable b
// Do something with b
b=INB(0x80);
b=INB(smbba);
//Do something with b
Since the value of b is not used after first assignment, remove the
first assignment.
Change-Id: I7458b416a69fd5e2aa300ca49d1352b6074ad0bc
Tested-by: Keith Hui <buurin(a)gmail.com>
Signed-off-by: Aarya Chaumal <aarya.chaumal(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62761
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org>
Reviewed-by: Keith Hui <buurin(a)gmail.com>
Reviewed-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
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---
M board_enable.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, but someone else must approve
Keith Hui: Looks good to me, but someone else must approve
Felix Singer: Looks good to me, but someone else must approve
Angel Pons: Looks good to me, but someone else must approve
Anastasia Klimchuk: Looks good to me, approved
diff --git a/board_enable.c b/board_enable.c
index 300fecb..442db33 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -910,7 +910,7 @@
/* Wait until SMBus transaction is complete. */
b = 0x1;
while (b & 0x01) {
- b = INB(0x80);
+ INB(0x80);
b = INB(smbba);
}
10 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62282 )
Change subject: ichspi: Add Jasper Lake support
......................................................................
Patch Set 7:
(3 comments)
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/62282/comment/ce1eecaf_89898e10
PS6, Line 1013: jlk
> Jasper lake is usually abbreviated as JSL.
Done
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/62282/comment/7638cd0c_2f1fea6d
PS6, Line 313: case CHIPSET_JASPER_LAKE:
> From the SPI programming guide I've seen (v0.8), this should use freq_str[1].
Ah your right, in rev 0.8 2020 I did see this in section 3.2. I think the version I looked at was earlier. Fixed then. Thanks for spotting this Sam!
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/62282/comment/2189d7f8_3ba3fb9f
PS6, Line 2063: msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Elkhart Lake.\n");
> Update the message to include Jasper Lake.
Done
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Hello build bot (Jenkins), Subrata Banik, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62282
to look at the new patch set (#7).
Change subject: ichspi: Add Jasper Lake support
......................................................................
ichspi: Add Jasper Lake support
Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect
the chipset when the CSSL (CPU Soft Strap Length) field default value
(0x03) on Jasper Lake is the same as Elkhart Lake.
BUG=b:221175960
TEST=dedede with `flashrom -p internal --flash-size`.
```
$ flashrom -VVV -p internal --ifd -i fd -i bios -r /tmp/filename.rom
<snip>
Enabling hardware sequencing by default for 100+ series PCH.
OK.
No board enable found matching coreboot IDs vendor="Google", model="Magolor".
The following protocols are supported: Programmer-specific.
Probing for Programmer Opaque flash chip, 0 kB: Chip identified: GD25Q127C/GD25Q128C
Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB.
There is only one partition containing the whole address space (0x000000 - 0xffffff).
There are 4096 erase blocks with 4096 B each.
Added layout entry 00000000 - 00ffffff named complete flash
Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific).
This chip may contain one-time programmable memory. flashrom cannot read
and may never be able to write it, hence it may not be able to completely
clone the contents of this chip (see man page for details).
Reading Status register
Block protection is disabled.
Reading ich descriptor... Reading 4096 bytes starting at 0x000000.
done.
Assuming chipset 'Jasper Lake'.
Added layout entry 00000000 - 00000fff named fd
Added layout entry 00381000 - 00ffffff named bios
Added layout entry 00001000 - 00380fff named me
restore_power_management: Re-enabling power management.
Using regions: "bios", "fd".
Reading Status register
Block protection is disabled.
Reading flash... 0x381000-0xffffff:R Reading 13103104 bytes starting at 0x381000.
000000-0x0fff:R Reading 4096 bytes starting at 0x000000.
done.
restore_power_management: Re-enabling power management.
SUCCESS
Restoring PCI config space for 00:1f:5 reg 0xdc
restore_power_management: Re-enabling power management.
```
Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M programmer.h
M util/ich_descriptors_tool/ich_descriptors_tool.c
5 files changed, 38 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/82/62282/7
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63130 )
Change subject: pony_spi.c: Extract out get_params to simplify init
......................................................................
Patch Set 3:
(2 comments)
File pony_spi.c:
https://review.coreboot.org/c/flashrom/+/63130/comment/5b87a07d_423b23d9
PS3, Line 167: bool have_device;
> This should probably be a separate patch? (changing variable type int -> bool)
A bit of nit isn't it? Is there a solid technical reason here or just personal preference?
https://review.coreboot.org/c/flashrom/+/63130/comment/079204ec_66a5c753
PS3, Line 190: serialport_shutdown
> This one line should probably also go to a very useful separate patch.
I think you are mis-interpreting the diff presented by gerrit Anastasia.
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