Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62761 )
Change subject: board_enable.c: Remove unnecessary assignment
......................................................................
board_enable.c: Remove unnecessary assignment
In function board_asus_p3b_f there were two consecutive lines which
modified the value of variable b
// Do something with b
b=INB(0x80);
b=INB(smbba);
//Do something with b
Since the value of b is not used after first assignment, remove the
first assignment.
Change-Id: I7458b416a69fd5e2aa300ca49d1352b6074ad0bc
Tested-by: Keith Hui <buurin(a)gmail.com>
Signed-off-by: Aarya Chaumal <aarya.chaumal(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62761
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org>
Reviewed-by: Keith Hui <buurin(a)gmail.com>
Reviewed-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M board_enable.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, but someone else must approve
Keith Hui: Looks good to me, but someone else must approve
Felix Singer: Looks good to me, but someone else must approve
Angel Pons: Looks good to me, but someone else must approve
Anastasia Klimchuk: Looks good to me, approved
diff --git a/board_enable.c b/board_enable.c
index 300fecb..442db33 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -910,7 +910,7 @@
/* Wait until SMBus transaction is complete. */
b = 0x1;
while (b & 0x01) {
- b = INB(0x80);
+ INB(0x80);
b = INB(smbba);
}
10 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Attention is currently required from: Sam McNally, Nico Huber, Angel Pons.
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62282 )
Change subject: ichspi: Add Jasper Lake support
......................................................................
Patch Set 7:
(3 comments)
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/62282/comment/ce1eecaf_89898e10
PS6, Line 1013: jlk
> Jasper lake is usually abbreviated as JSL.
Done
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/62282/comment/7638cd0c_2f1fea6d
PS6, Line 313: case CHIPSET_JASPER_LAKE:
> From the SPI programming guide I've seen (v0.8), this should use freq_str[1].
Ah your right, in rev 0.8 2020 I did see this in section 3.2. I think the version I looked at was earlier. Fixed then. Thanks for spotting this Sam!
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/62282/comment/2189d7f8_3ba3fb9f
PS6, Line 2063: msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Elkhart Lake.\n");
> Update the message to include Jasper Lake.
Done
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Comment-In-Reply-To: Sam McNally <sammc(a)google.com>
Gerrit-MessageType: comment
Attention is currently required from: Nico Huber, Edward O'Callaghan, Angel Pons.
Hello build bot (Jenkins), Subrata Banik, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62282
to look at the new patch set (#7).
Change subject: ichspi: Add Jasper Lake support
......................................................................
ichspi: Add Jasper Lake support
Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect
the chipset when the CSSL (CPU Soft Strap Length) field default value
(0x03) on Jasper Lake is the same as Elkhart Lake.
BUG=b:221175960
TEST=dedede with `flashrom -p internal --flash-size`.
```
$ flashrom -VVV -p internal --ifd -i fd -i bios -r /tmp/filename.rom
<snip>
Enabling hardware sequencing by default for 100+ series PCH.
OK.
No board enable found matching coreboot IDs vendor="Google", model="Magolor".
The following protocols are supported: Programmer-specific.
Probing for Programmer Opaque flash chip, 0 kB: Chip identified: GD25Q127C/GD25Q128C
Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB.
There is only one partition containing the whole address space (0x000000 - 0xffffff).
There are 4096 erase blocks with 4096 B each.
Added layout entry 00000000 - 00ffffff named complete flash
Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific).
This chip may contain one-time programmable memory. flashrom cannot read
and may never be able to write it, hence it may not be able to completely
clone the contents of this chip (see man page for details).
Reading Status register
Block protection is disabled.
Reading ich descriptor... Reading 4096 bytes starting at 0x000000.
done.
Assuming chipset 'Jasper Lake'.
Added layout entry 00000000 - 00000fff named fd
Added layout entry 00381000 - 00ffffff named bios
Added layout entry 00001000 - 00380fff named me
restore_power_management: Re-enabling power management.
Using regions: "bios", "fd".
Reading Status register
Block protection is disabled.
Reading flash... 0x381000-0xffffff:R Reading 13103104 bytes starting at 0x381000.
000000-0x0fff:R Reading 4096 bytes starting at 0x000000.
done.
restore_power_management: Re-enabling power management.
SUCCESS
Restoring PCI config space for 00:1f:5 reg 0xdc
restore_power_management: Re-enabling power management.
```
Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M programmer.h
M util/ich_descriptors_tool/ich_descriptors_tool.c
5 files changed, 38 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/82/62282/7
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Gerrit-Change-Number: 62282
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Attention is currently required from: Light, Anastasia Klimchuk.
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63130 )
Change subject: pony_spi.c: Extract out get_params to simplify init
......................................................................
Patch Set 3:
(2 comments)
File pony_spi.c:
https://review.coreboot.org/c/flashrom/+/63130/comment/5b87a07d_423b23d9
PS3, Line 167: bool have_device;
> This should probably be a separate patch? (changing variable type int -> bool)
A bit of nit isn't it? Is there a solid technical reason here or just personal preference?
https://review.coreboot.org/c/flashrom/+/63130/comment/079204ec_66a5c753
PS3, Line 190: serialport_shutdown
> This one line should probably also go to a very useful separate patch.
I think you are mis-interpreting the diff presented by gerrit Anastasia.
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Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/63104 )
Change subject: flashrom.8.tmpl: document lspcon_i2c_spi
......................................................................
flashrom.8.tmpl: document lspcon_i2c_spi
This programmer operates much the same as realtek_mst_i2c_spi, so the
I2C options are moved to a new section describing both programmers
and a short description is added for this programmer itself.
Signed-off-by: Peter Marheine <pmarheine(a)chromium.org>
Change-Id: I9ccb9694fdea29e68f062cc049efc0204917a139
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63104
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flashrom.8.tmpl
1 file changed, 22 insertions(+), 11 deletions(-)
Approvals:
build bot (Jenkins): Verified
Edward O'Callaghan: Looks good to me, approved
Nikolai Artemiev: Looks good to me, but someone else must approve
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index 92dff68..bf8960f 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -395,6 +395,8 @@
.sp
.BR "* realtek_mst_i2c_spi" " (for SPI flash ROMs attached to Realtek DisplayPort hubs accessible through I2C)"
.sp
+.BR "* lspcon_i2c_spi" " (for SPI flash ROMs attached to Parade Technologies LSPCONs)"
+.sp
Some programmers have optional or mandatory parameters which are described
in detail in the
.B PROGRAMMER-SPECIFIC INFORMATION
@@ -1417,21 +1419,25 @@
If the passed frequency is not supported by the adapter the nearest lower
supported frequency will be used.
.SS
-.BR "realtek_mst_i2c_spi " programmer
+.BR "realtek_mst_i2c_spi " and " lspcon_i2c_spi " programmers
.IP
-This programmer supports SPI flash programming for chips attached to Realtek
-DisplayPort MST hubs, themselves accessed through I2C (tunneling SPI flash
-commands through the MST hub's I2C connection with the host).
-
-The I2C bus on which the hub is reachable must be specified by either a device
-path with the \fBdevpath\fP option:
+These programmers tunnel SPI commands through I2C-connected devices. The I2C
+bus over which communication occurs must be specified either by device path
+with the \fBdevpath\fP option:
.sp
.B " flashrom \-p realtek_mst_i2c_spi:devpath=/dev/i2c-8"
.sp
or by a bus number with the \fBbus\fP option, which implies a device path like
/dev/i2c-N where N is the specified bus number:
.sp
-.B " flashrom \-p realtek_mst_i2c_spi:bus=8"
+.B " flashrom \-p lspcon_i2c_spi:bus=8"
+
+.SS
+.BR "realtek_mst_i2c_spi " programmer
+.IP
+This programmer supports SPI flash programming for chips attached to Realtek
+DisplayPort MST hubs, themselves accessed through I2C (tunneling SPI flash
+commands through the MST hub's I2C connection with the host).
.TP
.B In-system programming (ISP) mode
.sp
@@ -1456,7 +1462,12 @@
.B " flashrom -p realtek_mst_i2c_spi:bus=0,enter-isp=1,reset-mcu=0 -E"
.br
.B " flashrom -p realtek_mst_i2c_spi:bus=0,enter-isp=0,reset-mcu=1 -w new.bin"
-.sp
+.SS
+.BR "lspcon_i2c_spi " programmer
+.IP
+This programmer supports SPI flash programming for chips attached to Parade
+Technologies DisplayPort-to-HDMI level shifter/protocol converters (LSPCONs).
+Communication to the SPI flash is tunneled through the LSPCON over I2C.
.SH EXAMPLES
To back up and update your BIOS, run
@@ -1535,8 +1546,8 @@
.B ogp
needs PCI configuration space read access and raw memory access.
.sp
-.B realtek_mst_i2c_spi
-needs userspace access to the selected I2C bus.
+.BR realtek_mst_i2c_spi " and " lspcon_i2c_spi
+need userspace access to the selected I2C bus.
.sp
On OpenBSD, you can obtain raw access permission by setting
.B "securelevel=-1"
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Gerrit-Change-Id: I9ccb9694fdea29e68f062cc049efc0204917a139
Gerrit-Change-Number: 63104
Gerrit-PatchSet: 3
Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org>
Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com>
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Gerrit-MessageType: merged
Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/63103 )
Change subject: flashrom.8.tmpl: document realtek_mst_i2c_spi
......................................................................
flashrom.8.tmpl: document realtek_mst_i2c_spi
This programmer was undocumented.
Signed-off-by: Peter Marheine <pmarheine(a)chromium.org>
Change-Id: Idde5a8de014fe84c4a472f8fbfd3562350997d39
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63103
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flashrom.8.tmpl
1 file changed, 45 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Edward O'Callaghan: Looks good to me, approved
Nikolai Artemiev: Looks good to me, but someone else must approve
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index 3e4bc5e..92dff68 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -393,6 +393,8 @@
.sp
.BR "* stlinkv3_spi" " (for SPI flash ROMs attached to STMicroelectronics STLINK V3 devices)"
.sp
+.BR "* realtek_mst_i2c_spi" " (for SPI flash ROMs attached to Realtek DisplayPort hubs accessible through I2C)"
+.sp
Some programmers have optional or mandatory parameters which are described
in detail in the
.B PROGRAMMER-SPECIFIC INFORMATION
@@ -1415,6 +1417,46 @@
If the passed frequency is not supported by the adapter the nearest lower
supported frequency will be used.
.SS
+.BR "realtek_mst_i2c_spi " programmer
+.IP
+This programmer supports SPI flash programming for chips attached to Realtek
+DisplayPort MST hubs, themselves accessed through I2C (tunneling SPI flash
+commands through the MST hub's I2C connection with the host).
+
+The I2C bus on which the hub is reachable must be specified by either a device
+path with the \fBdevpath\fP option:
+.sp
+.B " flashrom \-p realtek_mst_i2c_spi:devpath=/dev/i2c-8"
+.sp
+or by a bus number with the \fBbus\fP option, which implies a device path like
+/dev/i2c-N where N is the specified bus number:
+.sp
+.B " flashrom \-p realtek_mst_i2c_spi:bus=8"
+.TP
+.B In-system programming (ISP) mode
+.sp
+The \fBreset-mcu\fP and \fBenter-isp\fP options provide control over device
+mode changes, where each can be set to 0 or 1 to enable or disable the
+corresponding mode transition.
+
+\fBenter-isp\fP defaults to 1, and if enabled will issue commands to the MST
+hub when beginning operation to put it into ISP mode.
+
+\fBreset-mcu\fP defaults to 0, and if enabled will issue a reset command to
+the MST hub on programming completion, causing it to exit ISP mode and to
+reload its own firmware from flash.
+
+The hub must be in ISP mode for SPI flash access to be possible, so it is
+usually only useful to disable \fBenter-isp\fP if an earlier invocation avoided
+resetting it on completion. For instance, to erase the flash and
+rewrite it with the contents of a file without resetting in between (which
+could render it nonfunctional if attempting to load firmware from a blank
+flash):
+.sp
+.B " flashrom -p realtek_mst_i2c_spi:bus=0,enter-isp=1,reset-mcu=0 -E"
+.br
+.B " flashrom -p realtek_mst_i2c_spi:bus=0,enter-isp=0,reset-mcu=1 -w new.bin"
+.sp
.SH EXAMPLES
To back up and update your BIOS, run
@@ -1493,6 +1535,9 @@
.B ogp
needs PCI configuration space read access and raw memory access.
.sp
+.B realtek_mst_i2c_spi
+needs userspace access to the selected I2C bus.
+.sp
On OpenBSD, you can obtain raw access permission by setting
.B "securelevel=-1"
in
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Gerrit-Branch: master
Gerrit-Change-Id: Idde5a8de014fe84c4a472f8fbfd3562350997d39
Gerrit-Change-Number: 63103
Gerrit-PatchSet: 3
Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org>
Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com>
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Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62794 )
Change subject: flashrom.8.tmpl: Clarify man entries for -w/-v/-x
......................................................................
flashrom.8.tmpl: Clarify man entries for -w/-v/-x
This change adds follow up changes to the man page:
- Explain (-) argument for -w/-v operations
- Expand on region name handling of -x operation
Also updates cli_classic.c to match with --help output.
BUG=b:224364316
Change-Id: I0cba593da3926c8587027789f4e1e89a2329ca7f
Signed-off-by: Daniel Campello <campello(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62794
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
---
M cli_classic.c
M flashrom.8.tmpl
2 files changed, 13 insertions(+), 7 deletions(-)
Approvals:
build bot (Jenkins): Verified
Edward O'Callaghan: Looks good to me, approved
diff --git a/cli_classic.c b/cli_classic.c
index b3930d2..0b6e79c 100644
--- a/cli_classic.c
+++ b/cli_classic.c
@@ -47,9 +47,9 @@
printf(" -h | --help print this help text\n"
" -R | --version print version (release)\n"
" -r | --read <file> read flash and save to <file>\n"
- " -w | --write <file|-> write <file> or the content provided\n"
+ " -w | --write (<file>|-) write <file> or the content provided\n"
" on the standard input to flash\n"
- " -v | --verify <file|-> verify flash against <file>\n"
+ " -v | --verify (<file>|-) verify flash against <file>\n"
" or the content provided on the standard input\n"
" -E | --erase erase flash memory\n"
" -V | --verbose more verbose output\n"
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index fe2d9d6..3e4bc5e 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -82,11 +82,13 @@
.BR <file> .
If the file already exists, it will be overwritten.
.TP
-.B "\-w, \-\-write <file>"
+.B "\-w, \-\-write (<file>|-)"
Write
.B <file>
-into flash ROM. This will first automatically
-.B erase
+into flash ROM. If
+.B -
+is provided instead, contents will be read from stdin. This will first automatically
+ B erase
the chip, then write to it.
.sp
In the process the chip is also read several times. First an in-memory backup
@@ -124,16 +126,20 @@
.BR internal
programmer. It may be enabled by default in this case in the future.
.TP
-.B "\-v, \-\-verify <file>"
+.B "\-v, \-\-verify (<file>|-)"
Verify the flash ROM contents against the given
.BR <file> .
+If
+.BR -
+is provided instead, contents will be written to the stdout.
.TP
.B "\-E, \-\-erase"
Erase the flash ROM chip.
.TP
.B "\-x, \-\-extract"
Extract every region defined on the layout from flash ROM chip to a
-file with the same name as the extracted region.
+file with the same name as the extracted region (replacing spaces with
+underscores).
.TP
.B "\-V, \-\-verbose"
More verbose output. This option can be supplied multiple times
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I0cba593da3926c8587027789f4e1e89a2329ca7f
Gerrit-Change-Number: 62794
Gerrit-PatchSet: 6
Gerrit-Owner: Daniel Campello <campello(a)chromium.org>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Gerrit-MessageType: merged
Attention is currently required from: Felix Singer, Nico Huber, Light, Anastasia Klimchuk.
Hello build bot (Jenkins), Nico Huber, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62747
to look at the new patch set (#15).
Change subject: flashrom.c, sfdp.c: Initialize dynamically allocated memory using calloc
......................................................................
flashrom.c, sfdp.c: Initialize dynamically allocated memory using calloc
In flashrom_image_write variables curcontents and oldcontents are
dynamically allocated using malloc. These could remain uninitialized and
when later used in need_erase could result in undefined behaviour.
Similar reasoning for variables hbuf, hdrs, tbuf in function
prob_spi_sfdp.
So allocate them using calloc to initialize them to zeroes. Also, copy
"FLASHROM BUG!" to detect future bugs.
Change-Id: I6b9269129968fb3b55b0d2a2e384c8a1aeba43ab
Signed-off-by: Aarya Chaumal <aarya.chaumal(a)gmail.com>
---
M flashrom.c
M sfdp.c
2 files changed, 9 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/47/62747/15
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Gerrit-PatchSet: 15
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Gerrit-MessageType: newpatchset