March 2022 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: tests: use MOCK_FD instead of NON_ZERO
by Daniel Campello (Code Review) March 30, 2022

March 30, 2022

Attention is currently required from: Edward O'Callaghan. Daniel Campello has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63193 ) Change subject: tests: use MOCK_FD instead of NON_ZERO ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/63193/comment/be7f7b0e_d541c5e1 PS2, Line 19: Signed-off-by: Daniel Campello <campello(a)chromium.org> > Co-Author: Done in CB:63227 -- To view, visit https://review.coreboot.org/c/flashrom/+/63193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib6bac051852aea2465665a6fd669b7f5e3772985 Gerrit-Change-Number: 63193 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Campello <campello(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 21:46:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: tests: use MOCK_FD instead of NON_ZERO
by Daniel Campello (Code Review) March 30, 2022

March 30, 2022

Attention is currently required from: Daniel Campello. Hello build bot (Jenkins), Edward O'Callaghan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/63193 to look at the new patch set (#3). Change subject: tests: use MOCK_FD instead of NON_ZERO ...................................................................... tests: use MOCK_FD instead of NON_ZERO With this change the mocks are able to return a non-negative value for the file descriptor expected from open operations. This avoid issues with subsequent error checks of the form `if (fd < 0)` BUG=b:227404721 TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom BRANCH=none Signed-off-by: Daniel Campello <campello(a)chromium.org> Change-Id: Ib6bac051852aea2465665a6fd669b7f5e3772985 --- M tests/include/test.h M tests/lifecycle.c M tests/tests.c 3 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/63193/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/63193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib6bac051852aea2465665a6fd669b7f5e3772985 Gerrit-Change-Number: 63193 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Campello <campello(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daniel Campello <campello(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: ichspi: Add Jasper Lake support
by Edward O'Callaghan (Code Review) March 30, 2022

March 30, 2022

Attention is currently required from: Nico Huber, Edward O'Callaghan, Angel Pons. Hello Sam McNally, build bot (Jenkins), Subrata Banik, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/62282 to look at the new patch set (#8). Change subject: ichspi: Add Jasper Lake support ...................................................................... ichspi: Add Jasper Lake support Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Jasper Lake is the same as Elkhart Lake. BUG=b:221175960 TEST=dedede with `flashrom -p internal --flash-size`. ``` $ flashrom -VVV -p internal --ifd -i fd -i bios -r /tmp/filename.rom <snip> Enabling hardware sequencing by default for 100+ series PCH. OK. No board enable found matching coreboot IDs vendor="Google", model="Magolor". The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Chip identified: GD25Q127C/GD25Q128C Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB. There is only one partition containing the whole address space (0x000000 - 0xffffff). There are 4096 erase blocks with 4096 B each. Added layout entry 00000000 - 00ffffff named complete flash Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading Status register Block protection is disabled. Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset 'Jasper Lake'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00381000 - 00ffffff named bios Added layout entry 00001000 - 00380fff named me restore_power_management: Re-enabling power management. Using regions: "bios", "fd". Reading Status register Block protection is disabled. Reading flash... 0x381000-0xffffff:R Reading 13103104 bytes starting at 0x381000. 000000-0x0fff:R Reading 4096 bytes starting at 0x000000. done. restore_power_management: Re-enabling power management. SUCCESS Restoring PCI config space for 00:1f:5 reg 0xdc restore_power_management: Re-enabling power management. ``` Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M chipset_enable.c M ich_descriptors.c M ichspi.c M programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 5 files changed, 35 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/82/62282/8 -- To view, visit https://review.coreboot.org/c/flashrom/+/62282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d Gerrit-Change-Number: 62282 Gerrit-PatchSet: 8 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: tests: assert pathname and flags when calling open()
by Daniel Campello (Code Review) March 30, 2022

March 30, 2022

Daniel Campello has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/63227 ) Change subject: tests: assert pathname and flags when calling open() ...................................................................... tests: assert pathname and flags when calling open() With this change the wrappers for mock and friends are able to take an optional io_mock_open_state struct to assert expected pathnames and flags whenever an open operation is called. Based partially on https://review.coreboot.org/c/flashrom/+/62319/5 BUG=b:227404721,b:217629892,b:215255210 TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom BRANCH=none Signed-off-by: Daniel Campello <campello(a)chromium.org> Co-Author: Edward O'Callaghan <quasisec(a)google.com> Change-Id: Ib46ca5b854c8453ec02ae09f3151cd4d25f988eb --- M tests/io_mock.h M tests/lifecycle.c M tests/tests.c 3 files changed, 36 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/27/63227/1 diff --git a/tests/io_mock.h b/tests/io_mock.h index f8f75ad..5d9bd0d 100644 --- a/tests/io_mock.h +++ b/tests/io_mock.h @@ -60,6 +60,15 @@ /* Always return success for tests. */ #define S_ISREG(x) 0 +/* Maximum number of open to mock. */ +#define MAX_MOCK_OPEN 2 + +struct io_mock_open_state { + unsigned int noc; + const char *paths[MAX_MOCK_OPEN]; + int flags[MAX_MOCK_OPEN]; +}; + struct io_mock { void *state; @@ -105,6 +114,8 @@ size_t (*fread)(void *state, void *buf, size_t size, size_t len, FILE *fp); int (*fprintf)(void *state, FILE *fp, const char *fmt, va_list args); int (*fclose)(void *state, FILE *fp); + + struct io_mock_open_state *open_state; }; void io_mock_register(const struct io_mock *io); diff --git a/tests/lifecycle.c b/tests/lifecycle.c index c37f3b9..fe63883 100644 --- a/tests/lifecycle.c +++ b/tests/lifecycle.c @@ -370,13 +370,6 @@ #endif } -static int realtek_mst_open(void *state, const char *pathname, int flags) -{ - assert_string_equal(pathname, "/dev/i2c-254"); - assert_int_equal(flags & O_RDWR, O_RDWR); - return MOCK_FD; -} - static int realtek_mst_ioctl(void *state, int fd, unsigned long request, va_list args) { assert_int_equal(fd, MOCK_FD); @@ -406,11 +399,16 @@ void realtek_mst_basic_lifecycle_test_success(void **state) { #if CONFIG_REALTEK_MST_I2C_SPI == 1 + struct io_mock_open_state realtek_mst_open_state = { + .noc = 0, + .paths = {"/dev/i2c-254"}, + .flags = {O_RDWR}, + }; const struct io_mock realtek_mst_io = { - .open = realtek_mst_open, .ioctl = realtek_mst_ioctl, .read = realtek_mst_read, .write = realtek_mst_write, + .open_state = &realtek_mst_open_state, }; io_mock_register(&realtek_mst_io); diff --git a/tests/tests.c b/tests/tests.c index f32c14d..bfe8b91 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -74,28 +74,38 @@ return (uint8_t)mock(); } +static int wrap_open_and_friends(const char *pathname, int flags) +{ + if (get_io() && get_io()->open) + return get_io()->open(get_io()->state, pathname, flags); + if (get_io() && get_io()->open_state) { + struct io_mock_open_state *io_state = get_io()->open_state; + unsigned int open_state_flags; + assert_true(io_state->noc < MAX_MOCK_OPEN); + assert_string_equal(pathname, io_state->paths[io_state->noc]); + open_state_flags = io_state->flags[io_state->noc]; + assert_int_equal(flags & open_state_flags, open_state_flags); + io_state->noc++; // proceed to the next path upon next call. + } + return MOCK_FD; +} + int __wrap_open(const char *pathname, int flags) { LOG_ME; - if (get_io() && get_io()->open) - return get_io()->open(get_io()->state, pathname, flags); - return MOCK_FD; + return wrap_open_and_friends(pathname, flags); } int __wrap_open64(const char *pathname, int flags) { LOG_ME; - if (get_io() && get_io()->open) - return get_io()->open(get_io()->state, pathname, flags); - return MOCK_FD; + return wrap_open_and_friends(pathname, flags); } int __wrap___open64_2(const char *pathname, int flags) { LOG_ME; - if (get_io() && get_io()->open) - return get_io()->open(get_io()->state, pathname, flags); - return MOCK_FD; + return wrap_open_and_friends(pathname, flags); } int __wrap_ioctl(int fd, unsigned long int request, ...) -- To view, visit https://review.coreboot.org/c/flashrom/+/63227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib46ca5b854c8453ec02ae09f3151cd4d25f988eb Gerrit-Change-Number: 63227 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Campello <campello(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: tests: assert pathname and flags when calling open()
by Edward O'Callaghan (Code Review) March 30, 2022

March 30, 2022

Attention is currently required from: Daniel Campello. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63193 ) Change subject: tests: assert pathname and flags when calling open() ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/63193/comment/50af6ea3_b183ed98 PS2, Line 19: Signed-off-by: Daniel Campello <campello(a)chromium.org> Co-Author: -- To view, visit https://review.coreboot.org/c/flashrom/+/63193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib6bac051852aea2465665a6fd669b7f5e3772985 Gerrit-Change-Number: 63193 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Campello <campello(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daniel Campello <campello(a)chromium.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 21:20:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: ichspi: Add support for Meteor Lake
by Edward O'Callaghan (Code Review) March 30, 2022

March 30, 2022

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62783 ) Change subject: ichspi: Add support for Meteor Lake ...................................................................... ichspi: Add support for Meteor Lake This patch adds Meteor Lake support into flashrom. Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect the chipset when the CSSL (CPU Soft Strap Length) field default value (0x03) on Meteor Lake is the same as Elkhart Lake. BUG=b:224325352 TEST=Flashrom is able to detect MTL SPI DID and show chipset name as below: > flashrom --flash-name .... Found chipset "Intel Meteor Lake-P/M". .... > flashrom - internal --ifd -i fd -i bios -r /tmp/bios.rom .... Reading ich_descriptor... done. Assuming chipset 'Meteor Lake'. Using regions: "bios", "fd". Reading flash... done. SUCCESS Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I0a2ffe2ba8d96c90d89b77e0d8583d179ff02a75 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62783 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Reviewed-by: Sam McNally <sammc(a)google.com> --- M chipset_enable.c M ich_descriptors.c M ichspi.c M programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 5 files changed, 38 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Wonkyu Kim: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved Sam McNally: Looks good to me, approved diff --git a/chipset_enable.c b/chipset_enable.c index 1cb1700..b050f64 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -606,6 +606,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_ELKHART_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: @@ -711,6 +712,7 @@ break; case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: boot_straps = boot_straps_pch500; break; case CHIPSET_APOLLO_LAKE: @@ -744,6 +746,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: @@ -1002,6 +1005,11 @@ return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_600_SERIES_ALDER_POINT); } +static int enable_flash_mtl(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_METEOR_LAKE); +} + static int enable_flash_mcc(struct pci_dev *const dev, const char *const name) { return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE); @@ -2151,6 +2159,7 @@ {0x8086, 0x438b, B_S, DEP, "Intel", "HM570", enable_flash_pch500}, {0x8086, 0x54a4, B_S, DEP, "Intel", "Alder Lake-N", enable_flash_pch600}, {0x8086, 0x51a4, B_S, DEP, "Intel", "Alder Lake-P", enable_flash_pch600}, + {0x8086, 0x7e23, B_S, DEP, "Intel", "Meteor Lake-P/M", enable_flash_mtl}, #endif {0}, }; diff --git a/ich_descriptors.c b/ich_descriptors.c index 256224d..7c03499 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -47,6 +47,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_ELKHART_LAKE: return 16; case CHIPSET_100_SERIES_SUNRISE_POINT: @@ -74,6 +75,7 @@ case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_APOLLO_LAKE: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: if (cont->NM <= MAX_NUM_MASTERS) @@ -113,7 +115,7 @@ "8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg", "9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point", "C620 series Lewisburg", "300 series Cannon Point", "400 series Comet Point", - "500 series Tiger Point", "600 series Alder Point", "Apollo Lake", "Gemini Lake", "Elkhart Lake", + "500 series Tiger Point", "600 series Alder Point", "Meteor Lake", "Apollo Lake", "Gemini Lake", "Elkhart Lake", }; if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names)) cs = 0; @@ -209,6 +211,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: { @@ -304,6 +307,7 @@ return freq_str[2][value]; case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: return freq_str[3][value]; case CHIPSET_ELKHART_LAKE: return freq_str[4][value]; @@ -351,6 +355,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: @@ -476,7 +481,8 @@ cs == CHIPSET_300_SERIES_CANNON_POINT || cs == CHIPSET_400_SERIES_COMET_POINT || cs == CHIPSET_500_SERIES_TIGER_POINT || - cs == CHIPSET_600_SERIES_ALDER_POINT) { + cs == CHIPSET_600_SERIES_ALDER_POINT || + cs == CHIPSET_METEOR_LAKE) { const char *const master_names[] = { "BIOS", "ME", "GbE", "unknown", "EC", }; @@ -1039,8 +1045,12 @@ return CHIPSET_500_SERIES_TIGER_POINT; if (content->CSSL == 0x14) return CHIPSET_600_SERIES_ALDER_POINT; - if (content->CSSL == 0x03) - return CHIPSET_ELKHART_LAKE; + if (content->CSSL == 0x03) { + if (content->CSSO == 0x70) + return CHIPSET_METEOR_LAKE; + else + return CHIPSET_ELKHART_LAKE; + } msg_pwarn("Unknown flash descriptor, assuming 500 series compatibility.\n"); return CHIPSET_500_SERIES_TIGER_POINT; } @@ -1063,6 +1073,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: /* `freq_read` was repurposed, so can't check on it any more. */ @@ -1220,6 +1231,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: @@ -1260,6 +1272,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: diff --git a/ichspi.c b/ichspi.c index 9f45ec2..a377247 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1799,6 +1799,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: @@ -1836,6 +1837,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: @@ -1895,6 +1897,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: @@ -1973,6 +1976,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_BAYTRAIL: @@ -2010,6 +2014,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_600_SERIES_ALDER_POINT: + case CHIPSET_METEOR_LAKE: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: case CHIPSET_ELKHART_LAKE: @@ -2053,8 +2058,9 @@ if (ich_spi_mode == ich_auto && (ich_gen == CHIPSET_APOLLO_LAKE || ich_gen == CHIPSET_GEMINI_LAKE || - ich_gen == CHIPSET_ELKHART_LAKE)) { - msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Elkhart Lake.\n"); + ich_gen == CHIPSET_ELKHART_LAKE || + ich_gen == CHIPSET_METEOR_LAKE)) { + msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Elkhart/Meteor Lake.\n"); ich_spi_mode = ich_hwseq; } diff --git a/programmer.h b/programmer.h index c79422c..33cbcc7 100644 --- a/programmer.h +++ b/programmer.h @@ -352,6 +352,7 @@ CHIPSET_400_SERIES_COMET_POINT, CHIPSET_500_SERIES_TIGER_POINT, CHIPSET_600_SERIES_ALDER_POINT, + CHIPSET_METEOR_LAKE, CHIPSET_APOLLO_LAKE, CHIPSET_GEMINI_LAKE, CHIPSET_ELKHART_LAKE, diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 532a1fb..13a1897 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -128,6 +128,7 @@ "\t- \"silvermont\" for chipsets from Intel's Silvermont architecture (e.g. Bay Trail),\n" "\t- \"apollo\" for Intel's Apollo Lake SoC.\n" "\t- \"gemini\" for Intel's Gemini Lake SoC.\n" +"\t- \"meteor\" for Intel's Meteor Lake SoC.\n" "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" @@ -243,6 +244,8 @@ cs = CHIPSET_GEMINI_LAKE; else if (strcmp(csn, "elkhart") == 0) cs = CHIPSET_ELKHART_LAKE; + else if (strcmp(csn, "meteor") == 0) + cs = CHIPSET_METEOR_LAKE; } ret = read_ich_descriptors_from_dump(buf, len, &cs, &desc); -- To view, visit https://review.coreboot.org/c/flashrom/+/62783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0a2ffe2ba8d96c90d89b77e0d8583d179ff02a75 Gerrit-Change-Number: 62783 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: tests: assert pathname and flags when calling open()
by Daniel Campello (Code Review) March 30, 2022

March 30, 2022

Attention is currently required from: Daniel Campello. Hello build bot (Jenkins), Edward O'Callaghan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/63193 to look at the new patch set (#2). Change subject: tests: assert pathname and flags when calling open() ...................................................................... tests: assert pathname and flags when calling open() With this change the wrappers for mock and friends are able to take an optional io_mock_open_state struct to assert expected pathnames and flags whenever an open operation is called. Based partially on https://review.coreboot.org/c/flashrom/+/62319/5 BUG=b:227404721,b:217629892,b:215255210 TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom BRANCH=none Signed-off-by: Daniel Campello <campello(a)chromium.org> Change-Id: Ib6bac051852aea2465665a6fd669b7f5e3772985 --- M tests/include/test.h M tests/io_mock.h M tests/lifecycle.c M tests/tests.c 4 files changed, 41 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/63193/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/63193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib6bac051852aea2465665a6fd669b7f5e3772985 Gerrit-Change-Number: 63193 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Campello <campello(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daniel Campello <campello(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: tests/linux_mtd: Allow for checking open() calls
by Daniel Campello (Code Review) March 30, 2022

March 30, 2022

Attention is currently required from: Edward O'Callaghan. Daniel Campello has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62318 ) Change subject: tests/linux_mtd: Allow for checking open() calls ...................................................................... Patch Set 4: (1 comment) File tests/lifecycle.c: https://review.coreboot.org/c/flashrom/+/62318/comment/c52289a1_4e31d7ff PS4, Line 267: NULL I gather from this that open is actually not called here? -- To view, visit https://review.coreboot.org/c/flashrom/+/62318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I06e54c0bdc4f5320904e2ab6542345721f1ca370 Gerrit-Change-Number: 62318 Gerrit-PatchSet: 4 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Campello <campello(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 18:08:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: tests/linux_spi: Validate param file path
by Daniel Campello (Code Review) March 30, 2022

March 30, 2022

Attention is currently required from: Edward O'Callaghan, Anastasia Klimchuk. Daniel Campello has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62319 ) Change subject: tests/linux_spi: Validate param file path ...................................................................... Patch Set 5: (1 comment) File tests/wraps.c: https://review.coreboot.org/c/flashrom/+/62319/comment/0dff6c74_fc09ee98 PS5, Line 26: assert_int_equal(flags & io_state->flags, io_state->flags); flags may be different for each path -- To view, visit https://review.coreboot.org/c/flashrom/+/62319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If5d24c65f291c53a35509fea5d2f5b3fdb51c306 Gerrit-Change-Number: 62319 Gerrit-PatchSet: 5 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Daniel Campello <campello(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 17:20:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: linux_mtd: Allow to open parition by name
by Angel Pons (Code Review) March 30, 2022

March 30, 2022

Attention is currently required from: Nico Huber, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63135 ) Change subject: linux_mtd: Allow to open parition by name ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File linux_mtd.c: https://review.coreboot.org/c/flashrom/+/63135/comment/93542ace_f737251c PS1, Line 376: sysfs_path[32], device_name[32] > Copied from above function. I see, it looks rather arbitrary. -- To view, visit https://review.coreboot.org/c/flashrom/+/63135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I566b9809950cbf47fbb01ae89305641c4e259f68 Gerrit-Change-Number: 63135 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 30 Mar 2022 14:03:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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