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Change subject: tests/: Allow for file path validation
......................................................................
tests/: Allow for file path validation
BUG=b:217629892,b:215255210
TEST=`ninja test`.
Change-Id: I892fa1ecee26ebce9640893edbb228fa9aa7b0b6
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M tests/lifecycle.c
1 file changed, 34 insertions(+), 0 deletions(-)
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Change subject: tests/chips.c: Mock out open() for lock file
......................................................................
tests/chips.c: Mock out open() for lock file
Change-Id: I527a266233648b0eef11a89108e82d0a008eeb8d
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M tests/chip.c
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Hello build bot (Jenkins), Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
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Change subject: tests/realtek_mst: Allow test to check multiple paths
......................................................................
tests/realtek_mst: Allow test to check multiple paths
While working on writing file-based locking for flashrom
it was observed that the realtek_mst unit-test does not
check subsequent paths from the io_mock state tracker.
Add infrasture into the realtek_mst unit-test to allow
for subsequent path validation.
BUG=b:217629892,b:215255210
TEST=`ninja test`.
Change-Id: I80d5e1fc26ad9caf49a98a7671d069bbd8428045
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
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M tests/lifecycle.c
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Hello build bot (Jenkins), Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
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Change subject: tests/linux_mtd: Allow for checking open() calls
......................................................................
tests/linux_mtd: Allow for checking open() calls
BUG=b:217629892,b:215255210
TEST=`ninja test`.
Change-Id: I06e54c0bdc4f5320904e2ab6542345721f1ca370
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
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M tests/lifecycle.c
1 file changed, 17 insertions(+), 1 deletion(-)
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Hello build bot (Jenkins), Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: tests/linux_spi: Validate param file path
......................................................................
tests/linux_spi: Validate param file path
While working on writing file-based locking for flashrom
it was observed that the linux_spi unit-test does not
check subsequent paths from the io_mock state tracker.
Add infrasture into the linux_spi unit-test to allow
for subsequent path validation and improve coverage
while here of '/dev/null'.
BUG=b:217629892,b:215255210
TEST=`ninja test`.
Change-Id: If5d24c65f291c53a35509fea5d2f5b3fdb51c306
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M tests/lifecycle.c
M tests/meson.build
A tests/wraps.c
A tests/wraps.h
4 files changed, 70 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/19/62319/5
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62769 )
Change subject: spi: Call clear_spi_id_cache() before probing next chip
......................................................................
Patch Set 1: Code-Review-1
(1 comment)
Patchset:
PS1:
Hi David, what did you originally intend? I have nothing but git history to work off.
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Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/62768 )
Change subject: flashrom.8.tmpl: Add raiden_debug_spi doc entry
......................................................................
flashrom.8.tmpl: Add raiden_debug_spi doc entry
BUG=b:224358254
TEST=`man ./flashrom.8.tmpl`.
Change-Id: I186920006bdfcc7a9f89542f84b452dfc72b18e4
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M flashrom.8.tmpl
1 file changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/68/62768/1
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index fe2d9d6..d72ea01 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -358,6 +358,8 @@
.sp
.BR "* rayer_spi" " (for SPI flash ROMs attached to a parallel port by one of various cable types)"
.sp
+.BR "* raiden_debug_spi" " (for SPI flash ROMs attached to a ChromiumOS servo debug board)"
+.sp
.BR "* pony_spi" " (for SPI flash ROMs attached to a SI-Prog serial port "
bitbanging adapter)
.sp
@@ -1124,6 +1126,39 @@
The schematic of the Xilinx DLC 5 was published in
.URLB "http://www.xilinx.com/support/documentation/user_guides/xtp029.pdf" "a Xilinx user guide" .
.SS
+.BR "raiden_debug_spi " programmer
+.IP
+The target of the SPI flashing mux must be specified with the
+.B target
+parameter with the
+.sp
+.B " flashrom \-p raiden_debug_spi:target=[ec|ap]"
+.sp
+syntax where
+.B target
+is either the "EC" or "AP" SPI flash to program.
+.sp
+The default is to use the first available servo. You can use the optional
+.B serial
+parameter to specify the servo serial to use
+.sp
+.B " flashrom \-p raiden_debug_spi:serial=XXX"
+.sp
+syntax.
+.sp
+Allow for power to settle on the AP and EC flash devices using a default of 1-3ms.
+You can use the optional
+.B custom_rst
+parameter to specify the reset to use up to 10ms for from power on to the first write with
+.sp
+.B " flashrom \-p raiden_debug_spi:custom_rst=(true,false)"
+.sp
+syntax.
+.sp
+More information about the ChromiumOS servo hardware is available at
+.nh
+.URLB "https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/do…" "servo website" .
+.SS
.BR "pony_spi " programmer
.IP
The serial port (like /dev/ttyS0, /dev/ttyUSB0 on Linux or COM3 on windows) is
@@ -1453,6 +1488,9 @@
.B rayer_spi
needs raw I/O port access.
.sp
+.B raiden_debug_spi
+need access to the respective USB device via libusb API version 1.0.
+.sp
.BR satasii ", " nicintel ", " nicintel_eeprom " and " nicintel_spi
need PCI configuration space read access and raw memory access.
.sp
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59741 )
Change subject: tests: Add run_probe_lifecycle and add dummyflasher probe test
......................................................................
Patch Set 5:
(3 comments)
File tests/lifecycle.c:
https://review.coreboot.org/c/flashrom/+/59741/comment/c9ee987d_347d4baf
PS4, Line 28: = NULL
> No need to initialize *flashctx. This is done by flashrom_flash_probe.
Done
https://review.coreboot.org/c/flashrom/+/59741/comment/171d18f2_1aa79c1a
PS4, Line 34: flashrom_flash_release(flashctx); /* cleanup */
> > Or aborts `assert_int_equal` the test? […]
Yes, if `assert_int_equal` fails, this terminates the test. In that case `flashrom_flash_release` won't be executed.
Does it mean flashctx still needs to be checked before releasing? (I haven't changed anything yet).
Thanks!
https://review.coreboot.org/c/flashrom/+/59741/comment/b6cf8eb1_e9fbbcf3
PS4, Line 45: = NULL
> No need to initialize *flashprog. This is done by flashrom_programmer_init. […]
Done
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