Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/62783 )
Change subject: ichspi: Add support for Meteor Lake
......................................................................
ichspi: Add support for Meteor Lake
This patch adds Meteor Lake support into flashrom.
BUG=b:224325352
TEST=Flashrom is able to detect MTL SPI DID and show chipset name as below:
> flashrom --flash-name
....
Found chipset "Intel Meteor Lake-P/M".
....
Note: Meteor Lake doesn't have PCH die hence, dropped `_POINT` postfix from
the chipset name.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I0a2ffe2ba8d96c90d89b77e0d8583d179ff02a75
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M programmer.h
M util/ich_descriptors_tool/ich_descriptors_tool.c
5 files changed, 36 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/62783/1
diff --git a/chipset_enable.c b/chipset_enable.c
index ac9377b..fbe4700 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -606,6 +606,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_METEOR_LAKE:
case CHIPSET_ELKHART_LAKE:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
@@ -711,6 +712,7 @@
break;
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_METEOR_LAKE:
boot_straps = boot_straps_pch500;
break;
case CHIPSET_APOLLO_LAKE:
@@ -744,6 +746,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_METEOR_LAKE:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
@@ -1002,6 +1005,11 @@
return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_600_SERIES_ALDER_POINT);
}
+static int enable_flash_mtl(struct pci_dev *const dev, const char *const name)
+{
+ return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_METEOR_LAKE);
+}
+
static int enable_flash_mcc(struct pci_dev *const dev, const char *const name)
{
return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE);
@@ -2151,6 +2159,7 @@
{0x8086, 0x438b, B_S, DEP, "Intel", "HM570", enable_flash_pch500},
{0x8086, 0x54a4, B_S, DEP, "Intel", "Alder Lake-N", enable_flash_pch600},
{0x8086, 0x51a4, B_S, DEP, "Intel", "Alder Lake-P", enable_flash_pch600},
+ {0x8086, 0x7e23, B_S, DEP, "Intel", "Meteor Lake-P/M", enable_flash_mtl},
#endif
{0},
};
diff --git a/ich_descriptors.c b/ich_descriptors.c
index 256224d..c0560d6 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -47,6 +47,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_METEOR_LAKE:
case CHIPSET_ELKHART_LAKE:
return 16;
case CHIPSET_100_SERIES_SUNRISE_POINT:
@@ -74,6 +75,7 @@
case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_METEOR_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
if (cont->NM <= MAX_NUM_MASTERS)
@@ -209,6 +211,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_METEOR_LAKE:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE: {
@@ -304,6 +307,7 @@
return freq_str[2][value];
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_METEOR_LAKE:
return freq_str[3][value];
case CHIPSET_ELKHART_LAKE:
return freq_str[4][value];
@@ -351,6 +355,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_METEOR_LAKE:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
@@ -476,7 +481,8 @@
cs == CHIPSET_300_SERIES_CANNON_POINT ||
cs == CHIPSET_400_SERIES_COMET_POINT ||
cs == CHIPSET_500_SERIES_TIGER_POINT ||
- cs == CHIPSET_600_SERIES_ALDER_POINT) {
+ cs == CHIPSET_600_SERIES_ALDER_POINT ||
+ cs == CHIPSET_METEOR_LAKE) {
const char *const master_names[] = {
"BIOS", "ME", "GbE", "unknown", "EC",
};
@@ -1039,8 +1045,12 @@
return CHIPSET_500_SERIES_TIGER_POINT;
if (content->CSSL == 0x14)
return CHIPSET_600_SERIES_ALDER_POINT;
- if (content->CSSL == 0x03)
- return CHIPSET_ELKHART_LAKE;
+ if (content->CSSL == 0x03) {
+ if (content->CSSO == 0x70)
+ return CHIPSET_METEOR_LAKE;
+ else
+ return CHIPSET_ELKHART_LAKE;
+ }
msg_pwarn("Unknown flash descriptor, assuming 500 series compatibility.\n");
return CHIPSET_500_SERIES_TIGER_POINT;
}
@@ -1063,6 +1073,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_METEOR_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
/* `freq_read` was repurposed, so can't check on it any more. */
@@ -1220,6 +1231,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_METEOR_LAKE:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
@@ -1260,6 +1272,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_METEOR_LAKE:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
diff --git a/ichspi.c b/ichspi.c
index 9f45ec2..1ffb8e8 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1799,6 +1799,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_METEOR_LAKE:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
@@ -1836,6 +1837,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_METEOR_LAKE:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
@@ -1895,6 +1897,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_METEOR_LAKE:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
@@ -1973,6 +1976,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_METEOR_LAKE:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_BAYTRAIL:
@@ -2010,6 +2014,7 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_METEOR_LAKE:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
@@ -2053,8 +2058,9 @@
if (ich_spi_mode == ich_auto &&
(ich_gen == CHIPSET_APOLLO_LAKE ||
ich_gen == CHIPSET_GEMINI_LAKE ||
- ich_gen == CHIPSET_ELKHART_LAKE)) {
- msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Elkhart Lake.\n");
+ ich_gen == CHIPSET_ELKHART_LAKE ||
+ ich_gen == CHIPSET_METEOR_LAKE)) {
+ msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Elkhart/Meteor Lake.\n");
ich_spi_mode = ich_hwseq;
}
diff --git a/programmer.h b/programmer.h
index 6a0c3fa..e751079 100644
--- a/programmer.h
+++ b/programmer.h
@@ -354,6 +354,7 @@
CHIPSET_400_SERIES_COMET_POINT,
CHIPSET_500_SERIES_TIGER_POINT,
CHIPSET_600_SERIES_ALDER_POINT,
+ CHIPSET_METEOR_LAKE,
CHIPSET_APOLLO_LAKE,
CHIPSET_GEMINI_LAKE,
CHIPSET_ELKHART_LAKE,
diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c
index 532a1fb..dacc199 100644
--- a/util/ich_descriptors_tool/ich_descriptors_tool.c
+++ b/util/ich_descriptors_tool/ich_descriptors_tool.c
@@ -237,6 +237,8 @@
cs = CHIPSET_500_SERIES_TIGER_POINT;
else if (strcmp(csn, "600") == 0)
cs = CHIPSET_600_SERIES_ALDER_POINT;
+ else if (strcmp(csn, "meteor") == 0)
+ cs = CHIPSET_METEOR_LAKE;
else if (strcmp(csn, "apollo") == 0)
cs = CHIPSET_APOLLO_LAKE;
else if (strcmp(csn, "gemini") == 0)
--
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62761 )
Change subject: board_enable.c: Fix dead assignment
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS1:
> I don't this change should affect the logic in any way but still wondering why were there 2 assignme […]
Maybe INB has some side-effects, for example doing something and then the assignment happens.
Keith, Idwer, maybe you know about it? Thank you!
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62747 )
Change subject: flashrom.c, sfdp.c: Initialize dynamically allocated memory using calloc
......................................................................
Patch Set 5: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62747/comment/80514137_676b34e3
PS5, Line 13: So allocate them using calloc to initialize them to
: zeroes or if allocating using malloc separately initialize them using a loop.
Maybe separate this by two new lines, so that it will be easier to read?
Patchset:
PS5:
Angel, I have something in memory that you had a patch at some point to replace malloc with calloc? I don't remember what happened with that patch :) But looks like it was a good idea.
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62725 )
Change subject: libflashrom.c: Fix unintialized value passed to function
......................................................................
Patch Set 12: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62725/comment/41d1fe6f_e01d1cf6
PS12, Line 15: Signed-off-by: aarya <aarya.chaumal(a)gmail.com>
You need to remove this line, you have Signed-off-by tag already just above.
In general, you need real name in Signed-off-by so first line is correct.
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62724 )
Change subject: pony_spi.c: Fix memory leak in function pony_init_spi
......................................................................
Patch Set 7: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62724/comment/f304e532_cb8eef74
PS3, Line 11: ii
> Done
This seems to be still in the latest patchset? Still 2 ii in "deallocatiing".
Commit Message:
https://review.coreboot.org/c/flashrom/+/62724/comment/a7b6b27f_b5c169ec
PS7, Line 9: Memory leaked was caused
I think "Memory leak was caused" sounds better (memory leak instead of memory leaked).
Patchset:
PS7:
I have just 2 comments about commit message.
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62324 )
Change subject: tests/chips.c: Mock out open() for lock file
......................................................................
Patch Set 4:
(1 comment)
File tests/chip.c:
https://review.coreboot.org/c/flashrom/+/62324/comment/52967d81_68a5c88f
PS3, Line 189: #define DEFAULT_MOCK_FD 0xC0FE
> Whatever will be end result in CB:62319 ideally it can be reused here
Cleaned up now put consolidating this into a new wraps.c object introduced in commit#1
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Change subject: tests/linux_spi: Validate param file path
......................................................................
Patch Set 5:
(2 comments)
File tests/init_shutdown.c:
https://review.coreboot.org/c/flashrom/+/62319/comment/c7c33198_5c5390a8
PS4, Line 41: default_io_mock_state
> Ok, maybe multipath is not great name if it has a meaning already, let's think of other name. […]
I have rebased with 'fallback' instead. I would be inclined to move all the wrap implementations in tests.c to wraps.c but I didn't do that in this patch series yet.
https://review.coreboot.org/c/flashrom/+/62319/comment/2004c2d6_2c17fae9
PS4, Line 43: 2
> Yes, great idea to have it as define!
Done
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Hello Hung-Te Lin, build bot (Jenkins), Nico Huber, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62213
to look at the new patch set (#13).
Change subject: flashrom.c: Implement file-based locking semantics
......................................................................
flashrom.c: Implement file-based locking semantics
This upstreams the ChromiumOS implementation of file-based locking
for multiple instances of flashrom that could be spawned either
from libflashrom (perhaps by fwupd for example) and user cli
as another example. Since flashrom is programming singleton state
of hardware from userspace there is no way to exclusively own
the address space and therefore a file-based locking semantic
is considered here.
BUG=b:217629892,b:215255210
BRANCH=none
TEST=nm -gD /build/brya/usr/lib64/libflashrom.so | grep "flock"
Test futility update with multiple instances of flashrom running.
Change-Id: I19cb4e3bf14caeb67c3e8100a20395b264c5113a
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M Makefile
A big_lock.c
A big_lock.h
A file_lock.c
M flashrom.c
A ipc_lock.h
M meson.build
M tests/lifecycle.c
8 files changed, 452 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/13/62213/13
--
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I19cb4e3bf14caeb67c3e8100a20395b264c5113a
Gerrit-Change-Number: 62213
Gerrit-PatchSet: 13
Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Attention: Nico Huber <nico.h(a)gmx.de>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-MessageType: newpatchset