Peter Marheine has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/63103 )
Change subject: flashrom.8.tmpl: document realtek_mst_i2c_spi
......................................................................
flashrom.8.tmpl: document realtek_mst_i2c_spi
This programmer was undocumented.
Signed-off-by: Peter Marheine <pmarheine(a)chromium.org>
Change-Id: Idde5a8de014fe84c4a472f8fbfd3562350997d39
---
M flashrom.8.tmpl
1 file changed, 45 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/03/63103/1
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index fe2d9d6..a6637d2 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -387,6 +387,8 @@
.sp
.BR "* stlinkv3_spi" " (for SPI flash ROMs attached to STMicroelectronics STLINK V3 devices)"
.sp
+.BR "* realtek_mst_i2c_spi" " (for SPI flash ROMs attached to Realtek DisplayPort hubs accessible through I2C)"
+.sp
Some programmers have optional or mandatory parameters which are described
in detail in the
.B PROGRAMMER-SPECIFIC INFORMATION
@@ -1409,6 +1411,46 @@
If the passed frequency is not supported by the adapter the nearest lower
supported frequency will be used.
.SS
+.BR "realtek_mst_i2c_spi " programmer
+.IP
+This programmer supports SPI flash programming for chips attached to Realtek
+DisplayPort MST hubs, themselves accessed through I2C (tunneling SPI flash
+commands through the MST hub's I2C connection with the host).
+
+The I2C bus on which the hub is reachable must be specified by either a device
+path with the \fBdevpath\fP option:
+.sp
+.B " flashrom \-p realtek_mst_i2c_spi:devpath=/dev/i2c-8"
+.sp
+or by a bus number with the \fBbus\fP option, which implies a device path like
+/dev/i2c-N where N is the specified bus number:
+.sp
+.B " flashrom \-p realtek_mst_i2c_spi:bus=8"
+.TP
+.B In-system programming (ISP) mode
+.sp
+The \fBreset-mcu\fP and \fBenter-isp\fP options provide control over device
+mode changes, where each can be set to 0 or 1 to enable or disable the
+corresponding mode transition.
+
+\fBenter-isp\fP defaults to 1, and if enabled will issue commands to the MST
+hub when beginning operation to put it into ISP mode.
+
+\fBreset-mcu\fP defaults to 0, and if enabled will issue a reset command to
+the MST hub on programming completion, causing it to exit ISP mode and to
+reload its own firmware from flash.
+
+The hub must be in ISP mode for SPI flash access to be possible, so it is
+usually only useful to disable \fBenter-isp\fP if an earlier invocation avoided
+resetting it on completion. For instance, to erase the flash and
+rewrite it with the contents of a file without resetting in between (which
+could render it nonfunctional if attempting to load firmware from a blank
+flash):
+.sp
+.B " flashrom -p realtek_mst_i2c_spi:bus=0,enter-isp=1,reset-mcu=0 -E"
+.br
+.B " flashrom -p realtek_mst_i2c_spi:bus=0,enter-isp=0,reset-mcu=1 -w new.bin"
+.sp
.SH EXAMPLES
To back up and update your BIOS, run
@@ -1487,6 +1529,9 @@
.B ogp
needs PCI configuration space read access and raw memory access.
.sp
+.B realtek_mst_i2c_spi
+needs userspace access to the selected I2C bus.
+.sp
On OpenBSD, you can obtain raw access permission by setting
.B "securelevel=-1"
in
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62868 )
Change subject: ichspi: Introduce HSFC CYCLE READ/WRITE/ERASE macros
......................................................................
Patch Set 11:
(1 comment)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/62868/comment/5c9ff157_0c89b33c
PS11, Line 1511: erase
isn't this explicitly adding a "read" which was implicit before?
Also make it clear in the commit message that this was added to be explicit over it being implicit there.
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62891 )
Change subject: ichspi: Introduce FCYCLE_MASK(n) macro
......................................................................
Patch Set 6: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62891/comment/c26dcc3f_e65c5d68
PS3, Line 12: Also, drops unused macros (PCH100_HSFC_FCYCLE_OFF and
: PCH100_HSFC_FCYCLE).
> I am slightly confused, you said Ack but haven't changed anything? […]
`PCH100_HSFC_FCYCLE_OFF` and `PCH100_HSFC_FCYCLE` seem to no longer be used as to be replaced as is the patch. Therefore not sure why is getting split out here into a separate patch Anastasia?
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Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62724 )
Change subject: pony_spi.c: Fix memory leak in function pony_init_spi
......................................................................
pony_spi.c: Fix memory leak in function pony_init_spi
The issue was found by running scan-build. Memory leak was caused as
data variable wasn't deallocated in some error cases where the
function returned without deallocating it. After making the change, the
issue no longer appeared in scan-build.
Change-Id: I7910db94f63693e7f131836d4963e88cfdbec301
Signed-off-by: Aarya Chaumal <aarya.chaumal(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62724
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org>
---
M pony_spi.c
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, but someone else must approve
Felix Singer: Looks good to me, but someone else must approve
Anastasia Klimchuk: Looks good to me, approved
diff --git a/pony_spi.c b/pony_spi.c
index 86ef238..a3ac274 100644
--- a/pony_spi.c
+++ b/pony_spi.c
@@ -161,6 +161,7 @@
if (!have_device) {
msg_perr("Error: No valid device specified.\n"
"Use flashrom -p pony_spi:dev=/dev/device[,type=name]\n");
+ free(data);
return 1;
}
8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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