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Change subject: flashrom.c, sfdp.c: Initialize dynamically allocated memory using calloc
......................................................................
Patch Set 12:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62747/comment/779a76fd_4f8b23f6
PS9, Line 11: when later used in need_erase could result in undefined behaviour.
> Maybe intitializing them with zeroes using calloc and then onlycopying "flashrom bug!" once should b […]
That would depend much on the kind of bug we are trying to catch,
i.e. do we expect flashrom could accidentally write the first bytes
of a chip or accidentally write any bytes?
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Change subject: ich_descriptors.c: Assert unsigned types >=0 on to prevent underflow error
......................................................................
Patch Set 12:
(1 comment)
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/62764/comment/8a2a5728_fe226634
PS6, Line 507: assert(j >= 12);
> One difference that I see, is for Sunrise Point: `num_regions` is 10 (assigned at line 492 in curren […]
If `num_regions` is 10, the second loop never runs. This doesn't change
because `j = 12;` can only increase `j`.
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Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/63124 )
Change subject: flashchips.c: Fix voltage ranges for MX23L1654 and MX23L6454
......................................................................
flashchips.c: Fix voltage ranges for MX23L1654 and MX23L6454
An user reported incorrect voltage ranges for the following flash chips:
* MX23L1654
* MX23L6454
Currently, their low end is at 3.0V, while 2.7V is allowed according to
their datasheets. Thus, fix their voltage ranges.
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Change-Id: I91dd6058d5951868b154c8bc8818cb0c412f2499
---
M flashchips.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/24/63124/1
diff --git a/flashchips.c b/flashchips.c
index acb7718..806d010 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -8279,7 +8279,7 @@
.probe_timing = TIMING_ZERO,
.write = NULL, /* MX23L1654 is a mask ROM, so it is read-only */
.read = spi_chip_read, /* Fast read (0x0B) supported */
- .voltage = {3000, 3600},
+ .voltage = {2700, 3600},
},
{
@@ -8311,7 +8311,7 @@
.probe_timing = TIMING_ZERO,
.write = NULL, /* MX23L6454 is a mask ROM, so it is read-only */
.read = spi_chip_read, /* Fast read (0x0B) supported */
- .voltage = {3000, 3600},
+ .voltage = {2700, 3600},
},
{
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Change subject: ich_descriptors.c: Assert unsigned types >=0 on to prevent underflow error
......................................................................
Patch Set 12:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62764/comment/9496c0c9_d2e02f1e
PS12, Line 7: ich_descriptors.c: Assert unsigned types >=0 on to prevent underflow error
We need to fit this into 72 char, and it is 74 at the moment :)
First of all, the latest version does not assert anything, so maybe say "ensure" instead of "assert"?
Also maybe drop the last word (error). I think "to prevent underflow" is enough. And then it will fit into char limit.
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Change subject: ich_descriptors.c: Assert unsigned types >=0 on to prevent underflow error
......................................................................
Patch Set 12: Code-Review+1
(1 comment)
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/62764/comment/716ae958_c48dbf18
PS6, Line 507: assert(j >= 12);
> Yeah I am okay with making it explicit :)
One difference that I see, is for Sunrise Point: `num_regions` is 10 (assigned at line 492 in current patchset). So in initial version the loop starts with j=10, after this patch it starts with j=12.
I understand about underflow and undefined behaviour, looks like it's correct to start loop with j=12.
I am curious, what was printed for Sunrise Point for j=10,11 , was that printing garbage?
Otherwise, looks good! What do you think Nico?
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Change subject: board_enable.c: Remove unnecessary assignment
......................................................................
Patch Set 10: Code-Review+2
(1 comment)
Patchset:
PS10:
Keith, would you like your name added as Tested-by tag? (sorry I only now thought about it, should have asked earlier).
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Change subject: flashrom.8.tmpl: document lspcon_i2c_spi
......................................................................
Patch Set 1: Code-Review+2
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Change subject: flashchips.c: add writeprotect support for more chips
......................................................................
Patch Set 26:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62214/comment/2706778b_f4f909b7
PS26, Line 10: Chips I wasn't able to test were just
: checked against the datasheets.
> Could a EM100 be leveraged here?
I just tried it, it would have been a great way to test but it appears that SR2 commands are being intrepreted incorrectly, e.g.
0x35 should be read sr2 and 0x31 should be write sr2.
```
em100 -c GD25Q64 --stop -t --start`
...
0x35 - enter quad I/O mode
...
0x31 - unknown command
```
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