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Change subject: ichspi: Rename HSFC_FDBC -> HSFC_FDBC_MASK
......................................................................
Patch Set 5:
(1 comment)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/62894/comment/78c3765c_71be11b7
PS4, Line 508: FDBC
> I have one more question :)
>
> First argument in `_pprint_reg` is `bit` (not `reg` as it is for `pprint_reg`). So should it be FDBC instead of HSFC, since you are replacing one function with the other?
The first argument is to present the name of the register IMO (looking at line 499 and 504 as other usage of _pprint_reg macro) and this is how it works
#include <stdio.h>
#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
#define HSFC_FDBC_MASK (0x3f << HSFC_FDBC_OFF)
#define _pprint_reg(bit, mask, off, val, sep) printf("%s=%d" sep, #bit, (val & mask) >> off)
int main()
{
int reg_val = 0x1234;
_pprint_reg(HSFC, HSFC_FDBC_MASK, HSFC_FDBC_OFF, reg_val, ",");
return 0;
}
output:
HSFC=18,
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62891 )
Change subject: ichspi: Introduce FCYCLE_MASK(n) macro
......................................................................
Patch Set 5:
(3 comments)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/62891/comment/253b1618_839bf88c
PS5, Line 141: 2 bits
> Can you elaborate more than just saying 2 bits so to help the reader who may not have access to the […]
Ack
https://review.coreboot.org/c/flashrom/+/62891/comment/82648ad5_38b9cc2b
PS5, Line 143: 1-2: FLASH Cycle
> `1-n: FLASH Cycle`
Ack
https://review.coreboot.org/c/flashrom/+/62891/comment/537ffb33_a23279a1
PS5, Line 145: #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
> isn't this removable now since you would have […]
Ack
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Light has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62724 )
Change subject: pony_spi.c: Fix memory leak in function pony_init_spi
......................................................................
Patch Set 12:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62724/comment/dc1a5e46_74736271
PS10, Line 9: I found the issue
> nit (not blocking): The issue was found
Done
https://review.coreboot.org/c/flashrom/+/62724/comment/182ed1cf_3e7d5ec3
PS10, Line 11: changes
> change,
Done
https://review.coreboot.org/c/flashrom/+/62724/comment/93d2f556_e7f26e01
PS10, Line 12: was no longer appeared
> no longer appeared
Done
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Hello Felix Singer, build bot (Jenkins), Nico Huber, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
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Change subject: pony_spi.c: Fix memory leak in function pony_init_spi
......................................................................
pony_spi.c: Fix memory leak in function pony_init_spi
The issue was found by running scan-build. Memory leak was caused as
data variable wasn't deallocated in some error cases where the
function returned without deallocating it. After making the change, the
issue no longer appeared in scan-build.
Change-Id: I7910db94f63693e7f131836d4963e88cfdbec301
Signed-off-by: Aarya Chaumal <aarya.chaumal(a)gmail.com>
---
M pony_spi.c
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/24/62724/12
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Hello Felix Singer, build bot (Jenkins), Nico Huber, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62724
to look at the new patch set (#11).
Change subject: pony_spi.c: Fix memory leak in function pony_init_spi
......................................................................
pony_spi.c: Fix memory leak in function pony_init_spi
The issue was found by running scan-build. Memory leak was caused as
data variable wasn't deallocated in some error cases where the
function returned without deallocating it. After making the change the
issue no longer appeared in scan-build.
Change-Id: I7910db94f63693e7f131836d4963e88cfdbec301
Signed-off-by: Aarya Chaumal <aarya.chaumal(a)gmail.com>
---
M pony_spi.c
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/24/62724/11
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62867 )
Change subject: ichspi: Unify timeouts across all SPI operations to 30s
......................................................................
Patch Set 8:
(5 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/62867/comment/6ab39b98_320eb32d
PS7, Line 7: Unify timeout (30sec) across all SPI operations
> `Unify timeouts across all SPI operations to 30s`
Ack
https://review.coreboot.org/c/flashrom/+/62867/comment/5a571279_ff4276d2
PS7, Line 9: This patch removes taking `timeout` argument for different operations
: using `ich_hwseq_wait_for_cycle_complete()`. Make use of 30sec unified
: timeout for all SPI operations.
> ``` […]
Ack
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/62867/comment/9b7f44c7_15fb95f0
PS7, Line 31: multi-master accessing the
> `multi-mastering access of the`
Ack
https://review.coreboot.org/c/flashrom/+/62867/comment/9b25e11a_2bd69196
PS7, Line 31: might
> `may`
Ack
https://review.coreboot.org/c/flashrom/+/62867/comment/279839e7_a4627f4d
PS7, Line 36: it's impossible to know
: * the actual status of the SPI bus
> I thought that is the point of the `HSFS_SCIP` bit? The phrasing may need adjustment here to clarify […]
Done
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Subrata Banik has uploaded a new patch set (#8) to the change originally created by Subrata Banik. ( https://review.coreboot.org/c/flashrom/+/62867 )
Change subject: ichspi: Unify timeouts across all SPI operations to 30s
......................................................................
ichspi: Unify timeouts across all SPI operations to 30s
`ich_hwseq_wait_for_cycle_complete()` drops taking `timeout` as argument
in favor of a fixed timeout of `30 seconds` for any given SPI operation
as recommended by the SPI programming guide.
Document: Alder Lake-P Client Platform SPI Programming Guide
Rev 1.30 (supporting document for multi-master accessing the
SPI Flash device.)
BUG=b:223630977
TEST=Able to perform read/write/erase operation on PCH 600 series
chipset (board name: Brya).
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b
---
M ichspi.c
1 file changed, 46 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/67/62867/8
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62764 )
Change subject: ich_descriptors.c: Assert unsigned types >=0 on to prevent underflow error
......................................................................
Patch Set 9:
(1 comment)
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/62764/comment/7afa4898_7a89134a
PS6, Line 507: assert(j >= 12);
> I am not sure, are we using assert in code? I am wondering what other people think. […]
I had a similar thought on the patch around `writeprotect_ranges.c`. Such
an assertion would help scan-build. Not sure if it helps humans :)
In this instance, maybe just make it explicit:
for (j = 12; j < num_regions; ++j)
?
If we'd want `assert()` only for function contracts, we could also make
exceptions and comment, e.g.
assert(j >= 12); /* to help scan-build */
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