November 2022 - flashrom-gerrit

[S] Change in flashrom[1.3.x]: cli_classic.c: Be consistent with pointer types
by Felix Singer (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Edward O'Callaghan, Arthur Heymans, Anastasia Klimchuk. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69983 ) Change subject: cli_classic.c: Be consistent with pointer types ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: See CB:69995. Repushed the patches so that they are shown as cherry-picks. Sorry for the noise. -- To view, visit https://review.coreboot.org/c/flashrom/+/69983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I05dbda3923f1cd262bdad62e58f9c0ae7d7ffe6f Gerrit-Change-Number: 69983 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Sat, 26 Nov 2022 16:39:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in flashrom[1.3.x]: libpayload: Fix compiling bugs
by Felix Singer (Code Review) 26 Nov '22

26 Nov '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/70040 ) Change subject: libpayload: Fix compiling bugs ...................................................................... libpayload: Fix compiling bugs hwaccess_physmap.c: make `void *sys_physmap()` static hwaccess_x86_io.c: Add missing include Original-Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69831 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Original-Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Original-Reviewed-by: Nico Huber <nico.h(a)gmx.de> Original-Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I5062c5a62b90f7a189488f3f569dc357bd2cb85f Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M hwaccess_physmap.c M hwaccess_x86_io.c 2 files changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/70040/1 diff --git a/hwaccess_physmap.c b/hwaccess_physmap.c index 81adf18..f95b5f6 100644 --- a/hwaccess_physmap.c +++ b/hwaccess_physmap.c @@ -121,7 +121,7 @@ #define MEM_DEV "" -void *sys_physmap(uintptr_t phys_addr, size_t len) +static void *sys_physmap(uintptr_t phys_addr, size_t len) { return (void *)phys_to_virt(phys_addr); } diff --git a/hwaccess_x86_io.c b/hwaccess_x86_io.c index c3ad313..a883ed4 100644 --- a/hwaccess_x86_io.c +++ b/hwaccess_x86_io.c @@ -134,6 +134,8 @@ #endif #if defined(__LIBPAYLOAD__) +#include <arch/io.h> + #define IO_PORT_PERMISSION USE_DUMMY #define IO_PORT_FUNCTION USE_LIBC_TARGET_LAST #endif -- To view, visit https://review.coreboot.org/c/flashrom/+/70040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I5062c5a62b90f7a189488f3f569dc357bd2cb85f Gerrit-Change-Number: 70040 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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[M] Change in flashrom[1.3.x]: ichspi: Fix number of bytes for HW seq operations
by Felix Singer (Code Review) 26 Nov '22

26 Nov '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/70039 ) Change subject: ichspi: Fix number of bytes for HW seq operations ...................................................................... ichspi: Fix number of bytes for HW seq operations This patch fixes a potential issue where the SPI controller register HSFC.FDBC (bits 24-29) value gets incorrectly calculated while passing the `len` as `0` instead of `1`. As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f` represents 64-bytes to be transferred. The number of bytes transferred is the value of this field plus 1. If we would like to transfer 1 byte then we need to set `0b` in FDBC for operations like read, write, flash id as to account for the `set byte count` hence, the `len` argument should be `1`. Additionally, as per EDS, the FDBC field is ignored for any block erase command. BUG=b:258280679 TEST=Able to build flashrom and perform below operations on Google, Rex and Google, Kano/Taeko. During `--wp-disable` HW seq operation that requires 1 byte data transfer. HSFC.FDBC value while passing `len` as `0` = 0x3f (represents 64-byte) HSFC.FDBC value while passing `len` as `1` = 0x0 (represents 1-byte) Original-Signed-off-by: Subrata Banik <subratabanik(a)google.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69789 Original-Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Change-Id: I5b911655649c693e576497520687d7810bbd3c54 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M ichspi.c 1 file changed, 52 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/39/70039/1 diff --git a/ichspi.c b/ichspi.c index 29dcd25..dd5a2c1 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1360,6 +1360,12 @@ /* Set up transaction parameters. */ hsfc |= hsfc_cycle; + /* + * The number of bytes transferred is the value of `FDBC` plus 1, hence, + * subtracted 1 from the length field. + * As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f` + * represents 64-bytes to be transferred. + */ hsfc |= HSFC_FDBC_VAL(len - 1); hsfc |= HSFC_FGO; /* start */ prettyprint_ich9_reg_hsfc(hsfc, ich_generation); @@ -1399,7 +1405,7 @@ } msg_pdbg("Reading Status register\n"); - if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RD_STATUS, 0, len, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RD_STATUS, 1, len, ich_generation, hwseq_data->addr_mask)) { msg_perr("Reading Status register failed\n!!"); return -1; @@ -1422,7 +1428,7 @@ ich_fill_data(&value, len, ICH9_REG_FDATA0); - if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WR_STATUS, 0, len, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WR_STATUS, 1, len, ich_generation, hwseq_data->addr_mask)) { msg_perr("Writing Status register failed\n!!"); return -1; @@ -1518,7 +1524,7 @@ msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); - if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_BLOCK_ERASE, addr, 0, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_BLOCK_ERASE, addr, 1, ich_generation, hwseq_data->addr_mask)) return -1; return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/70039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I5b911655649c693e576497520687d7810bbd3c54 Gerrit-Change-Number: 70039 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[M] Change in flashrom[1.3.x]: ichspi: Clear Fast SPI HSFC register before HW seq operation
by Felix Singer (Code Review) 26 Nov '22

26 Nov '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69998 ) Change subject: ichspi: Clear Fast SPI HSFC register before HW seq operation ...................................................................... ichspi: Clear Fast SPI HSFC register before HW seq operation This patch fixes a regression introduced with commit 7ed1337309d3fe74f5af09520970f0f1d417399a (ichspi: Factor out common hwseq_xfer logic into helpers). The reason for the regression is ignoring the fact that the Fast SPI controller MMIO register HSFC (0x06) might not hold the default zero value before initiating the HW sequencing operation. Having a `1b` value in the HSFC.FDBC (bits 24-29) field would represent a byte that needs to be transfered. While debugging the regression, we have observed that the default value in the FDBC (prior to initiate any operation) is 0x3f (instead of zero) which represents 64-byte transfer. localhost ~ # iotools mmio_read32 0x92d16006 0x3f00 <Fast SPI MMIO BAR: 0x92d16000 and HSFC offset: 0x06> FDBC offset during `--wp-disable` operation represents higher numbers of bytes than the actual and eventually results in the error. Additionally, dropped unused variable (struct hwseq_data *hwseq_data). BUG=b:258280679 TEST=Able to build flashrom and perform below operations on Google, Rex and Google, Kano/Taeko. Without this patch: HSFC register value inside ich_start_hwseq_xfer() before initiating the HW seq operations: 0x3f00 HSFC register value inside ich_start_hwseq_xfer() during the HW seq operations (Read Status): 0x3f11 With this patch: HSFC register value inside ich_start_hwseq_xfer() before initiating the HW seq operations: 0x0 HSFC register value inside ich_start_hwseq_xfer() during the HW seq operations (Read Status): 0x11 Additionally, verified other HW sequencing operations (like read, write, erase, read status, write status, read ID) working fine without any error. Original-Signed-off-by: Subrata Banik <subratabanik(a)google.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69788 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> Change-Id: I4cc3f24f880d1d621f1f48a6e6b276449fa46f98 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M ichspi.c 1 file changed, 65 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/98/69998/1 diff --git a/ichspi.c b/ichspi.c index cd6e802..29dcd25 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1349,8 +1349,8 @@ uint32_t hsfc_cycle, uint32_t flash_addr, size_t len, uint32_t addr_mask) { - uint16_t hsfc; - struct hwseq_data *hwseq_data = get_hwseq_data_from_context(flash); + /* make sure HSFC register is cleared before initiate any operation */ + uint16_t hsfc = 0; /* Sets flash_addr in FADDR */ ich_hwseq_set_addr(flash_addr, addr_mask); @@ -1359,8 +1359,6 @@ REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); /* Set up transaction parameters. */ - hsfc = REGREAD16(ICH9_REG_HSFC); - hsfc &= ~hwseq_data->hsfc_fcycle; /* clear operation */ hsfc |= hsfc_cycle; hsfc |= HSFC_FDBC_VAL(len - 1); hsfc |= HSFC_FGO; /* start */ -- To view, visit https://review.coreboot.org/c/flashrom/+/69998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I4cc3f24f880d1d621f1f48a6e6b276449fa46f98 Gerrit-Change-Number: 69998 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in flashrom[1.3.x]: opaque_master: Mark Opaque chip as tested for WP
by Felix Singer (Code Review) 26 Nov '22

26 Nov '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69997 ) Change subject: opaque_master: Mark Opaque chip as tested for WP ...................................................................... opaque_master: Mark Opaque chip as tested for WP Opaque masters, by design, populate the flashchip structure during the execution of their probe function. Therefore any opaque master operation displays a message to the user: "This flash part has status UNTESTED for operations: WP". However, for all the other operations (read, write, erase) opaque masters always mark them as tested. Thus, align WP as marked tested inline with other opaque chip operations. BUG=b:258755442 TEST=the following does not display untested message: 1) flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE 2) flashrom -p internal (on Intel device) Original-Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69842 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Original-Reviewed-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Original-Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I5ae4cb49eb0abc6ab26cfe2f3359e4e50dd4fd4f Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M dummyflasher.c M ichspi.c M nicintel_eeprom.c 3 files changed, 35 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/97/69997/1 diff --git a/dummyflasher.c b/dummyflasher.c index 110a88c..35cdfef 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -145,7 +145,7 @@ msg_cdbg("%s: set flash->total_size to %dK bytes.\n", __func__, flash->chip->total_size); - flash->chip->tested = TEST_OK_PREW; + flash->chip->tested = TEST_OK_PREWB; if (emu_data->erase_to_zero) flash->chip->feature_bits |= FEATURE_ERASED_ZERO; diff --git a/ichspi.c b/ichspi.c index b3beaea..cd6e802 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1485,7 +1485,7 @@ msg_cdbg("In that range are %d erase blocks with %d B each.\n", size_high / erase_size_high, erase_size_high); } - flash->chip->tested = TEST_OK_PREW; + flash->chip->tested = TEST_OK_PREWB; return 1; } diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index ff2c3ce..4d5ab6b 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -115,7 +115,7 @@ /* Emulated eeprom has a fixed size of 4 KB */ flash->chip->total_size = 4; flash->chip->page_size = flash->chip->total_size * 1024; - flash->chip->tested = TEST_OK_PREW; + flash->chip->tested = TEST_OK_PREWB; flash->chip->gran = write_gran_1byte_implicit_erase; flash->chip->block_erasers->eraseblocks[0].size = flash->chip->page_size; flash->chip->block_erasers->eraseblocks[0].count = 1; @@ -146,7 +146,7 @@ } flash->chip->page_size = EE_PAGE_MASK + 1; - flash->chip->tested = TEST_OK_PREW; + flash->chip->tested = TEST_OK_PREWB; flash->chip->gran = write_gran_1byte_implicit_erase; flash->chip->block_erasers->eraseblocks[0].size = (EE_PAGE_MASK + 1); flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (EE_PAGE_MASK + 1); -- To view, visit https://review.coreboot.org/c/flashrom/+/69997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I5ae4cb49eb0abc6ab26cfe2f3359e4e50dd4fd4f Gerrit-Change-Number: 69997 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in flashrom[1.3.x]: linux_mtd: Mark Opaque chip as tested for WP
by Felix Singer (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Nikolai Artemiev. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69996 ) Change subject: linux_mtd: Mark Opaque chip as tested for WP ...................................................................... linux_mtd: Mark Opaque chip as tested for WP Since linux_mtd supports write-protect, its probe function needs to mark Opaque chip as tested for WP. Programmers which are opaque masters are responsible for populating flashchip#tested struct in probe function. Without the patch, any operation running via linux_mtd displays a message "This flash part has status UNTESTED for operations: WP". With the patch, the message is not displayed anymore. BUG=b:258755442 BRANCH=none TEST=flashrom -p host on ARM dut Found Programmer flash chip "Opaque flash chip" (8192 kB, Programmer-specific) on host. No operations were specified. Original-Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69518 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Original-Reviewed-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Change-Id: Icc0521c28555a93f26ce66bdbeaa68590f10c358 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M linux_mtd.c 1 file changed, 33 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/69996/1 diff --git a/linux_mtd.c b/linux_mtd.c index 5a1360e..c49b14a 100644 --- a/linux_mtd.c +++ b/linux_mtd.c @@ -179,7 +179,7 @@ if (data->no_erase) flash->chip->feature_bits |= FEATURE_NO_ERASE; - flash->chip->tested = TEST_OK_PREW; + flash->chip->tested = TEST_OK_PREWB; flash->chip->total_size = data->total_size / 1024; /* bytes -> kB */ flash->chip->block_erasers[0].eraseblocks[0].size = data->erasesize; flash->chip->block_erasers[0].eraseblocks[0].count = -- To view, visit https://review.coreboot.org/c/flashrom/+/69996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: Icc0521c28555a93f26ce66bdbeaa68590f10c358 Gerrit-Change-Number: 69996 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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[S] Change in flashrom[1.3.x]: cli_classic.c: Be consistent with pointer types
by Felix Singer (Code Review) 26 Nov '22

26 Nov '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69995 ) Change subject: cli_classic.c: Be consistent with pointer types ...................................................................... cli_classic.c: Be consistent with pointer types With `i586-pc-msdosdjgpp-gcc (GCC) 12.2.0`, `uint32_t` is defined as `long unsigned int`, which is not the same as `unsigned int`. As the `flashrom_layout_get_region_range()` function is part of libflashrom API, adjust `cli_classic.c` instead to avoid type mismatches. Original-Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69451 Original-Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Original-Reviewed-by: Evan Benn <evanbenn(a)google.com> Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Change-Id: Ie8f5bc0d9296f7c6b8f8a351b53052f5fe86b09d Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M cli_classic.c 1 file changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/69995/1 diff --git a/cli_classic.c b/cli_classic.c index a77422e..4649c73 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -126,7 +126,7 @@ return true; } -static int parse_wp_range(uint32_t *start, uint32_t *len) +static int parse_wp_range(unsigned int *start, unsigned int *len) { char *endptr = NULL, *token = NULL; @@ -568,7 +568,7 @@ int namelen, opt, i, j; int startchip = -1, chipcount = 0, option_index = 0; int operation_specified = 0; - uint32_t wp_start = 0, wp_len = 0; + unsigned int wp_start = 0, wp_len = 0; bool force = false, ifd = false, fmap = false; #if CONFIG_PRINT_WIKI == 1 bool list_supported_wiki = false; -- To view, visit https://review.coreboot.org/c/flashrom/+/69995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: Ie8f5bc0d9296f7c6b8f8a351b53052f5fe86b09d Gerrit-Change-Number: 69995 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in flashrom[1.3.x]: libpayload: Fix compiling bugs
by Felix Singer (Code Review) 26 Nov '22

26 Nov '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69994 ) Change subject: libpayload: Fix compiling bugs ...................................................................... libpayload: Fix compiling bugs hwaccess_physmap.c: make `void *sys_physmap()` static hwaccess_x86_io.c: Add missing include Change-Id: I5062c5a62b90f7a189488f3f569dc357bd2cb85f Original-Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69831 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Original-Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Original-Reviewed-by: Nico Huber <nico.h(a)gmx.de> Original-Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I7c4b28aaa79bc667c65c283e2481c846165bb8c9 --- M hwaccess_physmap.c M hwaccess_x86_io.c 2 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/69994/1 diff --git a/hwaccess_physmap.c b/hwaccess_physmap.c index 81adf18..f95b5f6 100644 --- a/hwaccess_physmap.c +++ b/hwaccess_physmap.c @@ -121,7 +121,7 @@ #define MEM_DEV "" -void *sys_physmap(uintptr_t phys_addr, size_t len) +static void *sys_physmap(uintptr_t phys_addr, size_t len) { return (void *)phys_to_virt(phys_addr); } diff --git a/hwaccess_x86_io.c b/hwaccess_x86_io.c index c3ad313..a883ed4 100644 --- a/hwaccess_x86_io.c +++ b/hwaccess_x86_io.c @@ -134,6 +134,8 @@ #endif #if defined(__LIBPAYLOAD__) +#include <arch/io.h> + #define IO_PORT_PERMISSION USE_DUMMY #define IO_PORT_FUNCTION USE_LIBC_TARGET_LAST #endif -- To view, visit https://review.coreboot.org/c/flashrom/+/69994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I7c4b28aaa79bc667c65c283e2481c846165bb8c9 Gerrit-Change-Number: 69994 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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[M] Change in flashrom[1.3.x]: ichspi: Fix number of bytes for HW seq operations
by Felix Singer (Code Review) 26 Nov '22

26 Nov '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69993 ) Change subject: ichspi: Fix number of bytes for HW seq operations ...................................................................... ichspi: Fix number of bytes for HW seq operations This patch fixes a potential issue where the SPI controller register HSFC.FDBC (bits 24-29) value gets incorrectly calculated while passing the `len` as `0` instead of `1`. As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f` represents 64-bytes to be transferred. The number of bytes transferred is the value of this field plus 1. If we would like to transfer 1 byte then we need to set `0b` in FDBC for operations like read, write, flash id as to account for the `set byte count` hence, the `len` argument should be `1`. Additionally, as per EDS, the FDBC field is ignored for any block erase command. BUG=b:258280679 TEST=Able to build flashrom and perform below operations on Google, Rex and Google, Kano/Taeko. During `--wp-disable` HW seq operation that requires 1 byte data transfer. HSFC.FDBC value while passing `len` as `0` = 0x3f (represents 64-byte) HSFC.FDBC value while passing `len` as `1` = 0x0 (represents 1-byte) Change-Id: I5b911655649c693e576497520687d7810bbd3c54 Original-Signed-off-by: Subrata Banik <subratabanik(a)google.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69789 Original-Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I4f39984f41c385686e816d81d6c53bf9b629f43f --- M ichspi.c 1 file changed, 53 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/69993/1 diff --git a/ichspi.c b/ichspi.c index 29dcd25..dd5a2c1 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1360,6 +1360,12 @@ /* Set up transaction parameters. */ hsfc |= hsfc_cycle; + /* + * The number of bytes transferred is the value of `FDBC` plus 1, hence, + * subtracted 1 from the length field. + * As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f` + * represents 64-bytes to be transferred. + */ hsfc |= HSFC_FDBC_VAL(len - 1); hsfc |= HSFC_FGO; /* start */ prettyprint_ich9_reg_hsfc(hsfc, ich_generation); @@ -1399,7 +1405,7 @@ } msg_pdbg("Reading Status register\n"); - if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RD_STATUS, 0, len, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RD_STATUS, 1, len, ich_generation, hwseq_data->addr_mask)) { msg_perr("Reading Status register failed\n!!"); return -1; @@ -1422,7 +1428,7 @@ ich_fill_data(&value, len, ICH9_REG_FDATA0); - if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WR_STATUS, 0, len, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WR_STATUS, 1, len, ich_generation, hwseq_data->addr_mask)) { msg_perr("Writing Status register failed\n!!"); return -1; @@ -1518,7 +1524,7 @@ msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); - if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_BLOCK_ERASE, addr, 0, ich_generation, + if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_BLOCK_ERASE, addr, 1, ich_generation, hwseq_data->addr_mask)) return -1; return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/69993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I4f39984f41c385686e816d81d6c53bf9b629f43f Gerrit-Change-Number: 69993 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[M] Change in flashrom[1.3.x]: ichspi: Clear Fast SPI HSFC register before HW seq operation
by Felix Singer (Code Review) 26 Nov '22

26 Nov '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69992 ) Change subject: ichspi: Clear Fast SPI HSFC register before HW seq operation ...................................................................... ichspi: Clear Fast SPI HSFC register before HW seq operation This patch fixes a regression introduced with commit 7ed1337309d3fe74f5af09520970f0f1d417399a (ichspi: Factor out common hwseq_xfer logic into helpers). The reason for the regression is ignoring the fact that the Fast SPI controller MMIO register HSFC (0x06) might not hold the default zero value before initiating the HW sequencing operation. Having a `1b` value in the HSFC.FDBC (bits 24-29) field would represent a byte that needs to be transfered. While debugging the regression, we have observed that the default value in the FDBC (prior to initiate any operation) is 0x3f (instead of zero) which represents 64-byte transfer. localhost ~ # iotools mmio_read32 0x92d16006 0x3f00 <Fast SPI MMIO BAR: 0x92d16000 and HSFC offset: 0x06> FDBC offset during `--wp-disable` operation represents higher numbers of bytes than the actual and eventually results in the error. Additionally, dropped unused variable (struct hwseq_data *hwseq_data). BUG=b:258280679 TEST=Able to build flashrom and perform below operations on Google, Rex and Google, Kano/Taeko. Without this patch: HSFC register value inside ich_start_hwseq_xfer() before initiating the HW seq operations: 0x3f00 HSFC register value inside ich_start_hwseq_xfer() during the HW seq operations (Read Status): 0x3f11 With this patch: HSFC register value inside ich_start_hwseq_xfer() before initiating the HW seq operations: 0x0 HSFC register value inside ich_start_hwseq_xfer() during the HW seq operations (Read Status): 0x11 Additionally, verified other HW sequencing operations (like read, write, erase, read status, write status, read ID) working fine without any error. Change-Id: I4cc3f24f880d1d621f1f48a6e6b276449fa46f98 Original-Signed-off-by: Subrata Banik <subratabanik(a)google.com> Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69788 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I086750f8bbdc0c95c4c067412b9b3d23fecdbe9d --- M ichspi.c 1 file changed, 66 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/92/69992/1 diff --git a/ichspi.c b/ichspi.c index cd6e802..29dcd25 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1349,8 +1349,8 @@ uint32_t hsfc_cycle, uint32_t flash_addr, size_t len, uint32_t addr_mask) { - uint16_t hsfc; - struct hwseq_data *hwseq_data = get_hwseq_data_from_context(flash); + /* make sure HSFC register is cleared before initiate any operation */ + uint16_t hsfc = 0; /* Sets flash_addr in FADDR */ ich_hwseq_set_addr(flash_addr, addr_mask); @@ -1359,8 +1359,6 @@ REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); /* Set up transaction parameters. */ - hsfc = REGREAD16(ICH9_REG_HSFC); - hsfc &= ~hwseq_data->hsfc_fcycle; /* clear operation */ hsfc |= hsfc_cycle; hsfc |= HSFC_FDBC_VAL(len - 1); hsfc |= HSFC_FGO; /* start */ -- To view, visit https://review.coreboot.org/c/flashrom/+/69992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I086750f8bbdc0c95c4c067412b9b3d23fecdbe9d Gerrit-Change-Number: 69992 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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