Attention is currently required from: Edward O'Callaghan.
Hello build bot (Jenkins), Edward O'Callaghan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/68153
to look at the new patch set (#3).
Change subject: libflashrom.c: Invert if conditions to improve the readability
......................................................................
libflashrom.c: Invert if conditions to improve the readability
Invert some if conditions to improve the readability of the code.
Instead of running some code if the specific condition applies, error
out early and reduce the indentation levels.
Change-Id: I4021d8802cd041dcca29a226af0798ebd9c5a81b
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M libflashrom.c
1 file changed, 50 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/53/68153/3
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I4021d8802cd041dcca29a226af0798ebd9c5a81b
Gerrit-Change-Number: 68153
Gerrit-PatchSet: 3
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68153 )
Change subject: libflashrom.c: Invert if conditions to improve the readability
......................................................................
Set Ready For Review
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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I4021d8802cd041dcca29a226af0798ebd9c5a81b
Gerrit-Change-Number: 68153
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Sat, 26 Nov 2022 04:14:06 +0000
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/69987
to look at the new patch set (#2).
Change subject: ichspi: Fix number of bytes for HW seq operations
......................................................................
ichspi: Fix number of bytes for HW seq operations
This patch fixes a potential issue where the SPI controller register
HSFC.FDBC (bits 24-29) value gets incorrectly calculated while passing
the `len` as `0` instead of `1`.
As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f`
represents 64-bytes to be transferred. The number of bytes
transferred is the value of this field plus 1.
If we would like to transfer 1 byte then we need to set `0b` in
FDBC for operations like read, write, flash id as to account for
the `set byte count` hence, the `len` argument should be `1`.
Additionally, as per EDS, the FDBC field is ignored for any block
erase command.
BUG=b:258280679
TEST=Able to build flashrom and perform below operations on Google,
Rex and Google, Kano/Taeko.
During `--wp-disable` HW seq operation that requires 1 byte data
transfer.
HSFC.FDBC value while passing `len` as `0` = 0x3f (represents 64-byte)
HSFC.FDBC value while passing `len` as `1` = 0x0 (represents 1-byte)
Original-Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Original-Change-Id: I5b911655649c693e576497520687d7810bbd3c54
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69789
Original-Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com>
Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Change-Id: Id54cb06bc66e86f95ea652ee604715e8969bcb02
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M ichspi.c
1 file changed, 53 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/87/69987/2
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Gerrit-Change-Id: Id54cb06bc66e86f95ea652ee604715e8969bcb02
Gerrit-Change-Number: 69987
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Gerrit-MessageType: newpatchset
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/69986
to look at the new patch set (#2).
Change subject: ichspi: Clear Fast SPI HSFC register before HW seq operation
......................................................................
ichspi: Clear Fast SPI HSFC register before HW seq operation
This patch fixes a regression introduced with
commit 7ed1337309d3fe74f5af09520970f0f1d417399a (ichspi: Factor out
common hwseq_xfer logic into helpers).
The reason for the regression is ignoring the fact that the Fast SPI
controller MMIO register HSFC (0x06) might not hold the default zero
value before initiating the HW sequencing operation.
Having a `1b` value in the HSFC.FDBC (bits 24-29) field would represent
a byte that needs to be transfered.
While debugging the regression, we have observed that the default value
in the FDBC (prior to initiate any operation) is 0x3f (instead of
zero) which represents 64-byte transfer.
localhost ~ # iotools mmio_read32 0x92d16006
0x3f00
<Fast SPI MMIO BAR: 0x92d16000 and HSFC offset: 0x06>
FDBC offset during `--wp-disable` operation represents higher numbers of
bytes than the actual and eventually results in the error.
Additionally, dropped unused variable (struct hwseq_data *hwseq_data).
BUG=b:258280679
TEST=Able to build flashrom and perform below operations on Google, Rex
and Google, Kano/Taeko.
Without this patch:
HSFC register value inside ich_start_hwseq_xfer() before initiating
the HW seq operations: 0x3f00
HSFC register value inside ich_start_hwseq_xfer() during the HW seq
operations (Read Status): 0x3f11
With this patch:
HSFC register value inside ich_start_hwseq_xfer() before initiating
the HW seq operations: 0x0
HSFC register value inside ich_start_hwseq_xfer() during the HW seq
operations (Read Status): 0x11
Additionally, verified other HW sequencing operations (like read, write,
erase, read status, write status, read ID) working fine without any
error.
Original-Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Original-Change-Id: I4cc3f24f880d1d621f1f48a6e6b276449fa46f98
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69788
Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com>
Change-Id: I1b77e563f67ad2793983b65e694be60c85f126c0
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M ichspi.c
1 file changed, 66 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/86/69986/2
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Gerrit-Branch: 1.3.x
Gerrit-Change-Id: I1b77e563f67ad2793983b65e694be60c85f126c0
Gerrit-Change-Number: 69986
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Subrata Banik <subratabanik(a)google.com>
Gerrit-MessageType: newpatchset
Attention is currently required from: Thomas Heijligen, Edward O'Callaghan.
Hello build bot (Jenkins), Thomas Heijligen, Edward O'Callaghan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/69985
to look at the new patch set (#2).
Change subject: opaque_master: Mark Opaque chip as tested for WP
......................................................................
opaque_master: Mark Opaque chip as tested for WP
Opaque masters, by design, populate the flashchip structure during
the execution of their probe function. Therefore any opaque master
operation displays a message to the user:
"This flash part has status UNTESTED for operations: WP".
However, for all the other operations (read, write, erase) opaque
masters always mark them as tested. Thus, align WP as marked tested
inline with other opaque chip operations.
BUG=b:258755442
TEST=the following does not display untested message:
1) flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE
2) flashrom -p internal (on Intel device)
Original-Change-Id: I5ae4cb49eb0abc6ab26cfe2f3359e4e50dd4fd4f
Original-Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69842
Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Original-Reviewed-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
Original-Reviewed-by: Felix Singer <felixsinger(a)posteo.net>
Change-Id: Iaef2026a9e06a823ab481853b520022ba83b1ca1
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M dummyflasher.c
M ichspi.c
M nicintel_eeprom.c
3 files changed, 36 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/85/69985/2
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Gerrit-Change-Id: Iaef2026a9e06a823ab481853b520022ba83b1ca1
Gerrit-Change-Number: 69985
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org>
Gerrit-Attention: Thomas Heijligen <src(a)posteo.de>
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Gerrit-MessageType: newpatchset
Attention is currently required from: Edward O'Callaghan, Nikolai Artemiev.
Hello build bot (Jenkins), Edward O'Callaghan, Anastasia Klimchuk, Nikolai Artemiev,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/69984
to look at the new patch set (#2).
Change subject: linux_mtd: Mark Opaque chip as tested for WP
......................................................................
linux_mtd: Mark Opaque chip as tested for WP
Since linux_mtd supports write-protect, its probe function needs
to mark Opaque chip as tested for WP. Programmers which are
opaque masters are responsible for populating flashchip#tested
struct in probe function.
Without the patch, any operation running via linux_mtd displays
a message "This flash part has status UNTESTED for operations: WP".
With the patch, the message is not displayed anymore.
BUG=b:258755442
BRANCH=none
TEST=flashrom -p host on ARM dut
Found Programmer flash chip "Opaque flash chip"
(8192 kB, Programmer-specific) on host.
No operations were specified.
Original-Change-Id: Icc0521c28555a93f26ce66bdbeaa68590f10c358
Original-Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69518
Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Original-Reviewed-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
Change-Id: I2740e75c974538ddae9f5b17dc4fba9a3101cbb3
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M linux_mtd.c
1 file changed, 34 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/84/69984/2
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Gerrit-Change-Id: I2740e75c974538ddae9f5b17dc4fba9a3101cbb3
Gerrit-Change-Number: 69984
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org>
Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Gerrit-MessageType: newpatchset
Attention is currently required from: Edward O'Callaghan, Anastasia Klimchuk.
Hello build bot (Jenkins), Edward O'Callaghan, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/69983
to look at the new patch set (#2).
Change subject: cli_classic.c: Be consistent with pointer types
......................................................................
cli_classic.c: Be consistent with pointer types
With `i586-pc-msdosdjgpp-gcc (GCC) 12.2.0`, `uint32_t` is defined as
`long unsigned int`, which is not the same as `unsigned int`. As the
`flashrom_layout_get_region_range()` function is part of libflashrom
API, adjust `cli_classic.c` instead to avoid type mismatches.
Original-Change-Id: Ie8f5bc0d9296f7c6b8f8a351b53052f5fe86b09d
Original-Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69451
Original-Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Original-Reviewed-by: Evan Benn <evanbenn(a)google.com>
Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com>
Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Change-Id: I05dbda3923f1cd262bdad62e58f9c0ae7d7ffe6f
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M cli_classic.c
1 file changed, 25 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/69983/2
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Gerrit-Change-Id: I05dbda3923f1cd262bdad62e58f9c0ae7d7ffe6f
Gerrit-Change-Number: 69983
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org>
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Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com>
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Gerrit-MessageType: newpatchset
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69987 )
Change subject: ichspi: Fix number of bytes for HW seq operations
......................................................................
ichspi: Fix number of bytes for HW seq operations
This patch fixes a potential issue where the SPI controller register
HSFC.FDBC (bits 24-29) value gets incorrectly calculated while passing
the `len` as `0` instead of `1`.
As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f`
represents 64-bytes to be transferred. The number of bytes
transferred is the value of this field plus 1.
If we would like to transfer 1 byte then we need to set `0b` in
FDBC for operations like read, write, flash id as to account for
the `set byte count` hence, the `len` argument should be `1`.
Additionally, as per EDS, the FDBC field is ignored for any block
erase command.
BUG=b:258280679
TEST=Able to build flashrom and perform below operations on Google,
Rex and Google, Kano/Taeko.
During `--wp-disable` HW seq operation that requires 1 byte data
transfer.
HSFC.FDBC value while passing `len` as `0` = 0x3f (represents 64-byte)
HSFC.FDBC value while passing `len` as `1` = 0x0 (represents 1-byte)
Original-Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Original-Change-Id: I5b911655649c693e576497520687d7810bbd3c54
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69789
Original-Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com>
Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Change-Id: Id54cb06bc66e86f95ea652ee604715e8969bcb02
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M ichspi.c
1 file changed, 53 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/87/69987/1
diff --git a/ichspi.c b/ichspi.c
index 29dcd25..dd5a2c1 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1360,6 +1360,12 @@
/* Set up transaction parameters. */
hsfc |= hsfc_cycle;
+ /*
+ * The number of bytes transferred is the value of `FDBC` plus 1, hence,
+ * subtracted 1 from the length field.
+ * As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f`
+ * represents 64-bytes to be transferred.
+ */
hsfc |= HSFC_FDBC_VAL(len - 1);
hsfc |= HSFC_FGO; /* start */
prettyprint_ich9_reg_hsfc(hsfc, ich_generation);
@@ -1399,7 +1405,7 @@
}
msg_pdbg("Reading Status register\n");
- if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RD_STATUS, 0, len, ich_generation,
+ if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RD_STATUS, 1, len, ich_generation,
hwseq_data->addr_mask)) {
msg_perr("Reading Status register failed\n!!");
return -1;
@@ -1422,7 +1428,7 @@
ich_fill_data(&value, len, ICH9_REG_FDATA0);
- if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WR_STATUS, 0, len, ich_generation,
+ if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_WR_STATUS, 1, len, ich_generation,
hwseq_data->addr_mask)) {
msg_perr("Writing Status register failed\n!!");
return -1;
@@ -1518,7 +1524,7 @@
msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
- if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_BLOCK_ERASE, addr, 0, ich_generation,
+ if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_BLOCK_ERASE, addr, 1, ich_generation,
hwseq_data->addr_mask))
return -1;
return 0;
--
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Gerrit-Project: flashrom
Gerrit-Branch: 1.3.x
Gerrit-Change-Id: Id54cb06bc66e86f95ea652ee604715e8969bcb02
Gerrit-Change-Number: 69987
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-CC: Subrata Banik <subratabanik(a)google.com>
Gerrit-MessageType: newchange
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69986 )
Change subject: ichspi: Clear Fast SPI HSFC register before HW seq operation
......................................................................
ichspi: Clear Fast SPI HSFC register before HW seq operation
This patch fixes a regression introduced with
commit 7ed1337309d3fe74f5af09520970f0f1d417399a (ichspi: Factor out
common hwseq_xfer logic into helpers).
The reason for the regression is ignoring the fact that the Fast SPI
controller MMIO register HSFC (0x06) might not hold the default zero
value before initiating the HW sequencing operation.
Having a `1b` value in the HSFC.FDBC (bits 24-29) field would represent
a byte that needs to be transfered.
While debugging the regression, we have observed that the default value
in the FDBC (prior to initiate any operation) is 0x3f (instead of
zero) which represents 64-byte transfer.
localhost ~ # iotools mmio_read32 0x92d16006
0x3f00
<Fast SPI MMIO BAR: 0x92d16000 and HSFC offset: 0x06>
FDBC offset during `--wp-disable` operation represents higher numbers of
bytes than the actual and eventually results in the error.
Additionally, dropped unused variable (struct hwseq_data *hwseq_data).
BUG=b:258280679
TEST=Able to build flashrom and perform below operations on Google, Rex
and Google, Kano/Taeko.
Without this patch:
HSFC register value inside ich_start_hwseq_xfer() before initiating
the HW seq operations: 0x3f00
HSFC register value inside ich_start_hwseq_xfer() during the HW seq
operations (Read Status): 0x3f11
With this patch:
HSFC register value inside ich_start_hwseq_xfer() before initiating
the HW seq operations: 0x0
HSFC register value inside ich_start_hwseq_xfer() during the HW seq
operations (Read Status): 0x11
Additionally, verified other HW sequencing operations (like read, write,
erase, read status, write status, read ID) working fine without any
error.
Original-Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Original-Change-Id: I4cc3f24f880d1d621f1f48a6e6b276449fa46f98
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/69788
Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Original-Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org>
Original-Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com>
Change-Id: I1b77e563f67ad2793983b65e694be60c85f126c0
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M ichspi.c
1 file changed, 66 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/86/69986/1
diff --git a/ichspi.c b/ichspi.c
index cd6e802..29dcd25 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1349,8 +1349,8 @@
uint32_t hsfc_cycle, uint32_t flash_addr, size_t len,
uint32_t addr_mask)
{
- uint16_t hsfc;
- struct hwseq_data *hwseq_data = get_hwseq_data_from_context(flash);
+ /* make sure HSFC register is cleared before initiate any operation */
+ uint16_t hsfc = 0;
/* Sets flash_addr in FADDR */
ich_hwseq_set_addr(flash_addr, addr_mask);
@@ -1359,8 +1359,6 @@
REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
/* Set up transaction parameters. */
- hsfc = REGREAD16(ICH9_REG_HSFC);
- hsfc &= ~hwseq_data->hsfc_fcycle; /* clear operation */
hsfc |= hsfc_cycle;
hsfc |= HSFC_FDBC_VAL(len - 1);
hsfc |= HSFC_FGO; /* start */
--
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70003 )
Change subject: cli, manpage: Clean up occurrences of old image argument
......................................................................
Patch Set 2:
(1 comment)
File cli_classic.c:
https://review.coreboot.org/c/flashrom/+/70003/comment/6ad403eb_f56d3244
PS2, Line 622: {"image", 1, NULL, 'i'},
Add a comment here that this is deprecated
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