May 2021 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: nicintel_spi.c: Refactor singleton states into reentrant pattern
by Anastasia Klimchuk (Code Review) May 26, 2021

May 26, 2021

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54995 ) Change subject: nicintel_spi.c: Refactor singleton states into reentrant pattern ...................................................................... nicintel_spi.c: Refactor singleton states into reentrant pattern Move global singleton states into a struct and store within the bitbang_spi_master data field for the life-time of the driver. This is one of the steps on the way to move spi_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". BUG=b:185191942 TEST=builds Change-Id: I385d3ced19dfe6453ccc4128a7b792c2dce3a449 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M nicintel_spi.c 1 file changed, 79 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/54995/1 diff --git a/nicintel_spi.c b/nicintel_spi.c index 9e97840..82b9c34 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -75,7 +75,9 @@ #define BIT(x) (1<<(x)) -static uint8_t *nicintel_spibar; +struct nicintel_spi_data { + uint8_t *nicintel_spibar; +}; const struct dev_entry nics_intel_spi[] = { {PCI_VENDOR_ID_INTEL, 0x105e, OK, "Intel", "82571EB Gigabit Ethernet Controller"}, @@ -109,60 +111,66 @@ static void nicintel_request_spibus(void *spi_data) { + struct nicintel_spi_data *data = spi_data; uint32_t tmp; - tmp = pci_mmio_readl(nicintel_spibar + FLA); + tmp = pci_mmio_readl(data->nicintel_spibar + FLA); tmp |= BIT(FL_REQ); - pci_mmio_writel(tmp, nicintel_spibar + FLA); + pci_mmio_writel(tmp, data->nicintel_spibar + FLA); /* Wait until we are allowed to use the SPI bus. */ - while (!(pci_mmio_readl(nicintel_spibar + FLA) & BIT(FL_GNT))) ; + while (!(pci_mmio_readl(data->nicintel_spibar + FLA) & BIT(FL_GNT))) ; } static void nicintel_release_spibus(void *spi_data) { + struct nicintel_spi_data *data = spi_data; uint32_t tmp; - tmp = pci_mmio_readl(nicintel_spibar + FLA); + tmp = pci_mmio_readl(data->nicintel_spibar + FLA); tmp &= ~BIT(FL_REQ); - pci_mmio_writel(tmp, nicintel_spibar + FLA); + pci_mmio_writel(tmp, data->nicintel_spibar + FLA); } static void nicintel_bitbang_set_cs(int val, void *spi_data) { + struct nicintel_spi_data *data = spi_data; uint32_t tmp; - tmp = pci_mmio_readl(nicintel_spibar + FLA); + tmp = pci_mmio_readl(data->nicintel_spibar + FLA); tmp &= ~BIT(FL_CS); tmp |= (val << FL_CS); - pci_mmio_writel(tmp, nicintel_spibar + FLA); + pci_mmio_writel(tmp, data->nicintel_spibar + FLA); } static void nicintel_bitbang_set_sck(int val, void *spi_data) { + struct nicintel_spi_data *data = spi_data; uint32_t tmp; - tmp = pci_mmio_readl(nicintel_spibar + FLA); + tmp = pci_mmio_readl(data->nicintel_spibar + FLA); tmp &= ~BIT(FL_SCK); tmp |= (val << FL_SCK); - pci_mmio_writel(tmp, nicintel_spibar + FLA); + pci_mmio_writel(tmp, data->nicintel_spibar + FLA); } static void nicintel_bitbang_set_mosi(int val, void *spi_data) { + struct nicintel_spi_data *data = spi_data; uint32_t tmp; - tmp = pci_mmio_readl(nicintel_spibar + FLA); + tmp = pci_mmio_readl(data->nicintel_spibar + FLA); tmp &= ~BIT(FL_SI); tmp |= (val << FL_SI); - pci_mmio_writel(tmp, nicintel_spibar + FLA); + pci_mmio_writel(tmp, data->nicintel_spibar + FLA); } static int nicintel_bitbang_get_miso(void *spi_data) { + struct nicintel_spi_data *data = spi_data; uint32_t tmp; - tmp = pci_mmio_readl(nicintel_spibar + FLA); + tmp = pci_mmio_readl(data->nicintel_spibar + FLA); tmp = (tmp >> FL_SO) & 0x1; return tmp; } @@ -177,20 +185,22 @@ .half_period = 1, }; -static int nicintel_spi_shutdown(void *data) +static int nicintel_spi_shutdown(void *spi_data) { + struct nicintel_spi_data *data = spi_data; uint32_t tmp; /* Disable writes manually. See the comment about EECD in nicintel_spi_init() for details. */ - tmp = pci_mmio_readl(nicintel_spibar + EECD); + tmp = pci_mmio_readl(data->nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_ENABLED; tmp |= FLASH_WRITES_DISABLED; - pci_mmio_writel(tmp, nicintel_spibar + EECD); + pci_mmio_writel(tmp, data->nicintel_spibar + EECD); + free(data); return 0; } -static int nicintel_spi_82599_enable_flash(void) +static int nicintel_spi_82599_enable_flash(struct nicintel_spi_data *data) { uint32_t tmp; @@ -199,45 +209,53 @@ * but other bits with side effects as well. Those other bits must be * left untouched. */ - tmp = pci_mmio_readl(nicintel_spibar + EECD); + tmp = pci_mmio_readl(data->nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_DISABLED; tmp |= FLASH_WRITES_ENABLED; - pci_mmio_writel(tmp, nicintel_spibar + EECD); + pci_mmio_writel(tmp, data->nicintel_spibar + EECD); /* test if FWE is really set to allow writes */ - tmp = pci_mmio_readl(nicintel_spibar + EECD); + tmp = pci_mmio_readl(data->nicintel_spibar + EECD); if ( (tmp & FLASH_WRITES_DISABLED) || !(tmp & FLASH_WRITES_ENABLED) ) { msg_perr("Enabling flash write access failed.\n"); return 1; } - if (register_shutdown(nicintel_spi_shutdown, NULL)) + if (register_shutdown(nicintel_spi_shutdown, data)) return 1; return 0; } -static int nicintel_spi_i210_enable_flash(void) +static int nicintel_spi_i210_shutdown(void *data) +{ + free(data); + return 0; +} + +static int nicintel_spi_i210_enable_flash(struct nicintel_spi_data *data) { uint32_t tmp; - tmp = pci_mmio_readl(nicintel_spibar + FLA); + tmp = pci_mmio_readl(data->nicintel_spibar + FLA); if (tmp & BIT(FL_LOCKED)) { msg_perr("Flash is in Secure Mode. Abort.\n"); return 1; } - if (!(tmp & BIT(FL_ABORT))) - return 0; - - tmp |= BIT(FL_CLR_ERR); - pci_mmio_writel(tmp, nicintel_spibar + FLA); - tmp = pci_mmio_readl(nicintel_spibar + FLA); - if (!(tmp & BIT(FL_ABORT))) { - msg_perr("Unable to clear Flash Access Error. Abort\n"); - return 1; + if (tmp & BIT(FL_ABORT)) { + tmp |= BIT(FL_CLR_ERR); + pci_mmio_writel(tmp, data->nicintel_spibar + FLA); + tmp = pci_mmio_readl(data->nicintel_spibar + FLA); + if (!(tmp & BIT(FL_ABORT))) { + msg_perr("Unable to clear Flash Access Error. Abort\n"); + return 1; + } } + if (register_shutdown(nicintel_spi_i210_shutdown, data)) + return 1; + return 0; } @@ -256,25 +274,37 @@ if (!io_base_addr) return 1; - if ((dev->device_id & 0xfff0) == 0x1530) { - nicintel_spibar = rphysmap("Intel I210 Gigabit w/ SPI flash", io_base_addr + 0x12000, - MEMMAP_SIZE); - if (!nicintel_spibar || nicintel_spi_i210_enable_flash()) - return 1; - } else if (dev->device_id < 0x10d8) { - nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, - MEMMAP_SIZE); - if (!nicintel_spibar || nicintel_spi_82599_enable_flash()) - return 1; - } else { - nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000, - MEMMAP_SIZE); - if (!nicintel_spibar || nicintel_spi_82599_enable_flash()) - return 1; + struct nicintel_spi_data *data = calloc(1, sizeof(*data)); + if (!data) { + msg_perr("Unable to allocate space for SPI master data\n"); + return 1; } - if (register_spi_bitbang_master(&bitbang_spi_master_nicintel, NULL)) - return 1; + if ((dev->device_id & 0xfff0) == 0x1530) { + data->nicintel_spibar = rphysmap("Intel I210 Gigabit w/ SPI flash", io_base_addr + 0x12000, + MEMMAP_SIZE); + if (!data->nicintel_spibar || nicintel_spi_i210_enable_flash(data)) { + free(data); + return 1; + } + } else if (dev->device_id < 0x10d8) { + data->nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, + MEMMAP_SIZE); + if (!data->nicintel_spibar || nicintel_spi_82599_enable_flash(data)) { + free(data); + return 1; + } + } else { + data->nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000, + MEMMAP_SIZE); + if (!data->nicintel_spibar || nicintel_spi_82599_enable_flash(data)) { + free(data); + return 1; + } + } + + if (register_spi_bitbang_master(&bitbang_spi_master_nicintel, data)) + return 1; /* shutdown function does cleanup */ return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/54995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I385d3ced19dfe6453ccc4128a7b792c2dce3a449 Gerrit-Change-Number: 54995 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: pony_spi.c: Refactor singleton states into reentrant pattern
by Anastasia Klimchuk (Code Review) May 26, 2021

May 26, 2021

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54997 ) Change subject: pony_spi.c: Refactor singleton states into reentrant pattern ...................................................................... pony_spi.c: Refactor singleton states into reentrant pattern Move global singleton states into a struct and store within the bitbang_spi_master data field for the life-time of the driver. This is one of the steps on the way to move spi_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". BUG=b:185191942 TEST=builds Change-Id: Icf1125dadcdaa287ebe3c07ca95adb770bb19412 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M pony_spi.c 1 file changed, 49 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/97/54997/1 diff --git a/pony_spi.c b/pony_spi.c index 940cae1..97b87be 100644 --- a/pony_spi.c +++ b/pony_spi.c @@ -49,16 +49,20 @@ TYPE_AJAWE }; -/* Pins for master->slave direction */ -static int pony_negate_cs = 1; -static int pony_negate_sck = 0; -static int pony_negate_mosi = 0; -/* Pins for slave->master direction */ -static int pony_negate_miso = 0; +struct pony_spi_data { + /* Pins for master->slave direction */ + int pony_negate_cs; + int pony_negate_sck; + int pony_negate_mosi; + /* Pins for slave->master direction */ + int pony_negate_miso; +}; static void pony_bitbang_set_cs(int val, void *spi_data) { - if (pony_negate_cs) + struct pony_spi_data *data = spi_data; + + if (data->pony_negate_cs) val ^= 1; sp_set_pin(PIN_TXD, val); @@ -66,7 +70,9 @@ static void pony_bitbang_set_sck(int val, void *spi_data) { - if (pony_negate_sck) + struct pony_spi_data *data = spi_data; + + if (data->pony_negate_sck) val ^= 1; sp_set_pin(PIN_RTS, val); @@ -74,7 +80,9 @@ static void pony_bitbang_set_mosi(int val, void *spi_data) { - if (pony_negate_mosi) + struct pony_spi_data *data = spi_data; + + if (data->pony_negate_mosi) val ^= 1; sp_set_pin(PIN_DTR, val); @@ -82,9 +90,10 @@ static int pony_bitbang_get_miso(void *spi_data) { + struct pony_spi_data *data = spi_data; int tmp = sp_get_pin(PIN_CTS); - if (pony_negate_miso) + if (data->pony_negate_miso) tmp ^= 1; return tmp; @@ -107,6 +116,7 @@ else msg_pdbg("Pony SPI shutdown completed.\n"); + free(data); return ret; } @@ -119,6 +129,16 @@ int have_device = 0; int have_prog = 0; + struct pony_spi_data *data = calloc(1, sizeof(*data)); + if (!data) { + msg_perr("Unable to allocate space for SPI master data\n"); + return 1; + } + data->pony_negate_cs = 1; + data->pony_negate_sck = 0; + data->pony_negate_mosi = 0; + data->pony_negate_miso = 0; + /* The parameter is in format "dev=/dev/device,type=serbang" */ arg = extract_programmer_param("dev"); if (arg && strlen(arg)) { @@ -127,8 +147,9 @@ free(arg); return 1; } - if (register_shutdown(pony_spi_shutdown, NULL) != 0) { + if (register_shutdown(pony_spi_shutdown, data) != 0) { free(arg); + free(data); serialport_shutdown(NULL); return 1; } @@ -165,25 +186,25 @@ */ switch (type) { case TYPE_AJAWE: - pony_negate_cs = 1; - pony_negate_sck = 1; - pony_negate_mosi = 1; - pony_negate_miso = 1; + data->pony_negate_cs = 1; + data->pony_negate_sck = 1; + data->pony_negate_mosi = 1; + data->pony_negate_miso = 1; name = "AJAWe"; break; case TYPE_SERBANG: - pony_negate_cs = 0; - pony_negate_sck = 0; - pony_negate_mosi = 0; - pony_negate_miso = 1; + data->pony_negate_cs = 0; + data->pony_negate_sck = 0; + data->pony_negate_mosi = 0; + data->pony_negate_miso = 1; name = "serbang"; break; default: case TYPE_SI_PROG: - pony_negate_cs = 1; - pony_negate_sck = 0; - pony_negate_mosi = 0; - pony_negate_miso = 0; + data->pony_negate_cs = 1; + data->pony_negate_sck = 0; + data->pony_negate_mosi = 0; + data->pony_negate_miso = 0; name = "SI-Prog"; break; } @@ -192,9 +213,9 @@ /* * Detect if there is a compatible hardware programmer connected. */ - pony_bitbang_set_cs(1, NULL); - pony_bitbang_set_sck(1, NULL); - pony_bitbang_set_mosi(1, NULL); + pony_bitbang_set_cs(1, data); + pony_bitbang_set_sck(1, data); + pony_bitbang_set_mosi(1, data); switch (type) { case TYPE_AJAWE: @@ -224,8 +245,8 @@ return 1; } - if (register_spi_bitbang_master(&bitbang_spi_master_pony, NULL)) { + if (register_spi_bitbang_master(&bitbang_spi_master_pony, data)) return 1; - } + return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/54997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Icf1125dadcdaa287ebe3c07ca95adb770bb19412 Gerrit-Change-Number: 54997 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ogp_spi.c: Refactor singleton states into reentrant pattern
by Anastasia Klimchuk (Code Review) May 26, 2021

May 26, 2021

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54996 ) Change subject: ogp_spi.c: Refactor singleton states into reentrant pattern ...................................................................... ogp_spi.c: Refactor singleton states into reentrant pattern Move global singleton states into a struct and store within the bitbang_spi_master data field for the life-time of the driver. This is one of the steps on the way to move spi_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". BUG=b:185191942 TEST=builds Change-Id: I6b8f6ecd7c9949ffb4098bf56a8936393283382f Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M ogp_spi.c 1 file changed, 46 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/54996/1 diff --git a/ogp_spi.c b/ogp_spi.c index 01694ca..a5d38f7 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -36,12 +36,14 @@ #define OGA1_XP10_CPROM_SCK 0x0058 /* W */ #define OGA1_XP10_CPROM_REG_SEL 0x005C /* W */ -static uint8_t *ogp_spibar; +struct ogp_spi_data { + uint8_t *ogp_spibar; -static uint32_t ogp_reg_sel; -static uint32_t ogp_reg_siso; -static uint32_t ogp_reg__ce; -static uint32_t ogp_reg_sck; + uint32_t ogp_reg_sel; + uint32_t ogp_reg_siso; + uint32_t ogp_reg__ce; + uint32_t ogp_reg_sck; +}; const struct dev_entry ogp_spi[] = { {PCI_VENDOR_ID_OGP, 0x0000, OK, "Open Graphics Project", "Development Board OGD1"}, @@ -51,34 +53,40 @@ static void ogp_request_spibus(void *spi_data) { - pci_mmio_writel(1, ogp_spibar + ogp_reg_sel); + struct ogp_spi_data *data = spi_data; + pci_mmio_writel(1, data->ogp_spibar + data->ogp_reg_sel); } static void ogp_release_spibus(void *spi_data) { - pci_mmio_writel(0, ogp_spibar + ogp_reg_sel); + struct ogp_spi_data *data = spi_data; + pci_mmio_writel(0, data->ogp_spibar + data->ogp_reg_sel); } static void ogp_bitbang_set_cs(int val, void *spi_data) { - pci_mmio_writel(val, ogp_spibar + ogp_reg__ce); + struct ogp_spi_data *data = spi_data; + pci_mmio_writel(val, data->ogp_spibar + data->ogp_reg__ce); } static void ogp_bitbang_set_sck(int val, void *spi_data) { - pci_mmio_writel(val, ogp_spibar + ogp_reg_sck); + struct ogp_spi_data *data = spi_data; + pci_mmio_writel(val, data->ogp_spibar + data->ogp_reg_sck); } static void ogp_bitbang_set_mosi(int val, void *spi_data) { - pci_mmio_writel(val, ogp_spibar + ogp_reg_siso); + struct ogp_spi_data *data = spi_data; + pci_mmio_writel(val, data->ogp_spibar + data->ogp_reg_siso); } static int ogp_bitbang_get_miso(void *spi_data) { + struct ogp_spi_data *data = spi_data; uint32_t tmp; - tmp = pci_mmio_readl(ogp_spibar + ogp_reg_siso); + tmp = pci_mmio_readl(data->ogp_spibar + data->ogp_reg_siso); return tmp & 0x1; } @@ -92,10 +100,21 @@ .half_period = 0, }; +static int ogp_spi_shutdown(void *data) +{ + free(data); + return 0; +} + int ogp_spi_init(void) { struct pci_dev *dev = NULL; char *type; + uint8_t *ogp_spibar; + uint32_t ogp_reg_sel; + uint32_t ogp_reg_siso; + uint32_t ogp_reg__ce; + uint32_t ogp_reg_sck; type = extract_programmer_param("rom"); @@ -135,7 +154,22 @@ if (ogp_spibar == ERROR_PTR) return 1; - if (register_spi_bitbang_master(&bitbang_spi_master_ogp, NULL)) + struct ogp_spi_data *data = calloc(1, sizeof(*data)); + if(!data) { + msg_perr("Unable to allocate space for SPI master data\n"); + return 1; + } + data->ogp_spibar = ogp_spibar; + data->ogp_reg_sel = ogp_reg_sel; + data->ogp_reg_siso = ogp_reg_siso; + data->ogp_reg__ce = ogp_reg__ce; + data->ogp_reg_sck = ogp_reg_sck; + if (register_shutdown(ogp_spi_shutdown, data)) { + free(data); + return 1; + } + + if (register_spi_bitbang_master(&bitbang_spi_master_ogp, data)) return 1; return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/54996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6b8f6ecd7c9949ffb4098bf56a8936393283382f Gerrit-Change-Number: 54996 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: developerbox_spi.c: Refactor singleton states into reentrant pattern
by Anastasia Klimchuk (Code Review) May 26, 2021

May 26, 2021

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54993 ) Change subject: developerbox_spi.c: Refactor singleton states into reentrant pattern ...................................................................... developerbox_spi.c: Refactor singleton states into reentrant pattern Move global singleton states into a struct and store within the bitbang_spi_master data field for the life-time of the driver. This is one of the steps on the way to move spi_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". BUG=b:185191942 TEST=builds Change-Id: I84bf0cffa4a14e58103bdb1e7e65ec2475344f12 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M developerbox_spi.c 1 file changed, 39 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/54993/1 diff --git a/developerbox_spi.c b/developerbox_spi.c index e741890..e4ab6f6 100644 --- a/developerbox_spi.c +++ b/developerbox_spi.c @@ -60,15 +60,18 @@ {0}, }; -static struct libusb_context *usb_ctx; -static libusb_device_handle *cp210x_handle; +struct devbox_spi_data { + struct libusb_context *usb_ctx; + libusb_device_handle *cp210x_handle; +}; -static int cp210x_gpio_get(void) +static int cp210x_gpio_get(void *spi_data) { int res; uint8_t gpio; + struct devbox_spi_data *data = spi_data; - res = libusb_control_transfer(cp210x_handle, REQTYPE_DEVICE_TO_HOST, + res = libusb_control_transfer(data->cp210x_handle, REQTYPE_DEVICE_TO_HOST, CP210X_VENDOR_SPECIFIC, CP210X_READ_LATCH, 0, &gpio, 1, 0); if (res < 0) { @@ -79,15 +82,16 @@ return gpio; } -static void cp210x_gpio_set(uint8_t val, uint8_t mask) +static void cp210x_gpio_set(uint8_t val, uint8_t mask, void *spi_data) { int res; uint16_t gpio; + struct devbox_spi_data *data = spi_data; gpio = ((val & 0xf) << 8) | (mask & 0xf); /* Set relay state on the card */ - res = libusb_control_transfer(cp210x_handle, REQTYPE_HOST_TO_DEVICE, + res = libusb_control_transfer(data->cp210x_handle, REQTYPE_HOST_TO_DEVICE, CP210X_VENDOR_SPECIFIC, CP210X_WRITE_LATCH, gpio, NULL, 0, 0); if (res < 0) @@ -96,28 +100,29 @@ static void cp210x_bitbang_set_cs(int val, void *spi_data) { - cp210x_gpio_set(val << DEVELOPERBOX_SPI_CS, 1 << DEVELOPERBOX_SPI_CS); + cp210x_gpio_set(val << DEVELOPERBOX_SPI_CS, 1 << DEVELOPERBOX_SPI_CS, spi_data); } static void cp210x_bitbang_set_sck(int val, void *spi_data) { - cp210x_gpio_set(val << DEVELOPERBOX_SPI_SCK, 1 << DEVELOPERBOX_SPI_SCK); + cp210x_gpio_set(val << DEVELOPERBOX_SPI_SCK, 1 << DEVELOPERBOX_SPI_SCK, spi_data); } static void cp210x_bitbang_set_mosi(int val, void *spi_data) { - cp210x_gpio_set(val << DEVELOPERBOX_SPI_MOSI, 1 << DEVELOPERBOX_SPI_MOSI); + cp210x_gpio_set(val << DEVELOPERBOX_SPI_MOSI, 1 << DEVELOPERBOX_SPI_MOSI, spi_data); } static int cp210x_bitbang_get_miso(void *spi_data) { - return !!(cp210x_gpio_get() & (1 << DEVELOPERBOX_SPI_MISO)); + return !!(cp210x_gpio_get(spi_data) & (1 << DEVELOPERBOX_SPI_MISO)); } static void cp210x_bitbang_set_sck_set_mosi(int sck, int mosi, void *spi_data) { cp210x_gpio_set(sck << DEVELOPERBOX_SPI_SCK | mosi << DEVELOPERBOX_SPI_MOSI, - 1 << DEVELOPERBOX_SPI_SCK | 1 << DEVELOPERBOX_SPI_MOSI); + 1 << DEVELOPERBOX_SPI_SCK | 1 << DEVELOPERBOX_SPI_MOSI, + spi_data); } static const struct bitbang_spi_master bitbang_spi_master_cp210x = { @@ -128,16 +133,22 @@ .set_sck_set_mosi = cp210x_bitbang_set_sck_set_mosi, }; -static int developerbox_spi_shutdown(void *data) +static int developerbox_spi_shutdown(void *spi_data) { - libusb_close(cp210x_handle); - libusb_exit(usb_ctx); + struct devbox_spi_data *data = spi_data; + libusb_close(data->cp210x_handle); + libusb_exit(data->usb_ctx); + + free(data); return 0; } int developerbox_spi_init(void) { + struct libusb_context *usb_ctx; + libusb_device_handle *cp210x_handle; + libusb_init(&usb_ctx); if (!usb_ctx) { msg_perr("Could not initialize libusb!\n"); @@ -155,15 +166,27 @@ goto err_exit; } - if (register_shutdown(developerbox_spi_shutdown, NULL)) + struct devbox_spi_data *data = calloc(1, sizeof(*data)); + if (!data) { + msg_perr("Unable to allocate space for SPI master data\n"); goto err_exit; + } + data->usb_ctx = usb_ctx; + data->cp210x_handle = cp210x_handle; - if (register_spi_bitbang_master(&bitbang_spi_master_cp210x, NULL)) + if (register_shutdown(developerbox_spi_shutdown, data)) { + free(data); goto err_exit; + } + + if (register_spi_bitbang_master(&bitbang_spi_master_cp210x, data)) + return 1; /* shutdown function does the cleanup */ return 0; err_exit: + if (cp210x_handle) + libusb_close(cp210x_handle); libusb_exit(usb_ctx); return 1; } -- To view, visit https://review.coreboot.org/c/flashrom/+/54993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I84bf0cffa4a14e58103bdb1e7e65ec2475344f12 Gerrit-Change-Number: 54993 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: bitbang_spi.c: Pass spi data into bitbang_spi_master functions
by Anastasia Klimchuk (Code Review) May 26, 2021

May 26, 2021

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54992 ) Change subject: bitbang_spi.c: Pass spi data into bitbang_spi_master functions ...................................................................... bitbang_spi.c: Pass spi data into bitbang_spi_master functions BUG=b:185191942 TEST=builds Change-Id: I90a340aeb9ed70605f5963aa66ee913d22bff865 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M bitbang_spi.c 1 file changed, 36 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/92/54992/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index 601b7a6..e941910 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -22,74 +22,76 @@ #include "spi.h" /* Note that CS# is active low, so val=0 means the chip is active. */ -static void bitbang_spi_set_cs(const struct bitbang_spi_master * const master, int val) +static void bitbang_spi_set_cs(const struct bitbang_spi_master * const master, int val, void *spi_data) { - master->set_cs(val, NULL); + master->set_cs(val, spi_data); } -static void bitbang_spi_set_sck(const struct bitbang_spi_master * const master, int val) +static void bitbang_spi_set_sck(const struct bitbang_spi_master * const master, int val, void *spi_data) { - master->set_sck(val, NULL); + master->set_sck(val, spi_data); } -static void bitbang_spi_request_bus(const struct bitbang_spi_master * const master) +static void bitbang_spi_request_bus(const struct bitbang_spi_master * const master, void *spi_data) { if (master->request_bus) - master->request_bus(NULL); + master->request_bus(spi_data); } -static void bitbang_spi_release_bus(const struct bitbang_spi_master * const master) +static void bitbang_spi_release_bus(const struct bitbang_spi_master * const master, void *spi_data) { if (master->release_bus) - master->release_bus(NULL); + master->release_bus(spi_data); } -static void bitbang_spi_set_sck_set_mosi(const struct bitbang_spi_master * const master, int sck, int mosi) +static void bitbang_spi_set_sck_set_mosi(const struct bitbang_spi_master * const master, int sck, int mosi, + void *spi_data) { if (master->set_sck_set_mosi) { - master->set_sck_set_mosi(sck, mosi, NULL); + master->set_sck_set_mosi(sck, mosi, spi_data); return; } - master->set_sck(sck, NULL); - master->set_mosi(mosi, NULL); + master->set_sck(sck, spi_data); + master->set_mosi(mosi, spi_data); } -static int bitbang_spi_set_sck_get_miso(const struct bitbang_spi_master * const master, int sck) +static int bitbang_spi_set_sck_get_miso(const struct bitbang_spi_master * const master, int sck, + void *spi_data) { if (master->set_sck_get_miso) - return master->set_sck_get_miso(sck, NULL); + return master->set_sck_get_miso(sck, spi_data); - master->set_sck(sck, NULL); - return master->get_miso(NULL); + master->set_sck(sck, spi_data); + return master->get_miso(spi_data); } -static uint8_t bitbang_spi_read_byte(const struct bitbang_spi_master *master) +static uint8_t bitbang_spi_read_byte(const struct bitbang_spi_master *master, void *spi_data) { uint8_t ret = 0; int i; for (i = 7; i >= 0; i--) { if (i == 0) - bitbang_spi_set_sck_set_mosi(master, 0, 0); + bitbang_spi_set_sck_set_mosi(master, 0, 0, spi_data); else - bitbang_spi_set_sck(master, 0); + bitbang_spi_set_sck(master, 0, spi_data); programmer_delay(master->half_period); ret <<= 1; - ret |= bitbang_spi_set_sck_get_miso(master, 1); + ret |= bitbang_spi_set_sck_get_miso(master, 1, spi_data); programmer_delay(master->half_period); } return ret; } -static void bitbang_spi_write_byte(const struct bitbang_spi_master *master, uint8_t val) +static void bitbang_spi_write_byte(const struct bitbang_spi_master *master, uint8_t val, void *spi_data) { int i; for (i = 7; i >= 0; i--) { - bitbang_spi_set_sck_set_mosi(master, 0, (val >> i) & 1); + bitbang_spi_set_sck_set_mosi(master, 0, (val >> i) & 1, spi_data); programmer_delay(master->half_period); - bitbang_spi_set_sck(master, 1); + bitbang_spi_set_sck(master, 1, spi_data); programmer_delay(master->half_period); } } @@ -112,19 +114,19 @@ * Requesting and releasing the SPI bus is handled in here to allow the * programmer to use its own SPI engine for native accesses. */ - bitbang_spi_request_bus(master); - bitbang_spi_set_cs(master, 0); + bitbang_spi_request_bus(master, data->spi_data); + bitbang_spi_set_cs(master, 0, data->spi_data); for (i = 0; i < writecnt; i++) - bitbang_spi_write_byte(master, writearr[i]); + bitbang_spi_write_byte(master, writearr[i], data->spi_data); for (i = 0; i < readcnt; i++) - readarr[i] = bitbang_spi_read_byte(master); + readarr[i] = bitbang_spi_read_byte(master, data->spi_data); - bitbang_spi_set_sck(master, 0); + bitbang_spi_set_sck(master, 0, data->spi_data); programmer_delay(master->half_period); - bitbang_spi_set_cs(master, 1); + bitbang_spi_set_cs(master, 1, data->spi_data); programmer_delay(master->half_period); /* FIXME: Run bitbang_spi_release_bus here or in programmer init? */ - bitbang_spi_release_bus(master); + bitbang_spi_release_bus(master, data->spi_data); return 0; } @@ -169,12 +171,12 @@ register_shutdown(bitbang_spi_shutdown, data); /* Only mess with the bus if we're sure nobody else uses it. */ - bitbang_spi_request_bus(master); - bitbang_spi_set_cs(master, 1); - bitbang_spi_set_sck_set_mosi(master, 0, 0); + bitbang_spi_request_bus(master, spi_data); + bitbang_spi_set_cs(master, 1, spi_data); + bitbang_spi_set_sck_set_mosi(master, 0, 0, spi_data); /* FIXME: Release SPI bus here and request it again for each command or * don't release it now and only release it on programmer shutdown? */ - bitbang_spi_release_bus(master); + bitbang_spi_release_bus(master, spi_data); return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/54992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I90a340aeb9ed70605f5963aa66ee913d22bff865 Gerrit-Change-Number: 54992 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: mcp6x_spi.c: Refactor singleton states into reentrant pattern
by Anastasia Klimchuk (Code Review) May 26, 2021

May 26, 2021

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54994 ) Change subject: mcp6x_spi.c: Refactor singleton states into reentrant pattern ...................................................................... mcp6x_spi.c: Refactor singleton states into reentrant pattern Move global singleton states into a struct and store within the bitbang_spi_master data field for the life-time of the driver. This is one of the steps on the way to move spi_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". BUG=b:185191942 TEST=builds Change-Id: Ia02c1cb9d36fb7b15bb7e09b769d8969c08c2bd5 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M mcp6x_spi.c 1 file changed, 56 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/54994/1 diff --git a/mcp6x_spi.c b/mcp6x_spi.c index de44299..083ad56 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -36,55 +36,68 @@ #define MCP6X_SPI_REQUEST 0 #define MCP6X_SPI_GRANT 8 -static void *mcp6x_spibar = NULL; - -/* Cached value of last GPIO state. */ -static uint8_t mcp_gpiostate; +struct mcp6x_spi_data { + void *mcp6x_spibar; + /* Cached value of last GPIO state. */ + uint8_t mcp_gpiostate; +}; static void mcp6x_request_spibus(void *spi_data) { - mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); - mcp_gpiostate |= 1 << MCP6X_SPI_REQUEST; - mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); + struct mcp6x_spi_data *data = spi_data; + + data->mcp_gpiostate = mmio_readb(data->mcp6x_spibar + 0x530); + data->mcp_gpiostate |= 1 << MCP6X_SPI_REQUEST; + mmio_writeb(data->mcp_gpiostate, data->mcp6x_spibar + 0x530); /* Wait until we are allowed to use the SPI bus. */ - while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) ; + while (!(mmio_readw(data->mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) ; /* Update the cache. */ - mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + data->mcp_gpiostate = mmio_readb(data->mcp6x_spibar + 0x530); } static void mcp6x_release_spibus(void *spi_data) { - mcp_gpiostate &= ~(1 << MCP6X_SPI_REQUEST); - mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); + struct mcp6x_spi_data *data = spi_data; + + data->mcp_gpiostate &= ~(1 << MCP6X_SPI_REQUEST); + mmio_writeb(data->mcp_gpiostate, data->mcp6x_spibar + 0x530); } static void mcp6x_bitbang_set_cs(int val, void *spi_data) { - mcp_gpiostate &= ~(1 << MCP6X_SPI_CS); - mcp_gpiostate |= (val << MCP6X_SPI_CS); - mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); + struct mcp6x_spi_data *data = spi_data; + + data->mcp_gpiostate &= ~(1 << MCP6X_SPI_CS); + data->mcp_gpiostate |= (val << MCP6X_SPI_CS); + mmio_writeb(data->mcp_gpiostate, data->mcp6x_spibar + 0x530); } static void mcp6x_bitbang_set_sck(int val, void *spi_data) { - mcp_gpiostate &= ~(1 << MCP6X_SPI_SCK); - mcp_gpiostate |= (val << MCP6X_SPI_SCK); - mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); + struct mcp6x_spi_data *data = spi_data; + + data->mcp_gpiostate &= ~(1 << MCP6X_SPI_SCK); + data->mcp_gpiostate |= (val << MCP6X_SPI_SCK); + mmio_writeb(data->mcp_gpiostate, data->mcp6x_spibar + 0x530); } static void mcp6x_bitbang_set_mosi(int val, void *spi_data) { - mcp_gpiostate &= ~(1 << MCP6X_SPI_MOSI); - mcp_gpiostate |= (val << MCP6X_SPI_MOSI); - mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); + struct mcp6x_spi_data *data = spi_data; + + data->mcp_gpiostate &= ~(1 << MCP6X_SPI_MOSI); + data->mcp_gpiostate |= (val << MCP6X_SPI_MOSI); + mmio_writeb(data->mcp_gpiostate, data->mcp6x_spibar + 0x530); } static int mcp6x_bitbang_get_miso(void *spi_data) { - mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); - return (mcp_gpiostate >> MCP6X_SPI_MISO) & 0x1; + struct mcp6x_spi_data *data = spi_data; + + data->mcp_gpiostate = mmio_readb(data->mcp6x_spibar + 0x530); + return (data->mcp_gpiostate >> MCP6X_SPI_MISO) & 0x1; } static const struct bitbang_spi_master bitbang_spi_master_mcp6x = { @@ -97,11 +110,19 @@ .half_period = 0, }; +static int mcp6x_shutdown(void *spi_data) +{ + free(spi_data); + return 0; +} + int mcp6x_spi_init(int want_spi) { uint16_t status; uint32_t mcp6x_spibaraddr; struct pci_dev *smbusdev; + void *mcp6x_spibar = NULL; + uint8_t mcp_gpiostate; /* Look for the SMBus device (SMBus PCI class) */ smbusdev = pci_dev_find_vendorclass(0x10de, 0x0c05); @@ -151,7 +172,19 @@ (status >> MCP6X_SPI_GRANT) & 0x1); mcp_gpiostate = status & 0xff; - if (register_spi_bitbang_master(&bitbang_spi_master_mcp6x, NULL)) { + struct mcp6x_spi_data *data = calloc(1, sizeof(*data)); + if (!data) { + msg_perr("Unable to allocate space for SPI master data\n"); + return 1; + } + data->mcp6x_spibar = mcp6x_spibar; + data->mcp_gpiostate = mcp_gpiostate; + + if (register_shutdown(mcp6x_shutdown, data)) { + free(data); + return 1; + } + if (register_spi_bitbang_master(&bitbang_spi_master_mcp6x, data)) { /* This should never happen. */ msg_perr("MCP6X bitbang SPI master init failed!\n"); return 1; -- To view, visit https://review.coreboot.org/c/flashrom/+/54994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia02c1cb9d36fb7b15bb7e09b769d8969c08c2bd5 Gerrit-Change-Number: 54994 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: bitbang: Extend register_spi_bitbang_master() API with spi data
by Anastasia Klimchuk (Code Review) May 26, 2021

May 26, 2021

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54990 ) Change subject: bitbang: Extend register_spi_bitbang_master() API with spi data ...................................................................... bitbang: Extend register_spi_bitbang_master() API with spi data This allows the users of register_spi_bitbang_master() API to pass their spi data into the API, and then the data can go further, into register_spi_master() API. BUG=b:185191942 TEST=builds Change-Id: I13e83ae74dbc3a3e79c84d1463683d360ff47bc0 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M bitbang_spi.c M developerbox_spi.c M mcp6x_spi.c M nicintel_spi.c M ogp_spi.c M pony_spi.c M programmer.h M rayer_spi.c 8 files changed, 13 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/90/54990/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index 85c867e..e595b16 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -96,6 +96,7 @@ struct bitbang_spi_master_data { const struct bitbang_spi_master *master; + void *spi_data; }; static int bitbang_spi_send_command(const struct flashctx *flash, @@ -146,7 +147,7 @@ return 0; } -int register_spi_bitbang_master(const struct bitbang_spi_master *master) +int register_spi_bitbang_master(const struct bitbang_spi_master *master, void *spi_data) { struct spi_master mst = spi_master_bitbang; /* If someone forgot to initialize a bitbang function, we catch it here. */ @@ -161,8 +162,10 @@ struct bitbang_spi_master_data *data = calloc(1, sizeof(struct bitbang_spi_master_data)); data->master = master; - mst.data = data; - register_spi_master(&mst, NULL); + if (spi_data) + data->spi_data = spi_data; + + register_spi_master(&mst, data); register_shutdown(bitbang_spi_shutdown, data); /* Only mess with the bus if we're sure nobody else uses it. */ diff --git a/developerbox_spi.c b/developerbox_spi.c index 4ff2fb6..4ccfaaa 100644 --- a/developerbox_spi.c +++ b/developerbox_spi.c @@ -158,7 +158,7 @@ if (register_shutdown(developerbox_spi_shutdown, NULL)) goto err_exit; - if (register_spi_bitbang_master(&bitbang_spi_master_cp210x)) + if (register_spi_bitbang_master(&bitbang_spi_master_cp210x, NULL)) goto err_exit; return 0; diff --git a/mcp6x_spi.c b/mcp6x_spi.c index b53d07b..543142b 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -151,7 +151,7 @@ (status >> MCP6X_SPI_GRANT) & 0x1); mcp_gpiostate = status & 0xff; - if (register_spi_bitbang_master(&bitbang_spi_master_mcp6x)) { + if (register_spi_bitbang_master(&bitbang_spi_master_mcp6x, NULL)) { /* This should never happen. */ msg_perr("MCP6X bitbang SPI master init failed!\n"); return 1; diff --git a/nicintel_spi.c b/nicintel_spi.c index 1173ef7..03df8ef 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -273,7 +273,7 @@ return 1; } - if (register_spi_bitbang_master(&bitbang_spi_master_nicintel)) + if (register_spi_bitbang_master(&bitbang_spi_master_nicintel, NULL)) return 1; return 0; diff --git a/ogp_spi.c b/ogp_spi.c index e603edb..7a22809 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -135,7 +135,7 @@ if (ogp_spibar == ERROR_PTR) return 1; - if (register_spi_bitbang_master(&bitbang_spi_master_ogp)) + if (register_spi_bitbang_master(&bitbang_spi_master_ogp, NULL)) return 1; return 0; diff --git a/pony_spi.c b/pony_spi.c index ed9d326..9e00b03 100644 --- a/pony_spi.c +++ b/pony_spi.c @@ -224,7 +224,7 @@ return 1; } - if (register_spi_bitbang_master(&bitbang_spi_master_pony)) { + if (register_spi_bitbang_master(&bitbang_spi_master_pony, NULL)) { return 1; } return 0; diff --git a/programmer.h b/programmer.h index 790fcc8..1874612 100644 --- a/programmer.h +++ b/programmer.h @@ -542,7 +542,7 @@ #endif /* bitbang_spi.c */ -int register_spi_bitbang_master(const struct bitbang_spi_master *master); +int register_spi_bitbang_master(const struct bitbang_spi_master *master, void *spi_data); /* buspirate_spi.c */ #if CONFIG_BUSPIRATE_SPI == 1 diff --git a/rayer_spi.c b/rayer_spi.c index cde008f..7b518c9 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -265,7 +265,7 @@ if (pinout->preinit) pinout->preinit(pinout); - if (register_spi_bitbang_master(&bitbang_spi_master_rayer)) + if (register_spi_bitbang_master(&bitbang_spi_master_rayer, NULL)) return 1; return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/54990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I13e83ae74dbc3a3e79c84d1463683d360ff47bc0 Gerrit-Change-Number: 54990 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: bitbang: Extend bitbang_spi_master functions to accept spi data
by Anastasia Klimchuk (Code Review) May 26, 2021

May 26, 2021

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54991 ) Change subject: bitbang: Extend bitbang_spi_master functions to accept spi data ...................................................................... bitbang: Extend bitbang_spi_master functions to accept spi data This way every bitbang spi master has access to its own spi data, and can use this data in all its functions. This patch only changes the signatures of functions. BUG=b:185191942 TEST=builds Change-Id: Id5722a43ce20feeed62630ad80e14df7744f9c02 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M bitbang_spi.c M developerbox_spi.c M mcp6x_spi.c M nicintel_spi.c M ogp_spi.c M pony_spi.c M programmer.h M rayer_spi.c 8 files changed, 52 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/91/54991/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index e595b16..601b7a6 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -24,44 +24,44 @@ /* Note that CS# is active low, so val=0 means the chip is active. */ static void bitbang_spi_set_cs(const struct bitbang_spi_master * const master, int val) { - master->set_cs(val); + master->set_cs(val, NULL); } static void bitbang_spi_set_sck(const struct bitbang_spi_master * const master, int val) { - master->set_sck(val); + master->set_sck(val, NULL); } static void bitbang_spi_request_bus(const struct bitbang_spi_master * const master) { if (master->request_bus) - master->request_bus(); + master->request_bus(NULL); } static void bitbang_spi_release_bus(const struct bitbang_spi_master * const master) { if (master->release_bus) - master->release_bus(); + master->release_bus(NULL); } static void bitbang_spi_set_sck_set_mosi(const struct bitbang_spi_master * const master, int sck, int mosi) { if (master->set_sck_set_mosi) { - master->set_sck_set_mosi(sck, mosi); + master->set_sck_set_mosi(sck, mosi, NULL); return; } - master->set_sck(sck); - master->set_mosi(mosi); + master->set_sck(sck, NULL); + master->set_mosi(mosi, NULL); } static int bitbang_spi_set_sck_get_miso(const struct bitbang_spi_master * const master, int sck) { if (master->set_sck_get_miso) - return master->set_sck_get_miso(sck); + return master->set_sck_get_miso(sck, NULL); - master->set_sck(sck); - return master->get_miso(); + master->set_sck(sck, NULL); + return master->get_miso(NULL); } static uint8_t bitbang_spi_read_byte(const struct bitbang_spi_master *master) diff --git a/developerbox_spi.c b/developerbox_spi.c index 4ccfaaa..e741890 100644 --- a/developerbox_spi.c +++ b/developerbox_spi.c @@ -94,27 +94,27 @@ msg_perr("Failed to read GPIO pins (%s)\n", libusb_error_name(res)); } -static void cp210x_bitbang_set_cs(int val) +static void cp210x_bitbang_set_cs(int val, void *spi_data) { cp210x_gpio_set(val << DEVELOPERBOX_SPI_CS, 1 << DEVELOPERBOX_SPI_CS); } -static void cp210x_bitbang_set_sck(int val) +static void cp210x_bitbang_set_sck(int val, void *spi_data) { cp210x_gpio_set(val << DEVELOPERBOX_SPI_SCK, 1 << DEVELOPERBOX_SPI_SCK); } -static void cp210x_bitbang_set_mosi(int val) +static void cp210x_bitbang_set_mosi(int val, void *spi_data) { cp210x_gpio_set(val << DEVELOPERBOX_SPI_MOSI, 1 << DEVELOPERBOX_SPI_MOSI); } -static int cp210x_bitbang_get_miso(void) +static int cp210x_bitbang_get_miso(void *spi_data) { return !!(cp210x_gpio_get() & (1 << DEVELOPERBOX_SPI_MISO)); } -static void cp210x_bitbang_set_sck_set_mosi(int sck, int mosi) +static void cp210x_bitbang_set_sck_set_mosi(int sck, int mosi, void *spi_data) { cp210x_gpio_set(sck << DEVELOPERBOX_SPI_SCK | mosi << DEVELOPERBOX_SPI_MOSI, 1 << DEVELOPERBOX_SPI_SCK | 1 << DEVELOPERBOX_SPI_MOSI); diff --git a/mcp6x_spi.c b/mcp6x_spi.c index 543142b..de44299 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -41,7 +41,7 @@ /* Cached value of last GPIO state. */ static uint8_t mcp_gpiostate; -static void mcp6x_request_spibus(void) +static void mcp6x_request_spibus(void *spi_data) { mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); mcp_gpiostate |= 1 << MCP6X_SPI_REQUEST; @@ -54,34 +54,34 @@ mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); } -static void mcp6x_release_spibus(void) +static void mcp6x_release_spibus(void *spi_data) { mcp_gpiostate &= ~(1 << MCP6X_SPI_REQUEST); mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } -static void mcp6x_bitbang_set_cs(int val) +static void mcp6x_bitbang_set_cs(int val, void *spi_data) { mcp_gpiostate &= ~(1 << MCP6X_SPI_CS); mcp_gpiostate |= (val << MCP6X_SPI_CS); mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } -static void mcp6x_bitbang_set_sck(int val) +static void mcp6x_bitbang_set_sck(int val, void *spi_data) { mcp_gpiostate &= ~(1 << MCP6X_SPI_SCK); mcp_gpiostate |= (val << MCP6X_SPI_SCK); mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } -static void mcp6x_bitbang_set_mosi(int val) +static void mcp6x_bitbang_set_mosi(int val, void *spi_data) { mcp_gpiostate &= ~(1 << MCP6X_SPI_MOSI); mcp_gpiostate |= (val << MCP6X_SPI_MOSI); mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); } -static int mcp6x_bitbang_get_miso(void) +static int mcp6x_bitbang_get_miso(void *spi_data) { mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); return (mcp_gpiostate >> MCP6X_SPI_MISO) & 0x1; diff --git a/nicintel_spi.c b/nicintel_spi.c index 03df8ef..9e97840 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -107,7 +107,7 @@ {0}, }; -static void nicintel_request_spibus(void) +static void nicintel_request_spibus(void *spi_data) { uint32_t tmp; @@ -119,7 +119,7 @@ while (!(pci_mmio_readl(nicintel_spibar + FLA) & BIT(FL_GNT))) ; } -static void nicintel_release_spibus(void) +static void nicintel_release_spibus(void *spi_data) { uint32_t tmp; @@ -128,7 +128,7 @@ pci_mmio_writel(tmp, nicintel_spibar + FLA); } -static void nicintel_bitbang_set_cs(int val) +static void nicintel_bitbang_set_cs(int val, void *spi_data) { uint32_t tmp; @@ -138,7 +138,7 @@ pci_mmio_writel(tmp, nicintel_spibar + FLA); } -static void nicintel_bitbang_set_sck(int val) +static void nicintel_bitbang_set_sck(int val, void *spi_data) { uint32_t tmp; @@ -148,7 +148,7 @@ pci_mmio_writel(tmp, nicintel_spibar + FLA); } -static void nicintel_bitbang_set_mosi(int val) +static void nicintel_bitbang_set_mosi(int val, void *spi_data) { uint32_t tmp; @@ -158,7 +158,7 @@ pci_mmio_writel(tmp, nicintel_spibar + FLA); } -static int nicintel_bitbang_get_miso(void) +static int nicintel_bitbang_get_miso(void *spi_data) { uint32_t tmp; diff --git a/ogp_spi.c b/ogp_spi.c index 7a22809..01694ca 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -49,32 +49,32 @@ {0}, }; -static void ogp_request_spibus(void) +static void ogp_request_spibus(void *spi_data) { pci_mmio_writel(1, ogp_spibar + ogp_reg_sel); } -static void ogp_release_spibus(void) +static void ogp_release_spibus(void *spi_data) { pci_mmio_writel(0, ogp_spibar + ogp_reg_sel); } -static void ogp_bitbang_set_cs(int val) +static void ogp_bitbang_set_cs(int val, void *spi_data) { pci_mmio_writel(val, ogp_spibar + ogp_reg__ce); } -static void ogp_bitbang_set_sck(int val) +static void ogp_bitbang_set_sck(int val, void *spi_data) { pci_mmio_writel(val, ogp_spibar + ogp_reg_sck); } -static void ogp_bitbang_set_mosi(int val) +static void ogp_bitbang_set_mosi(int val, void *spi_data) { pci_mmio_writel(val, ogp_spibar + ogp_reg_siso); } -static int ogp_bitbang_get_miso(void) +static int ogp_bitbang_get_miso(void *spi_data) { uint32_t tmp; diff --git a/pony_spi.c b/pony_spi.c index 9e00b03..940cae1 100644 --- a/pony_spi.c +++ b/pony_spi.c @@ -56,7 +56,7 @@ /* Pins for slave->master direction */ static int pony_negate_miso = 0; -static void pony_bitbang_set_cs(int val) +static void pony_bitbang_set_cs(int val, void *spi_data) { if (pony_negate_cs) val ^= 1; @@ -64,7 +64,7 @@ sp_set_pin(PIN_TXD, val); } -static void pony_bitbang_set_sck(int val) +static void pony_bitbang_set_sck(int val, void *spi_data) { if (pony_negate_sck) val ^= 1; @@ -72,7 +72,7 @@ sp_set_pin(PIN_RTS, val); } -static void pony_bitbang_set_mosi(int val) +static void pony_bitbang_set_mosi(int val, void *spi_data) { if (pony_negate_mosi) val ^= 1; @@ -80,7 +80,7 @@ sp_set_pin(PIN_DTR, val); } -static int pony_bitbang_get_miso(void) +static int pony_bitbang_get_miso(void *spi_data) { int tmp = sp_get_pin(PIN_CTS); @@ -192,9 +192,9 @@ /* * Detect if there is a compatible hardware programmer connected. */ - pony_bitbang_set_cs(1); - pony_bitbang_set_sck(1); - pony_bitbang_set_mosi(1); + pony_bitbang_set_cs(1, NULL); + pony_bitbang_set_sck(1, NULL); + pony_bitbang_set_mosi(1, NULL); switch (type) { case TYPE_AJAWE: diff --git a/programmer.h b/programmer.h index 1874612..a0ff6bc 100644 --- a/programmer.h +++ b/programmer.h @@ -182,15 +182,15 @@ struct bitbang_spi_master { /* Note that CS# is active low, so val=0 means the chip is active. */ - void (*set_cs) (int val); - void (*set_sck) (int val); - void (*set_mosi) (int val); - int (*get_miso) (void); - void (*request_bus) (void); - void (*release_bus) (void); + void (*set_cs) (int val, void *spi_data); + void (*set_sck) (int val, void *spi_data); + void (*set_mosi) (int val, void *spi_data); + int (*get_miso) (void *spi_data); + void (*request_bus) (void *spi_data); + void (*release_bus) (void *spi_data); /* optional functions to optimize xfers */ - void (*set_sck_set_mosi) (int sck, int mosi); - int (*set_sck_get_miso) (int sck); + void (*set_sck_set_mosi) (int sck, int mosi, void *spi_data); + int (*set_sck_get_miso) (int sck, void *spi_data); /* Length of half a clock period in usecs. */ unsigned int half_period; }; diff --git a/rayer_spi.c b/rayer_spi.c index 7b518c9..8401cda 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -160,28 +160,28 @@ static const struct rayer_pinout *pinout = NULL; -static void rayer_bitbang_set_cs(int val) +static void rayer_bitbang_set_cs(int val, void *spi_data) { lpt_outbyte &= ~(1 << pinout->cs_bit); lpt_outbyte |= (val << pinout->cs_bit); OUTB(lpt_outbyte, lpt_iobase); } -static void rayer_bitbang_set_sck(int val) +static void rayer_bitbang_set_sck(int val, void *spi_data) { lpt_outbyte &= ~(1 << pinout->sck_bit); lpt_outbyte |= (val << pinout->sck_bit); OUTB(lpt_outbyte, lpt_iobase); } -static void rayer_bitbang_set_mosi(int val) +static void rayer_bitbang_set_mosi(int val, void *spi_data) { lpt_outbyte &= ~(1 << pinout->mosi_bit); lpt_outbyte |= (val << pinout->mosi_bit); OUTB(lpt_outbyte, lpt_iobase); } -static int rayer_bitbang_get_miso(void) +static int rayer_bitbang_get_miso(void *spi_data) { uint8_t tmp; -- To view, visit https://review.coreboot.org/c/flashrom/+/54991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id5722a43ce20feeed62630ad80e14df7744f9c02 Gerrit-Change-Number: 54991 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: bitbang_spi.c: Rename usages of bitbang_spi_master into master
by Anastasia Klimchuk (Code Review) May 26, 2021

May 26, 2021

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54989 ) Change subject: bitbang_spi.c: Rename usages of bitbang_spi_master into master ...................................................................... bitbang_spi.c: Rename usages of bitbang_spi_master into master There were two different things in this file, but both of them were called "mst" and it was confusing. Now the variables of type bitbang_spi_master are called "master", including the member of bitbang_spi_master_data. The variables of type spi_master are called mst. BUG=b:185191942 TEST=builds Change-Id: I2fdbdc2daedde7f6996642cfbb2d34ec06a89621 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M bitbang_spi.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/89/54989/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index bb89071..85c867e 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -95,7 +95,7 @@ } struct bitbang_spi_master_data { - const struct bitbang_spi_master *mst; + const struct bitbang_spi_master *master; }; static int bitbang_spi_send_command(const struct flashctx *flash, @@ -105,7 +105,7 @@ { unsigned int i; const struct bitbang_spi_master_data *data = flash->mst->spi.data; - const struct bitbang_spi_master *master = data->mst; + const struct bitbang_spi_master *master = data->master; /* FIXME: Run bitbang_spi_request_bus here or in programmer init? * Requesting and releasing the SPI bus is handled in here to allow the @@ -160,7 +160,7 @@ } struct bitbang_spi_master_data *data = calloc(1, sizeof(struct bitbang_spi_master_data)); - data->mst = master; + data->master = master; mst.data = data; register_spi_master(&mst, NULL); register_shutdown(bitbang_spi_shutdown, data); -- To view, visit https://review.coreboot.org/c/flashrom/+/54989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2fdbdc2daedde7f6996642cfbb2d34ec06a89621 Gerrit-Change-Number: 54989 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: add support for Winbond W25Q01JV
by David Bartley (Code Review) May 26, 2021

May 26, 2021

David Bartley has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54968 ) Change subject: flashchips: add support for Winbond W25Q01JV ...................................................................... flashchips: add support for Winbond W25Q01JV Signed-off-by: David Bartley <andareed(a)gmail.com> Change-Id: If369409419332070c1fed96ce0e96b7cfe42c169 --- M flashchips.c M flashchips.h 2 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/68/54968/1 diff --git a/flashchips.c b/flashchips.c index 007bcc9..e83e39d 100644 --- a/flashchips.c +++ b/flashchips.c @@ -17742,6 +17742,52 @@ { .vendor = "Winbond", + .name = "W25Q501V", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q01JV, + .total_size = 128 * 1024, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + /* Full chip erase is fastest, typically takes 200s */ + { + .eraseblocks = { {128 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {128 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_20, + } + }, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + + { + .vendor = "Winbond", .name = "W25Q64.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, diff --git a/flashchips.h b/flashchips.h index b6b75c8..3cd459d 100644 --- a/flashchips.h +++ b/flashchips.h @@ -965,6 +965,7 @@ #define WINBOND_NEX_W25Q128_V 0x4018 /* W25Q128BV; W25Q128FV in SPI mode (default) */ #define WINBOND_NEX_W25Q256_V 0x4019 /* W25Q256FV or W25Q256JV_Q (QE=1) */ #define WINBOND_NEX_W25Q512JV 0x4020 /* W25Q512JV */ +#define WINBOND_NEX_W25Q01JV 0x4021 /* W25Q01JV */ #define WINBOND_NEX_W25Q20_W 0x5012 /* W25Q20BW */ #define WINBOND_NEX_W25Q40BW 0x5013 /* W25Q40BW */ #define WINBOND_NEX_W25Q80BW 0x5014 /* W25Q80BW */ -- To view, visit https://review.coreboot.org/c/flashrom/+/54968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If369409419332070c1fed96ce0e96b7cfe42c169 Gerrit-Change-Number: 54968 Gerrit-PatchSet: 1 Gerrit-Owner: David Bartley <andareed(a)gmail.com> Gerrit-MessageType: newchange

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