May 2021 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: nicintel_spi.c: Refactor singleton states into reentrant pattern
by Angel Pons (Code Review) 27 May '21

27 May '21

Attention is currently required from: Nico Huber, Edward O'Callaghan, Anastasia Klimchuk. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54995 ) Change subject: nicintel_spi.c: Refactor singleton states into reentrant pattern ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File nicintel_spi.c: https://review.coreboot.org/c/flashrom/+/54995/comment/13ac18ef_c9812483 PS1, Line 79: nicintel_ I'd drop the `nicintel_` prefix. This patch already adds `data->` to the code. -- To view, visit https://review.coreboot.org/c/flashrom/+/54995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I385d3ced19dfe6453ccc4128a7b792c2dce3a449 Gerrit-Change-Number: 54995 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 27 May 2021 10:28:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: mcp6x_spi.c: Refactor singleton states into reentrant pattern
by Angel Pons (Code Review) 27 May '21

27 May '21

Attention is currently required from: Nico Huber, Edward O'Callaghan, Anastasia Klimchuk. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54994 ) Change subject: mcp6x_spi.c: Refactor singleton states into reentrant pattern ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File mcp6x_spi.c: https://review.coreboot.org/c/flashrom/+/54994/comment/dc53e92c_faf2f831 PS1, Line 42: uint8_t mcp_gpiostate; I'd rename the struct members to drop the `mcp6x` and `mcp` prefixes. Since this patch already touches the code, one might as well do it as part of this commit. -- To view, visit https://review.coreboot.org/c/flashrom/+/54994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia02c1cb9d36fb7b15bb7e09b769d8969c08c2bd5 Gerrit-Change-Number: 54994 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 27 May 2021 10:24:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: bitbang_spi.c: Rename usages of bitbang_spi_master into master
by Edward O'Callaghan (Code Review) 27 May '21

27 May '21

Attention is currently required from: Nico Huber, Angel Pons, Anastasia Klimchuk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54989 ) Change subject: bitbang_spi.c: Rename usages of bitbang_spi_master into master ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/54989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2fdbdc2daedde7f6996642cfbb2d34ec06a89621 Gerrit-Change-Number: 54989 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 27 May 2021 10:19:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: developerbox_spi.c: Refactor singleton states into reentrant pattern
by Angel Pons (Code Review) 27 May '21

27 May '21

Attention is currently required from: Nico Huber, Edward O'Callaghan, Anastasia Klimchuk. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54993 ) Change subject: developerbox_spi.c: Refactor singleton states into reentrant pattern ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/54993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I84bf0cffa4a14e58103bdb1e7e65ec2475344f12 Gerrit-Change-Number: 54993 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 27 May 2021 10:19:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: bitbang: Extend register_spi_bitbang_master() API with spi data
by Edward O'Callaghan (Code Review) 27 May '21

27 May '21

Attention is currently required from: Nico Huber, Angel Pons, Anastasia Klimchuk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54990 ) Change subject: bitbang: Extend register_spi_bitbang_master() API with spi data ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File bitbang_spi.c: https://review.coreboot.org/c/flashrom/+/54990/comment/5cff25e5_2a184792 PS1, Line 164: mst.data = data; : register_spi_master(&mst, NULL); I feel like the removal of `mst.data = data;` and instead passing data directly into register_spi_master() is itself a patch. small granted but none the less technically not within the scope of this patch. -- To view, visit https://review.coreboot.org/c/flashrom/+/54990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I13e83ae74dbc3a3e79c84d1463683d360ff47bc0 Gerrit-Change-Number: 54990 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 27 May 2021 10:19:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: bitbang: Extend bitbang_spi_master functions to accept spi data
by Edward O'Callaghan (Code Review) 27 May '21

27 May '21

Attention is currently required from: Nico Huber, Angel Pons, Anastasia Klimchuk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54991 ) Change subject: bitbang: Extend bitbang_spi_master functions to accept spi data ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/54991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id5722a43ce20feeed62630ad80e14df7744f9c02 Gerrit-Change-Number: 54991 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 27 May 2021 10:15:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips: add support for Winbond W25Q01JV
by Angel Pons (Code Review) 27 May '21

27 May '21

Attention is currently required from: David Bartley, Nico Huber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54968 ) Change subject: flashchips: add support for Winbond W25Q01JV ...................................................................... Patch Set 1: (6 comments) File flashchips.c: https://review.coreboot.org/c/flashrom/+/54968/comment/e9563905_4d8bc47c PS1, Line 17745: W25Q501V Flash chip entries are sorted alphabetically by vendor and name. This one should be placed between `W25P80` and `W25Q128.V`. https://review.coreboot.org/c/flashrom/+/54968/comment/df90eb13_fb1880d9 PS1, Line 17745: 5 The `5` seems spurious? https://review.coreboot.org/c/flashrom/+/54968/comment/c8b5bb4b_ce6abeb1 PS1, Line 17757: /* Full chip erase is fastest, typically takes 200s */ Block erasers for the other flash chip entries are intentionally sorted in ascending block size. Please keep this ordering. # Context When writing, flashrom first reads the old flash chip contents and only erases/writes the blocks which have changed. This significantly reduces flashing time when only a part of the data needs to be rewritten. This behavior is also useful when using a layout file to only rewrite specific sections of the flash chip. However, flashrom currently always uses the first block eraser, and only falls back to the other block erasers if there's an error. Dynamically choosing the best block erasers for each case would be great to have, but someone needs to implement it. Patches are welcome! https://review.coreboot.org/c/flashrom/+/54968/comment/9aa66627_05ce4e8c PS1, Line 17781: spi_prettyprint_status_register_plain spi_prettyprint_status_register_bp3_srwd https://review.coreboot.org/c/flashrom/+/54968/comment/bf58c60a_28a6a207 PS1, Line 17782: spi_disable_blockprotect spi_disable_blockprotect_bp3_srwd https://review.coreboot.org/c/flashrom/+/54968/comment/f6300f56_5c9ea10b PS1, Line 17788: nit: use only one blank line (there's two right now) -- To view, visit https://review.coreboot.org/c/flashrom/+/54968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If369409419332070c1fed96ce0e96b7cfe42c169 Gerrit-Change-Number: 54968 Gerrit-PatchSet: 1 Gerrit-Owner: David Bartley <andareed(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: David Bartley <andareed(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 27 May 2021 09:32:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: buspirate_spi.c: Refactor singleton states into reentrant pattern
by Anastasia Klimchuk (Code Review) 27 May '21

27 May '21

Attention is currently required from: Nico Huber, Edward O'Callaghan, Angel Pons. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/52958 ) Change subject: buspirate_spi.c: Refactor singleton states into reentrant pattern ...................................................................... Patch Set 3: (2 comments) File buspirate_spi.c: https://review.coreboot.org/c/flashrom/+/52958/comment/21f643f3_6ce3fdfa PS3, Line 58: unsigned char **bp_commbuf > I'd just pass a pointer to `struct bp_spi_data` I was considering the idea to pass a pointer to `struct bp_spi_data` into buspirate_commbuf_grow but it didn't look great [to me] in init function. Init function is quite long, and I wanted to use local variables for bp_commbuf and bp_commbufsize in init function to minimize diffs and noise. But at the same time, buspirate_commbuf_grow is called twice in the middle of init function, and each of those calls can change the pointer and the size. So, if I would need to pass data struct into buspirate_commbuf_grow, and also using local variables during init, that would mean: assigning local values into data, calling buspirate_commbuf_grow, and then assigning updated values from data into local variables. https://review.coreboot.org/c/flashrom/+/52958/comment/f8d568a4_c90df3f2 PS3, Line 221: unsigned char *const bp_commbuf = bp_data->bp_commbuf; > I thought that buspirate_commbuf_grow can change the pointer, and I can have this local variable as […] As I learned today from C standard, realloc can change the pointer. And because I want this to be a constant pointer, I only can define it after the call to buspirate_commbuf_grow (because it does realloc). -- To view, visit https://review.coreboot.org/c/flashrom/+/52958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I418bbfff15fb126b042fbc9be09dbf59f4d243b8 Gerrit-Change-Number: 52958 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 27 May 2021 02:43:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: par_masters: Reshuffle to remove forward declarations
by Edward O'Callaghan (Code Review) 27 May '21

27 May '21

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/54873 ) Change subject: par_masters: Reshuffle to remove forward declarations ...................................................................... par_masters: Reshuffle to remove forward declarations Dispense with all these forward declarations by way of ordering. Just deal with all the par_masters in one go to be over and done with. BUG=none BRANCH=none TEST=builds Change-Id: I88e89992380195fee7c9de7ec57502ab980ec5df Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54873 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M atahpt.c M atapromise.c M atavia.c M gfxnvidia.c M it8212.c M nic3com.c M nicintel.c M nicnatsemi.c M nicrealtek.c M satamv.c M satasii.c 11 files changed, 258 insertions(+), 293 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Anastasia Klimchuk: Looks good to me, but someone else must approve diff --git a/atahpt.c b/atahpt.c index 620e894..327d74b 100644 --- a/atahpt.c +++ b/atahpt.c @@ -40,9 +40,19 @@ }; static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr); + chipaddr addr) +{ + OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + OUTB(val, io_base_addr + BIOS_ROM_DATA); +} + static uint8_t atahpt_chip_readb(const struct flashctx *flash, - const chipaddr addr); + const chipaddr addr) +{ + OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + return INB(io_base_addr + BIOS_ROM_DATA); +} + static const struct par_master par_master_atahpt = { .chip_readb = atahpt_chip_readb, .chip_readw = fallback_chip_readw, @@ -80,20 +90,6 @@ return 0; } -static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr) -{ - OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); - OUTB(val, io_base_addr + BIOS_ROM_DATA); -} - -static uint8_t atahpt_chip_readb(const struct flashctx *flash, - const chipaddr addr) -{ - OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); - return INB(io_base_addr + BIOS_ROM_DATA); -} - #else #error PCI port I/O access is not supported on this architecture yet. #endif diff --git a/atapromise.c b/atapromise.c index f32bdb4..4941a7c 100644 --- a/atapromise.c +++ b/atapromise.c @@ -53,20 +53,6 @@ {0}, }; -static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); -static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr); - -static const struct par_master par_master_atapromise = { - .chip_readb = atapromise_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = atapromise_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, -}; - void *atapromise_map(const char *descr, uintptr_t phys_addr, size_t len) { /* In case fallback_map ever returns something other than NULL. */ @@ -106,6 +92,32 @@ } } +static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) +{ + uint32_t data; + + atapromise_limit_chip(flash->chip); + data = (rom_base_addr + (addr & ADDR_MASK)) << 8 | val; + OUTL(data, io_base_addr + 0x14); +} + +static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr) +{ + atapromise_limit_chip(flash->chip); + return pci_mmio_readb(atapromise_bar + (addr & ADDR_MASK)); +} + +static const struct par_master par_master_atapromise = { + .chip_readb = atapromise_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = atapromise_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + int atapromise_init(void) { struct pci_dev *dev = NULL; @@ -150,21 +162,6 @@ return 0; } -static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) -{ - uint32_t data; - - atapromise_limit_chip(flash->chip); - data = (rom_base_addr + (addr & ADDR_MASK)) << 8 | val; - OUTL(data, io_base_addr + 0x14); -} - -static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr) -{ - atapromise_limit_chip(flash->chip); - return pci_mmio_readb(atapromise_bar + (addr & ADDR_MASK)); -} - #else #error PCI port I/O access is not supported on this architecture yet. #endif diff --git a/atavia.c b/atavia.c index e04950a..8045e1b 100644 --- a/atavia.c +++ b/atavia.c @@ -54,19 +54,6 @@ {0}, }; -static void atavia_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); -static uint8_t atavia_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_master lpc_master_atavia = { - .chip_readb = atavia_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = atavia_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, -}; - static void *atavia_offset = NULL; static struct pci_dev *dev = NULL; @@ -119,6 +106,43 @@ return (atavia_offset != 0) ? atavia_offset : (void *)phys_addr; } +static void atavia_chip_writeb(const struct flashctx *flash, uint8_t val, const chipaddr addr) +{ + msg_pspew("%s: 0x%02x to 0x%*" PRIxPTR ".\n", __func__, val, PRIxPTR_WIDTH, addr); + pci_write_long(dev, BROM_ADDR, (addr & ~3)); + pci_write_long(dev, BROM_DATA, val << BYTE_OFFSET(addr)); + pci_write_byte(dev, BROM_ACCESS, BROM_TRIGGER | BROM_WRITE | ENABLE_BYTE(addr)); + + if (!atavia_ready(dev)) { + msg_perr("not ready after write\n"); + } +} + +static uint8_t atavia_chip_readb(const struct flashctx *flash, const chipaddr addr) +{ + pci_write_long(dev, BROM_ADDR, (addr & ~3)); + pci_write_byte(dev, BROM_ACCESS, BROM_TRIGGER | ENABLE_BYTE(addr)); + + if (!atavia_ready(dev)) { + msg_perr("not ready after read\n"); + } + + uint8_t val = (pci_read_long(dev, BROM_DATA) >> BYTE_OFFSET(addr)) & 0xff; + msg_pspew("%s: 0x%02x from 0x%*" PRIxPTR ".\n", __func__, val, PRIxPTR_WIDTH, addr); + return val; +} + +static const struct par_master lpc_master_atavia = { + .chip_readb = atavia_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = atavia_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + int atavia_init(void) { char *arg = extract_programmer_param("offset"); @@ -164,29 +188,3 @@ return 0; } - -static void atavia_chip_writeb(const struct flashctx *flash, uint8_t val, const chipaddr addr) -{ - msg_pspew("%s: 0x%02x to 0x%*" PRIxPTR ".\n", __func__, val, PRIxPTR_WIDTH, addr); - pci_write_long(dev, BROM_ADDR, (addr & ~3)); - pci_write_long(dev, BROM_DATA, val << BYTE_OFFSET(addr)); - pci_write_byte(dev, BROM_ACCESS, BROM_TRIGGER | BROM_WRITE | ENABLE_BYTE(addr)); - - if (!atavia_ready(dev)) { - msg_perr("not ready after write\n"); - } -} - -static uint8_t atavia_chip_readb(const struct flashctx *flash, const chipaddr addr) -{ - pci_write_long(dev, BROM_ADDR, (addr & ~3)); - pci_write_byte(dev, BROM_ACCESS, BROM_TRIGGER | ENABLE_BYTE(addr)); - - if (!atavia_ready(dev)) { - msg_perr("not ready after read\n"); - } - - uint8_t val = (pci_read_long(dev, BROM_DATA) >> BYTE_OFFSET(addr)) & 0xff; - msg_pspew("%s: 0x%02x from 0x%*" PRIxPTR ".\n", __func__, val, PRIxPTR_WIDTH, addr); - return val; -} diff --git a/gfxnvidia.c b/gfxnvidia.c index fe6f982..6b1efcf 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -59,9 +59,17 @@ }; static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr); + chipaddr addr) +{ + pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); +} + static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash, - const chipaddr addr); + const chipaddr addr) +{ + return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); +} + static const struct par_master par_master_gfxnvidia = { .chip_readb = gfxnvidia_chip_readb, .chip_readw = fallback_chip_readw, @@ -107,15 +115,3 @@ return 0; } - -static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr) -{ - pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); -} - -static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash, - const chipaddr addr) -{ - return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK)); -} diff --git a/it8212.c b/it8212.c index 2f2d43e..7c66a59 100644 --- a/it8212.c +++ b/it8212.c @@ -32,8 +32,16 @@ #define IT8212_MEMMAP_SIZE (128 * 1024) #define IT8212_MEMMAP_MASK (IT8212_MEMMAP_SIZE - 1) -static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); -static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr addr); +static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) +{ + pci_mmio_writeb(val, it8212_bar + (addr & IT8212_MEMMAP_MASK)); +} + +static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr addr) +{ + return pci_mmio_readb(it8212_bar + (addr & IT8212_MEMMAP_MASK)); +} + static const struct par_master par_master_it8212 = { .chip_readb = it8212_chip_readb, .chip_readw = fallback_chip_readw, @@ -70,13 +78,3 @@ register_par_master(&par_master_it8212, BUS_PARALLEL, NULL); return 0; } - -static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) -{ - pci_mmio_writeb(val, it8212_bar + (addr & IT8212_MEMMAP_MASK)); -} - -static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr addr) -{ - return pci_mmio_readb(it8212_bar + (addr & IT8212_MEMMAP_MASK)); -} diff --git a/nic3com.c b/nic3com.c index 6ff91e7..d60b03c 100644 --- a/nic3com.c +++ b/nic3com.c @@ -54,9 +54,19 @@ }; static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr); + chipaddr addr) +{ + OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + OUTB(val, io_base_addr + BIOS_ROM_DATA); +} + static uint8_t nic3com_chip_readb(const struct flashctx *flash, - const chipaddr addr); + const chipaddr addr) +{ + OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); + return INB(io_base_addr + BIOS_ROM_DATA); +} + static const struct par_master par_master_nic3com = { .chip_readb = nic3com_chip_readb, .chip_readw = fallback_chip_readw, @@ -125,20 +135,6 @@ return 0; } -static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr) -{ - OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); - OUTB(val, io_base_addr + BIOS_ROM_DATA); -} - -static uint8_t nic3com_chip_readb(const struct flashctx *flash, - const chipaddr addr) -{ - OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); - return INB(io_base_addr + BIOS_ROM_DATA); -} - #else #error PCI port I/O access is not supported on this architecture yet. #endif diff --git a/nicintel.c b/nicintel.c index afd2682..3d324da 100644 --- a/nicintel.c +++ b/nicintel.c @@ -41,9 +41,17 @@ #define CSR_FCR 0x0c static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr); + chipaddr addr) +{ + pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); +} + static uint8_t nicintel_chip_readb(const struct flashctx *flash, - const chipaddr addr); + const chipaddr addr) +{ + return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); +} + static const struct par_master par_master_nicintel = { .chip_readb = nicintel_chip_readb, .chip_readw = fallback_chip_readw, @@ -103,15 +111,3 @@ return 0; } - -static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr) -{ - pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); -} - -static uint8_t nicintel_chip_readb(const struct flashctx *flash, - const chipaddr addr) -{ - return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK)); -} diff --git a/nicnatsemi.c b/nicnatsemi.c index 77b5440..56297fe 100644 --- a/nicnatsemi.c +++ b/nicnatsemi.c @@ -35,9 +35,35 @@ }; static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr); + chipaddr addr) +{ + OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR); + /* + * The datasheet requires 32 bit accesses to this register, but it seems + * that requirement might only apply if the register is memory mapped. + * Bits 8-31 of this register are apparently don't care, and if this + * register is I/O port mapped, 8 bit accesses to the lowest byte of the + * register seem to work fine. Due to that, we ignore the advice in the + * data sheet. + */ + OUTB(val, io_base_addr + BOOT_ROM_DATA); +} + static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash, - const chipaddr addr); + const chipaddr addr) +{ + OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR); + /* + * The datasheet requires 32 bit accesses to this register, but it seems + * that requirement might only apply if the register is memory mapped. + * Bits 8-31 of this register are apparently don't care, and if this + * register is I/O port mapped, 8 bit accesses to the lowest byte of the + * register seem to work fine. Due to that, we ignore the advice in the + * data sheet. + */ + return INB(io_base_addr + BOOT_ROM_DATA); +} + static const struct par_master par_master_nicnatsemi = { .chip_readb = nicnatsemi_chip_readb, .chip_readw = fallback_chip_readw, @@ -76,36 +102,6 @@ return 0; } -static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr) -{ - OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR); - /* - * The datasheet requires 32 bit accesses to this register, but it seems - * that requirement might only apply if the register is memory mapped. - * Bits 8-31 of this register are apparently don't care, and if this - * register is I/O port mapped, 8 bit accesses to the lowest byte of the - * register seem to work fine. Due to that, we ignore the advice in the - * data sheet. - */ - OUTB(val, io_base_addr + BOOT_ROM_DATA); -} - -static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash, - const chipaddr addr) -{ - OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR); - /* - * The datasheet requires 32 bit accesses to this register, but it seems - * that requirement might only apply if the register is memory mapped. - * Bits 8-31 of this register are apparently don't care, and if this - * register is I/O port mapped, 8 bit accesses to the lowest byte of the - * register seem to work fine. Due to that, we ignore the advice in the - * data sheet. - */ - return INB(io_base_addr + BOOT_ROM_DATA); -} - #else #error PCI port I/O access is not supported on this architecture yet. #endif diff --git a/nicrealtek.c b/nicrealtek.c index 2208179..788c088 100644 --- a/nicrealtek.c +++ b/nicrealtek.c @@ -35,8 +35,44 @@ {0}, }; -static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); -static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr); +static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) +{ + /* Output addr and data, set WE to 0, set OE to 1, set CS to 0, + * enable software access. + */ + OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24), + io_base_addr + bios_rom_addr); + /* Output addr and data, set WE to 1, set OE to 1, set CS to 1, + * enable software access. + */ + OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24), + io_base_addr + bios_rom_addr); +} + +static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr) +{ + uint8_t val; + + /* FIXME: Can we skip reading the old data and simply use 0? */ + /* Read old data. */ + val = INB(io_base_addr + bios_rom_data); + /* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0, + * enable software access. + */ + OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24), + io_base_addr + bios_rom_addr); + + /* Read new data. */ + val = INB(io_base_addr + bios_rom_data); + /* Output addr and new data, set WE to 1, set OE to 1, set CS to 1, + * enable software access. + */ + OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24), + io_base_addr + bios_rom_addr); + + return val; +} + static const struct par_master par_master_nicrealtek = { .chip_readb = nicrealtek_chip_readb, .chip_readw = fallback_chip_readw, @@ -91,44 +127,6 @@ return 0; } -static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) -{ - /* Output addr and data, set WE to 0, set OE to 1, set CS to 0, - * enable software access. - */ - OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24), - io_base_addr + bios_rom_addr); - /* Output addr and data, set WE to 1, set OE to 1, set CS to 1, - * enable software access. - */ - OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24), - io_base_addr + bios_rom_addr); -} - -static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr) -{ - uint8_t val; - - /* FIXME: Can we skip reading the old data and simply use 0? */ - /* Read old data. */ - val = INB(io_base_addr + bios_rom_data); - /* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0, - * enable software access. - */ - OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24), - io_base_addr + bios_rom_addr); - - /* Read new data. */ - val = INB(io_base_addr + bios_rom_data); - /* Output addr and new data, set WE to 1, set OE to 1, set CS to 1, - * enable software access. - */ - OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24), - io_base_addr + bios_rom_addr); - - return val; -} - #else #error PCI port I/O access is not supported on this architecture yet. #endif diff --git a/satamv.c b/satamv.c index 2640b78..30b7c34 100644 --- a/satamv.c +++ b/satamv.c @@ -38,10 +38,41 @@ #define PCI_BAR2_CONTROL 0x00c08 #define GPIO_PORT_CONTROL 0x104f0 +/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function. + * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O). + * This code only supports indirect accesses for now. + */ + +/* Indirect access to via the I/O BAR1. */ +static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr) +{ + /* 0x80000000 selects BAR2 for remapping. */ + OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); + OUTB(val, mv_iobar + 0x80 + (addr & 0x3)); +} + +/* Indirect access to via the I/O BAR1. */ +static uint8_t satamv_indirect_chip_readb(const chipaddr addr) +{ + /* 0x80000000 selects BAR2 for remapping. */ + OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); + return INB(mv_iobar + 0x80 + (addr & 0x3)); +} + +/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr); + chipaddr addr) +{ + satamv_indirect_chip_writeb(val, addr); +} + +/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ static uint8_t satamv_chip_readb(const struct flashctx *flash, - const chipaddr addr); + const chipaddr addr) +{ + return satamv_indirect_chip_readb(addr); +} + static const struct par_master par_master_satamv = { .chip_readb = satamv_chip_readb, .chip_readw = fallback_chip_readw, @@ -153,41 +184,6 @@ return 0; } -/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function. - * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O). - * This code only supports indirect accesses for now. - */ - -/* Indirect access to via the I/O BAR1. */ -static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr) -{ - /* 0x80000000 selects BAR2 for remapping. */ - OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); - OUTB(val, mv_iobar + 0x80 + (addr & 0x3)); -} - -/* Indirect access to via the I/O BAR1. */ -static uint8_t satamv_indirect_chip_readb(const chipaddr addr) -{ - /* 0x80000000 selects BAR2 for remapping. */ - OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar); - return INB(mv_iobar + 0x80 + (addr & 0x3)); -} - -/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ -static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr) -{ - satamv_indirect_chip_writeb(val, addr); -} - -/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */ -static uint8_t satamv_chip_readb(const struct flashctx *flash, - const chipaddr addr) -{ - return satamv_indirect_chip_readb(addr); -} - #else #error PCI port I/O access is not supported on this architecture yet. #endif diff --git a/satasii.c b/satasii.c index c9dfdad..0d22650 100644 --- a/satasii.c +++ b/satasii.c @@ -37,19 +37,6 @@ {0}, }; -static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); -static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_master par_master_satasii = { - .chip_readb = satasii_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = satasii_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, -}; - static uint32_t satasii_wait_done(void) { uint32_t ctrl_reg; @@ -64,6 +51,48 @@ return ctrl_reg; } +static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) +{ + uint32_t data_reg; + uint32_t ctrl_reg = satasii_wait_done(); + + /* Mask out unused/reserved bits, set writes and start transaction. */ + ctrl_reg &= 0xfcf80000; + ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); + + data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val; + pci_mmio_writel(data_reg, (sii_bar + 4)); + pci_mmio_writel(ctrl_reg, sii_bar); + + satasii_wait_done(); +} + +static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr) +{ + uint32_t ctrl_reg = satasii_wait_done(); + + /* Mask out unused/reserved bits, set reads and start transaction. */ + ctrl_reg &= 0xfcf80000; + ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); + + pci_mmio_writel(ctrl_reg, sii_bar); + + satasii_wait_done(); + + return (pci_mmio_readl(sii_bar + 4)) & 0xff; +} + +static const struct par_master par_master_satasii = { + .chip_readb = satasii_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = satasii_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + int satasii_init(void) { struct pci_dev *dev = NULL; @@ -104,34 +133,3 @@ return 0; } - -static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) -{ - uint32_t data_reg; - uint32_t ctrl_reg = satasii_wait_done(); - - /* Mask out unused/reserved bits, set writes and start transaction. */ - ctrl_reg &= 0xfcf80000; - ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); - - data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val; - pci_mmio_writel(data_reg, (sii_bar + 4)); - pci_mmio_writel(ctrl_reg, sii_bar); - - satasii_wait_done(); -} - -static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr) -{ - uint32_t ctrl_reg = satasii_wait_done(); - - /* Mask out unused/reserved bits, set reads and start transaction. */ - ctrl_reg &= 0xfcf80000; - ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); - - pci_mmio_writel(ctrl_reg, sii_bar); - - satasii_wait_done(); - - return (pci_mmio_readl(sii_bar + 4)) & 0xff; -} -- To view, visit https://review.coreboot.org/c/flashrom/+/54873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I88e89992380195fee7c9de7ec57502ab980ec5df Gerrit-Change-Number: 54873 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in flashrom[master]: drkaiser.c: Reshuffle to remove forward declarations
by Edward O'Callaghan (Code Review) 27 May '21

27 May '21

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/54850 ) Change subject: drkaiser.c: Reshuffle to remove forward declarations ...................................................................... drkaiser.c: Reshuffle to remove forward declarations BUG=none BRANCH=none TEST=builds Change-Id: Iee550dc8055eabfe8c7c4ad32003b6eec4f1e496 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54850 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M drkaiser.c 1 file changed, 10 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Anastasia Klimchuk: Looks good to me, but someone else must approve diff --git a/drkaiser.c b/drkaiser.c index fa562b4..4858b35 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -38,9 +38,17 @@ static uint8_t *drkaiser_bar; static void drkaiser_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr); + chipaddr addr) +{ + pci_mmio_writeb(val, drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); +} + static uint8_t drkaiser_chip_readb(const struct flashctx *flash, - const chipaddr addr); + const chipaddr addr) +{ + return pci_mmio_readb(drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); +} + static const struct par_master par_master_drkaiser = { .chip_readb = drkaiser_chip_readb, .chip_readw = fallback_chip_readw, @@ -81,15 +89,3 @@ return 0; } - -static void drkaiser_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr) -{ - pci_mmio_writeb(val, drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); -} - -static uint8_t drkaiser_chip_readb(const struct flashctx *flash, - const chipaddr addr) -{ - return pci_mmio_readb(drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK)); -} -- To view, visit https://review.coreboot.org/c/flashrom/+/54850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iee550dc8055eabfe8c7c4ad32003b6eec4f1e496 Gerrit-Change-Number: 54850 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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flashrom-gerrit May 2021