May 2021 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: dummyflasher.c: Get rid of get_data_from_context()
by Edward O'Callaghan (Code Review) 27 May '21

27 May '21

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/54907 ) Change subject: dummyflasher.c: Get rid of get_data_from_context() ...................................................................... dummyflasher.c: Get rid of get_data_from_context() Relying on the global state 'dummy_buses_supported' to determine the member master struct [mst.par or mst.spi] is both buggy and ultimately unnecessary. It became apparent after commit 4eef651ff503f81b77 just how fragile this really was as the 'defaults' simultaneously selected both buses causing get_data_from_context() to fall-though however memory happened to workout by chance due to the union. With the member master structs now being struct fields the subtle bug is more apparent. BUG=none BRANCH=none TEST=`./flashrom -r /tmp/fwupdater.apnSQQ -p dummy:emulate=VARIABLE_SIZE,image=test_update.sh.tmp.emu,size=8388608` Change-Id: I07a34faf50ff0679cb3d6bc683142f82160010b1 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54907 Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Sam McNally <sammc(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M dummyflasher.c 1 file changed, 2 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved Anastasia Klimchuk: Looks good to me, but someone else must approve diff --git a/dummyflasher.c b/dummyflasher.c index 587fc61..b7cfab8 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -103,18 +103,6 @@ #endif #endif -static enum chipbustype dummy_buses_supported = BUS_NONE; - -static struct emu_data* get_data_from_context(const struct flashctx *flash) -{ - if (dummy_buses_supported & BUS_NONSPI) - return (struct emu_data *)flash->mst->par.data; - else if (dummy_buses_supported & BUS_SPI) - return (struct emu_data *)flash->mst->spi.data; - - return NULL; /* buses was set to BUS_NONE. */ -} - void *dummy_map(const char *descr, uintptr_t phys_addr, size_t len) { msg_pspew("%s: Mapping %s, 0x%zx bytes at 0x%0*" PRIxPTR "\n", @@ -688,7 +676,7 @@ /* Convert the parameters to lowercase. */ tolower_string(bustext); - dummy_buses_supported = BUS_NONE; + enum chipbustype dummy_buses_supported = BUS_NONE; if (strstr(bustext, "parallel")) { dummy_buses_supported |= BUS_PARALLEL; msg_pdbg("Enabling support for %s flash.\n", "parallel"); @@ -1041,7 +1029,7 @@ int probe_variable_size(struct flashctx *flash) { unsigned int i; - const struct emu_data *emu_data = get_data_from_context(flash); + const struct emu_data *emu_data = flash->mst->spi.data; /* Skip the probing if we don't emulate this chip. */ if (!emu_data || emu_data->emu_chip != EMULATE_VARIABLE_SIZE) -- To view, visit https://review.coreboot.org/c/flashrom/+/54907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I07a34faf50ff0679cb3d6bc683142f82160010b1 Gerrit-Change-Number: 54907 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Namyoon Woo <namyoon(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in flashrom[master]: dummyflasher.c: Inline data fetch for spi workers
by Edward O'Callaghan (Code Review) 27 May '21

27 May '21

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/54906 ) Change subject: dummyflasher.c: Inline data fetch for spi workers ...................................................................... dummyflasher.c: Inline data fetch for spi workers The spi callbacks do not need par logic to fetch the data field. Instead of going though get_data_from_context() just fetch 'data' directly out of mst.spi. This leads us towards a path of removing dummy_buses_supported from global state. BUG=none BRANCH=none TEST=`./flashrom -r /tmp/fwupdater.apnSQQ -p dummy:emulate=VARIABLE_SIZE,image=test_update.sh.tmp.emu,size=8388608` Change-Id: I63b8d8861df75f52f241f09614146990fdfe59ed Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54906 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sam McNally <sammc(a)google.com> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M dummyflasher.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved Anastasia Klimchuk: Looks good to me, but someone else must approve diff --git a/dummyflasher.c b/dummyflasher.c index 4661f3d..587fc61 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -129,7 +129,7 @@ static int dummy_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) { - struct emu_data *emu_data = get_data_from_context(flash); + struct emu_data *emu_data = flash->mst->spi.data; return spi_write_chunked(flash, buf, start, len, emu_data->spi_write_256_chunksize); } @@ -570,7 +570,7 @@ unsigned char *readarr) { unsigned int i; - struct emu_data *emu_data = get_data_from_context(flash); + struct emu_data *emu_data = flash->mst->spi.data; if (!emu_data) { msg_perr("No data in flash context!\n"); return 1; -- To view, visit https://review.coreboot.org/c/flashrom/+/54906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I63b8d8861df75f52f241f09614146990fdfe59ed Gerrit-Change-Number: 54906 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in flashrom[master]: dummyflasher.c: Replace atoi() with strtoul()
by Edward O'Callaghan (Code Review) 27 May '21

27 May '21

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/54854 ) Change subject: dummyflasher.c: Replace atoi() with strtoul() ...................................................................... dummyflasher.c: Replace atoi() with strtoul() BUG=none BRANCH=none TEST=builds Change-Id: Ib9e66016a2f4ce2d13b833c261f900cab80916b7 Spotted-by: Angel Pons <th3fanbus(a)gmail.com> Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54854 Reviewed-by: Sam McNally <sammc(a)google.com> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M dummyflasher.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved Anastasia Klimchuk: Looks good to me, but someone else must approve diff --git a/dummyflasher.c b/dummyflasher.c index 2f39c98..4661f3d 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -668,6 +668,7 @@ #if EMULATE_CHIP struct stat image_stat; #endif + char *endptr; struct emu_data *data = calloc(1, sizeof(struct emu_data)); if (!data) { @@ -710,9 +711,9 @@ tmp = extract_programmer_param("spi_write_256_chunksize"); if (tmp) { - data->spi_write_256_chunksize = atoi(tmp); + data->spi_write_256_chunksize = strtoul(tmp, &endptr, 0); free(tmp); - if (data->spi_write_256_chunksize < 1) { + if (*endptr != '\0' || data->spi_write_256_chunksize < 1) { msg_perr("invalid spi_write_256_chunksize\n"); return 1; } @@ -977,7 +978,6 @@ #ifdef EMULATE_SPI_CHIP status = extract_programmer_param("spi_status"); if (status) { - char *endptr; errno = 0; data->emu_status = strtoul(status, &endptr, 0); free(status); -- To view, visit https://review.coreboot.org/c/flashrom/+/54854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib9e66016a2f4ce2d13b833c261f900cab80916b7 Gerrit-Change-Number: 54854 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in flashrom[master]: programmer: Introduce default shutdown function
by Anastasia Klimchuk (Code Review) 27 May '21

27 May '21

Attention is currently required from: Nico Huber, Edward O'Callaghan, Angel Pons. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54890 ) Change subject: programmer: Introduce default shutdown function ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/54890/comment/6c871a4f_ec3cf9f3 PS1, Line 13: lot of par masters that : will use it in the nearest future. > Yes sure, my main goal was to get some comments, thank you for comment! […] I have an update: there are 4 more customers that would be using default_shutdown function (bitbang spi masters): CB:54994 CB:54995 CB:54996 CB:54998 So if you are saying this is a good direction, maybe we can consider going ahead with it? If this goes after bitbangs, that would be 5 places to change - still fine. And then 10 par masters would use default shutdown straight away. -- To view, visit https://review.coreboot.org/c/flashrom/+/54890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8b20717ba549e12edffbc5d1643ff064a4f0c517 Gerrit-Change-Number: 54890 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 27 May 2021 02:00:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: rayer_spi.c: Refactor singleton states into reentrant pattern
by Anastasia Klimchuk (Code Review) 27 May '21

27 May '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/54998 to look at the new patch set (#2). Change subject: rayer_spi.c: Refactor singleton states into reentrant pattern ...................................................................... rayer_spi.c: Refactor singleton states into reentrant pattern Move global singleton states into a struct and store within the bitbang_spi_master data field for the life-time of the driver. This is one of the steps on the way to move spi_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". BUG=b:185191942 TEST=builds Change-Id: Idde4557d89f80fe5d5884ce6c8cdf538ad2e5d68 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M rayer_spi.c 1 file changed, 93 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/98/54998/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/54998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idde4557d89f80fe5d5884ce6c8cdf538ad2e5d68 Gerrit-Change-Number: 54998 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: rayer_spi.c: Refactor singleton states into reentrant pattern
by Anastasia Klimchuk (Code Review) 27 May '21

27 May '21

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54998 ) Change subject: rayer_spi.c: Refactor singleton states into reentrant pattern ...................................................................... rayer_spi.c: Refactor singleton states into reentrant pattern Move global singleton states into a struct and store within the bitbang_spi_master data field for the life-time of the driver. This is one of the steps on the way to move spi_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". BUG=b:185191942 TEST=builds Change-Id: Idde4557d89f80fe5d5884ce6c8cdf538ad2e5d68 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M rayer_spi.c 1 file changed, 84 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/98/54998/1 diff --git a/rayer_spi.c b/rayer_spi.c index 8401cda..ae5042f 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -31,11 +31,6 @@ #include "programmer.h" #include "hwaccess.h" -static uint16_t lpt_iobase; - -/* Cached value of last byte sent. */ -static uint8_t lpt_outbyte; - /* We have two sets of pins, out and in. The numbers for both sets are * independent and are bitshift values, not real pin numbers. * Default settings are for the RayeR hardware. @@ -53,10 +48,18 @@ uint8_t sck_bit; uint8_t mosi_bit; uint8_t miso_bit; - void (*preinit)(const void *); + void (*preinit)(void *); int (*shutdown)(void *); }; +struct rayer_spi_data { + uint16_t lpt_iobase; + /* Cached value of last byte sent. */ + uint8_t lpt_outbyte; + + const struct rayer_pinout *pinout; +}; + static const struct rayer_pinout rayer_spipgm = { .cs_bit = 5, .sck_bit = 6, @@ -64,18 +67,26 @@ .miso_bit = 6, }; -static void dlc5_preinit(const void *data) { +static void dlc5_preinit(void *spi_data) +{ + struct rayer_spi_data *data = spi_data; + msg_pdbg("dlc5_preinit\n"); /* Assert pin 6 to receive MISO. */ - lpt_outbyte |= (1<<4); - OUTB(lpt_outbyte, lpt_iobase); + data->lpt_outbyte |= (1<<4); + OUTB(data->lpt_outbyte, data->lpt_iobase); } -static int dlc5_shutdown(void *data) { +static int dlc5_shutdown(void *spi_data) +{ + struct rayer_spi_data *data = spi_data; + msg_pdbg("dlc5_shutdown\n"); /* De-assert pin 6 to force MISO low. */ - lpt_outbyte &= ~(1<<4); - OUTB(lpt_outbyte, lpt_iobase); + data->lpt_outbyte &= ~(1<<4); + OUTB(data->lpt_outbyte, data->lpt_iobase); + + free(data); return 0; } @@ -88,16 +99,24 @@ .shutdown = dlc5_shutdown, }; -static void byteblaster_preinit(const void *data){ +static void byteblaster_preinit(void *spi_data) +{ + struct rayer_spi_data *data = spi_data; + msg_pdbg("byteblaster_preinit\n"); /* Assert #EN signal. */ - OUTB(2, lpt_iobase + 2 ); + OUTB(2, data->lpt_iobase + 2 ); } -static int byteblaster_shutdown(void *data){ +static int byteblaster_shutdown(void *spi_data) +{ + struct rayer_spi_data *data = spi_data; + msg_pdbg("byteblaster_shutdown\n"); /* De-Assert #EN signal. */ - OUTB(0, lpt_iobase + 2 ); + OUTB(0, data->lpt_iobase + 2 ); + + free(data); return 0; } @@ -110,18 +129,26 @@ .shutdown = byteblaster_shutdown, }; -static void stk200_preinit(const void *data) { +static void stk200_preinit(void *spi_data) +{ + struct rayer_spi_data *data = spi_data; + msg_pdbg("stk200_init\n"); /* Assert #EN signals, set LED signal. */ - lpt_outbyte = (1 << 6) ; - OUTB(lpt_outbyte, lpt_iobase); + data->lpt_outbyte = (1 << 6) ; + OUTB(data->lpt_outbyte, data->lpt_iobase); } -static int stk200_shutdown(void *data) { +static int stk200_shutdown(void *spi_data) +{ + struct rayer_spi_data *data = spi_data; + msg_pdbg("stk200_shutdown\n"); /* Assert #EN signals, clear LED signal. */ - lpt_outbyte = (1 << 2) | (1 << 3); - OUTB(lpt_outbyte, lpt_iobase); + data->lpt_outbyte = (1 << 2) | (1 << 3); + OUTB(data->lpt_outbyte, data->lpt_iobase); + + free(data); return 0; } @@ -158,35 +185,40 @@ {0}, }; -static const struct rayer_pinout *pinout = NULL; - static void rayer_bitbang_set_cs(int val, void *spi_data) { - lpt_outbyte &= ~(1 << pinout->cs_bit); - lpt_outbyte |= (val << pinout->cs_bit); - OUTB(lpt_outbyte, lpt_iobase); + struct rayer_spi_data *data = spi_data; + + data->lpt_outbyte &= ~(1 << data->pinout->cs_bit); + data->lpt_outbyte |= (val << data->pinout->cs_bit); + OUTB(data->lpt_outbyte, data->lpt_iobase); } static void rayer_bitbang_set_sck(int val, void *spi_data) { - lpt_outbyte &= ~(1 << pinout->sck_bit); - lpt_outbyte |= (val << pinout->sck_bit); - OUTB(lpt_outbyte, lpt_iobase); + struct rayer_spi_data *data = spi_data; + + data->lpt_outbyte &= ~(1 << data->pinout->sck_bit); + data->lpt_outbyte |= (val << data->pinout->sck_bit); + OUTB(data->lpt_outbyte, data->lpt_iobase); } static void rayer_bitbang_set_mosi(int val, void *spi_data) { - lpt_outbyte &= ~(1 << pinout->mosi_bit); - lpt_outbyte |= (val << pinout->mosi_bit); - OUTB(lpt_outbyte, lpt_iobase); + struct rayer_spi_data *data = spi_data; + + data->lpt_outbyte &= ~(1 << data->pinout->mosi_bit); + data->lpt_outbyte |= (val << data->pinout->mosi_bit); + OUTB(data->lpt_outbyte, data->lpt_iobase); } static int rayer_bitbang_get_miso(void *spi_data) { + struct rayer_spi_data *data = spi_data; uint8_t tmp; - tmp = INB(lpt_iobase + 1) ^ 0x80; // bit.7 inverted - tmp = (tmp >> pinout->miso_bit) & 0x1; + tmp = INB(data->lpt_iobase + 1) ^ 0x80; // bit.7 inverted + tmp = (tmp >> data->pinout->miso_bit) & 0x1; return tmp; } @@ -202,6 +234,9 @@ { const struct rayer_programmer *prog = rayer_spi_types; char *arg = NULL; + struct rayer_pinout *pinout = NULL; + uint16_t lpt_iobase; + uint8_t lpt_outbyte; /* Non-default port requested? */ arg = extract_programmer_param("iobase"); @@ -260,12 +295,21 @@ /* Get the initial value before writing to any line. */ lpt_outbyte = INB(lpt_iobase); - if (pinout->shutdown) - register_shutdown(pinout->shutdown, (void*)pinout); - if (pinout->preinit) - pinout->preinit(pinout); + struct rayer_spi_data *data = calloc(1, sizeof(*data)); + if (!data) { + msg_perr("Unable to allocate space for SPI master data\n"); + return 1; + } + data->pinout = pinout; + data->lpt_iobase = lpt_iobase; + data->lpt_outbyte = lpt_outbyte; - if (register_spi_bitbang_master(&bitbang_spi_master_rayer, NULL)) + if (pinout->shutdown) + register_shutdown(pinout->shutdown, data); + if (pinout->preinit) + pinout->preinit(data); + + if (register_spi_bitbang_master(&bitbang_spi_master_rayer, data)) return 1; return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/54998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idde4557d89f80fe5d5884ce6c8cdf538ad2e5d68 Gerrit-Change-Number: 54998 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ogp_spi.c: Refactor singleton states into reentrant pattern
by Anastasia Klimchuk (Code Review) 27 May '21

27 May '21

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54996 ) Change subject: ogp_spi.c: Refactor singleton states into reentrant pattern ...................................................................... ogp_spi.c: Refactor singleton states into reentrant pattern Move global singleton states into a struct and store within the bitbang_spi_master data field for the life-time of the driver. This is one of the steps on the way to move spi_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". BUG=b:185191942 TEST=builds Change-Id: I6b8f6ecd7c9949ffb4098bf56a8936393283382f Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M ogp_spi.c 1 file changed, 46 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/54996/1 diff --git a/ogp_spi.c b/ogp_spi.c index 01694ca..a5d38f7 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -36,12 +36,14 @@ #define OGA1_XP10_CPROM_SCK 0x0058 /* W */ #define OGA1_XP10_CPROM_REG_SEL 0x005C /* W */ -static uint8_t *ogp_spibar; +struct ogp_spi_data { + uint8_t *ogp_spibar; -static uint32_t ogp_reg_sel; -static uint32_t ogp_reg_siso; -static uint32_t ogp_reg__ce; -static uint32_t ogp_reg_sck; + uint32_t ogp_reg_sel; + uint32_t ogp_reg_siso; + uint32_t ogp_reg__ce; + uint32_t ogp_reg_sck; +}; const struct dev_entry ogp_spi[] = { {PCI_VENDOR_ID_OGP, 0x0000, OK, "Open Graphics Project", "Development Board OGD1"}, @@ -51,34 +53,40 @@ static void ogp_request_spibus(void *spi_data) { - pci_mmio_writel(1, ogp_spibar + ogp_reg_sel); + struct ogp_spi_data *data = spi_data; + pci_mmio_writel(1, data->ogp_spibar + data->ogp_reg_sel); } static void ogp_release_spibus(void *spi_data) { - pci_mmio_writel(0, ogp_spibar + ogp_reg_sel); + struct ogp_spi_data *data = spi_data; + pci_mmio_writel(0, data->ogp_spibar + data->ogp_reg_sel); } static void ogp_bitbang_set_cs(int val, void *spi_data) { - pci_mmio_writel(val, ogp_spibar + ogp_reg__ce); + struct ogp_spi_data *data = spi_data; + pci_mmio_writel(val, data->ogp_spibar + data->ogp_reg__ce); } static void ogp_bitbang_set_sck(int val, void *spi_data) { - pci_mmio_writel(val, ogp_spibar + ogp_reg_sck); + struct ogp_spi_data *data = spi_data; + pci_mmio_writel(val, data->ogp_spibar + data->ogp_reg_sck); } static void ogp_bitbang_set_mosi(int val, void *spi_data) { - pci_mmio_writel(val, ogp_spibar + ogp_reg_siso); + struct ogp_spi_data *data = spi_data; + pci_mmio_writel(val, data->ogp_spibar + data->ogp_reg_siso); } static int ogp_bitbang_get_miso(void *spi_data) { + struct ogp_spi_data *data = spi_data; uint32_t tmp; - tmp = pci_mmio_readl(ogp_spibar + ogp_reg_siso); + tmp = pci_mmio_readl(data->ogp_spibar + data->ogp_reg_siso); return tmp & 0x1; } @@ -92,10 +100,21 @@ .half_period = 0, }; +static int ogp_spi_shutdown(void *data) +{ + free(data); + return 0; +} + int ogp_spi_init(void) { struct pci_dev *dev = NULL; char *type; + uint8_t *ogp_spibar; + uint32_t ogp_reg_sel; + uint32_t ogp_reg_siso; + uint32_t ogp_reg__ce; + uint32_t ogp_reg_sck; type = extract_programmer_param("rom"); @@ -135,7 +154,22 @@ if (ogp_spibar == ERROR_PTR) return 1; - if (register_spi_bitbang_master(&bitbang_spi_master_ogp, NULL)) + struct ogp_spi_data *data = calloc(1, sizeof(*data)); + if(!data) { + msg_perr("Unable to allocate space for SPI master data\n"); + return 1; + } + data->ogp_spibar = ogp_spibar; + data->ogp_reg_sel = ogp_reg_sel; + data->ogp_reg_siso = ogp_reg_siso; + data->ogp_reg__ce = ogp_reg__ce; + data->ogp_reg_sck = ogp_reg_sck; + if (register_shutdown(ogp_spi_shutdown, data)) { + free(data); + return 1; + } + + if (register_spi_bitbang_master(&bitbang_spi_master_ogp, data)) return 1; return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/54996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6b8f6ecd7c9949ffb4098bf56a8936393283382f Gerrit-Change-Number: 54996 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: pony_spi.c: Refactor singleton states into reentrant pattern
by Anastasia Klimchuk (Code Review) 27 May '21

27 May '21

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54997 ) Change subject: pony_spi.c: Refactor singleton states into reentrant pattern ...................................................................... pony_spi.c: Refactor singleton states into reentrant pattern Move global singleton states into a struct and store within the bitbang_spi_master data field for the life-time of the driver. This is one of the steps on the way to move spi_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". BUG=b:185191942 TEST=builds Change-Id: Icf1125dadcdaa287ebe3c07ca95adb770bb19412 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M pony_spi.c 1 file changed, 49 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/97/54997/1 diff --git a/pony_spi.c b/pony_spi.c index 940cae1..97b87be 100644 --- a/pony_spi.c +++ b/pony_spi.c @@ -49,16 +49,20 @@ TYPE_AJAWE }; -/* Pins for master->slave direction */ -static int pony_negate_cs = 1; -static int pony_negate_sck = 0; -static int pony_negate_mosi = 0; -/* Pins for slave->master direction */ -static int pony_negate_miso = 0; +struct pony_spi_data { + /* Pins for master->slave direction */ + int pony_negate_cs; + int pony_negate_sck; + int pony_negate_mosi; + /* Pins for slave->master direction */ + int pony_negate_miso; +}; static void pony_bitbang_set_cs(int val, void *spi_data) { - if (pony_negate_cs) + struct pony_spi_data *data = spi_data; + + if (data->pony_negate_cs) val ^= 1; sp_set_pin(PIN_TXD, val); @@ -66,7 +70,9 @@ static void pony_bitbang_set_sck(int val, void *spi_data) { - if (pony_negate_sck) + struct pony_spi_data *data = spi_data; + + if (data->pony_negate_sck) val ^= 1; sp_set_pin(PIN_RTS, val); @@ -74,7 +80,9 @@ static void pony_bitbang_set_mosi(int val, void *spi_data) { - if (pony_negate_mosi) + struct pony_spi_data *data = spi_data; + + if (data->pony_negate_mosi) val ^= 1; sp_set_pin(PIN_DTR, val); @@ -82,9 +90,10 @@ static int pony_bitbang_get_miso(void *spi_data) { + struct pony_spi_data *data = spi_data; int tmp = sp_get_pin(PIN_CTS); - if (pony_negate_miso) + if (data->pony_negate_miso) tmp ^= 1; return tmp; @@ -107,6 +116,7 @@ else msg_pdbg("Pony SPI shutdown completed.\n"); + free(data); return ret; } @@ -119,6 +129,16 @@ int have_device = 0; int have_prog = 0; + struct pony_spi_data *data = calloc(1, sizeof(*data)); + if (!data) { + msg_perr("Unable to allocate space for SPI master data\n"); + return 1; + } + data->pony_negate_cs = 1; + data->pony_negate_sck = 0; + data->pony_negate_mosi = 0; + data->pony_negate_miso = 0; + /* The parameter is in format "dev=/dev/device,type=serbang" */ arg = extract_programmer_param("dev"); if (arg && strlen(arg)) { @@ -127,8 +147,9 @@ free(arg); return 1; } - if (register_shutdown(pony_spi_shutdown, NULL) != 0) { + if (register_shutdown(pony_spi_shutdown, data) != 0) { free(arg); + free(data); serialport_shutdown(NULL); return 1; } @@ -165,25 +186,25 @@ */ switch (type) { case TYPE_AJAWE: - pony_negate_cs = 1; - pony_negate_sck = 1; - pony_negate_mosi = 1; - pony_negate_miso = 1; + data->pony_negate_cs = 1; + data->pony_negate_sck = 1; + data->pony_negate_mosi = 1; + data->pony_negate_miso = 1; name = "AJAWe"; break; case TYPE_SERBANG: - pony_negate_cs = 0; - pony_negate_sck = 0; - pony_negate_mosi = 0; - pony_negate_miso = 1; + data->pony_negate_cs = 0; + data->pony_negate_sck = 0; + data->pony_negate_mosi = 0; + data->pony_negate_miso = 1; name = "serbang"; break; default: case TYPE_SI_PROG: - pony_negate_cs = 1; - pony_negate_sck = 0; - pony_negate_mosi = 0; - pony_negate_miso = 0; + data->pony_negate_cs = 1; + data->pony_negate_sck = 0; + data->pony_negate_mosi = 0; + data->pony_negate_miso = 0; name = "SI-Prog"; break; } @@ -192,9 +213,9 @@ /* * Detect if there is a compatible hardware programmer connected. */ - pony_bitbang_set_cs(1, NULL); - pony_bitbang_set_sck(1, NULL); - pony_bitbang_set_mosi(1, NULL); + pony_bitbang_set_cs(1, data); + pony_bitbang_set_sck(1, data); + pony_bitbang_set_mosi(1, data); switch (type) { case TYPE_AJAWE: @@ -224,8 +245,8 @@ return 1; } - if (register_spi_bitbang_master(&bitbang_spi_master_pony, NULL)) { + if (register_spi_bitbang_master(&bitbang_spi_master_pony, data)) return 1; - } + return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/54997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Icf1125dadcdaa287ebe3c07ca95adb770bb19412 Gerrit-Change-Number: 54997 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: nicintel_spi.c: Refactor singleton states into reentrant pattern
by Anastasia Klimchuk (Code Review) 27 May '21

27 May '21

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54995 ) Change subject: nicintel_spi.c: Refactor singleton states into reentrant pattern ...................................................................... nicintel_spi.c: Refactor singleton states into reentrant pattern Move global singleton states into a struct and store within the bitbang_spi_master data field for the life-time of the driver. This is one of the steps on the way to move spi_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". BUG=b:185191942 TEST=builds Change-Id: I385d3ced19dfe6453ccc4128a7b792c2dce3a449 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M nicintel_spi.c 1 file changed, 79 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/54995/1 diff --git a/nicintel_spi.c b/nicintel_spi.c index 9e97840..82b9c34 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -75,7 +75,9 @@ #define BIT(x) (1<<(x)) -static uint8_t *nicintel_spibar; +struct nicintel_spi_data { + uint8_t *nicintel_spibar; +}; const struct dev_entry nics_intel_spi[] = { {PCI_VENDOR_ID_INTEL, 0x105e, OK, "Intel", "82571EB Gigabit Ethernet Controller"}, @@ -109,60 +111,66 @@ static void nicintel_request_spibus(void *spi_data) { + struct nicintel_spi_data *data = spi_data; uint32_t tmp; - tmp = pci_mmio_readl(nicintel_spibar + FLA); + tmp = pci_mmio_readl(data->nicintel_spibar + FLA); tmp |= BIT(FL_REQ); - pci_mmio_writel(tmp, nicintel_spibar + FLA); + pci_mmio_writel(tmp, data->nicintel_spibar + FLA); /* Wait until we are allowed to use the SPI bus. */ - while (!(pci_mmio_readl(nicintel_spibar + FLA) & BIT(FL_GNT))) ; + while (!(pci_mmio_readl(data->nicintel_spibar + FLA) & BIT(FL_GNT))) ; } static void nicintel_release_spibus(void *spi_data) { + struct nicintel_spi_data *data = spi_data; uint32_t tmp; - tmp = pci_mmio_readl(nicintel_spibar + FLA); + tmp = pci_mmio_readl(data->nicintel_spibar + FLA); tmp &= ~BIT(FL_REQ); - pci_mmio_writel(tmp, nicintel_spibar + FLA); + pci_mmio_writel(tmp, data->nicintel_spibar + FLA); } static void nicintel_bitbang_set_cs(int val, void *spi_data) { + struct nicintel_spi_data *data = spi_data; uint32_t tmp; - tmp = pci_mmio_readl(nicintel_spibar + FLA); + tmp = pci_mmio_readl(data->nicintel_spibar + FLA); tmp &= ~BIT(FL_CS); tmp |= (val << FL_CS); - pci_mmio_writel(tmp, nicintel_spibar + FLA); + pci_mmio_writel(tmp, data->nicintel_spibar + FLA); } static void nicintel_bitbang_set_sck(int val, void *spi_data) { + struct nicintel_spi_data *data = spi_data; uint32_t tmp; - tmp = pci_mmio_readl(nicintel_spibar + FLA); + tmp = pci_mmio_readl(data->nicintel_spibar + FLA); tmp &= ~BIT(FL_SCK); tmp |= (val << FL_SCK); - pci_mmio_writel(tmp, nicintel_spibar + FLA); + pci_mmio_writel(tmp, data->nicintel_spibar + FLA); } static void nicintel_bitbang_set_mosi(int val, void *spi_data) { + struct nicintel_spi_data *data = spi_data; uint32_t tmp; - tmp = pci_mmio_readl(nicintel_spibar + FLA); + tmp = pci_mmio_readl(data->nicintel_spibar + FLA); tmp &= ~BIT(FL_SI); tmp |= (val << FL_SI); - pci_mmio_writel(tmp, nicintel_spibar + FLA); + pci_mmio_writel(tmp, data->nicintel_spibar + FLA); } static int nicintel_bitbang_get_miso(void *spi_data) { + struct nicintel_spi_data *data = spi_data; uint32_t tmp; - tmp = pci_mmio_readl(nicintel_spibar + FLA); + tmp = pci_mmio_readl(data->nicintel_spibar + FLA); tmp = (tmp >> FL_SO) & 0x1; return tmp; } @@ -177,20 +185,22 @@ .half_period = 1, }; -static int nicintel_spi_shutdown(void *data) +static int nicintel_spi_shutdown(void *spi_data) { + struct nicintel_spi_data *data = spi_data; uint32_t tmp; /* Disable writes manually. See the comment about EECD in nicintel_spi_init() for details. */ - tmp = pci_mmio_readl(nicintel_spibar + EECD); + tmp = pci_mmio_readl(data->nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_ENABLED; tmp |= FLASH_WRITES_DISABLED; - pci_mmio_writel(tmp, nicintel_spibar + EECD); + pci_mmio_writel(tmp, data->nicintel_spibar + EECD); + free(data); return 0; } -static int nicintel_spi_82599_enable_flash(void) +static int nicintel_spi_82599_enable_flash(struct nicintel_spi_data *data) { uint32_t tmp; @@ -199,45 +209,53 @@ * but other bits with side effects as well. Those other bits must be * left untouched. */ - tmp = pci_mmio_readl(nicintel_spibar + EECD); + tmp = pci_mmio_readl(data->nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_DISABLED; tmp |= FLASH_WRITES_ENABLED; - pci_mmio_writel(tmp, nicintel_spibar + EECD); + pci_mmio_writel(tmp, data->nicintel_spibar + EECD); /* test if FWE is really set to allow writes */ - tmp = pci_mmio_readl(nicintel_spibar + EECD); + tmp = pci_mmio_readl(data->nicintel_spibar + EECD); if ( (tmp & FLASH_WRITES_DISABLED) || !(tmp & FLASH_WRITES_ENABLED) ) { msg_perr("Enabling flash write access failed.\n"); return 1; } - if (register_shutdown(nicintel_spi_shutdown, NULL)) + if (register_shutdown(nicintel_spi_shutdown, data)) return 1; return 0; } -static int nicintel_spi_i210_enable_flash(void) +static int nicintel_spi_i210_shutdown(void *data) +{ + free(data); + return 0; +} + +static int nicintel_spi_i210_enable_flash(struct nicintel_spi_data *data) { uint32_t tmp; - tmp = pci_mmio_readl(nicintel_spibar + FLA); + tmp = pci_mmio_readl(data->nicintel_spibar + FLA); if (tmp & BIT(FL_LOCKED)) { msg_perr("Flash is in Secure Mode. Abort.\n"); return 1; } - if (!(tmp & BIT(FL_ABORT))) - return 0; - - tmp |= BIT(FL_CLR_ERR); - pci_mmio_writel(tmp, nicintel_spibar + FLA); - tmp = pci_mmio_readl(nicintel_spibar + FLA); - if (!(tmp & BIT(FL_ABORT))) { - msg_perr("Unable to clear Flash Access Error. Abort\n"); - return 1; + if (tmp & BIT(FL_ABORT)) { + tmp |= BIT(FL_CLR_ERR); + pci_mmio_writel(tmp, data->nicintel_spibar + FLA); + tmp = pci_mmio_readl(data->nicintel_spibar + FLA); + if (!(tmp & BIT(FL_ABORT))) { + msg_perr("Unable to clear Flash Access Error. Abort\n"); + return 1; + } } + if (register_shutdown(nicintel_spi_i210_shutdown, data)) + return 1; + return 0; } @@ -256,25 +274,37 @@ if (!io_base_addr) return 1; - if ((dev->device_id & 0xfff0) == 0x1530) { - nicintel_spibar = rphysmap("Intel I210 Gigabit w/ SPI flash", io_base_addr + 0x12000, - MEMMAP_SIZE); - if (!nicintel_spibar || nicintel_spi_i210_enable_flash()) - return 1; - } else if (dev->device_id < 0x10d8) { - nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, - MEMMAP_SIZE); - if (!nicintel_spibar || nicintel_spi_82599_enable_flash()) - return 1; - } else { - nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000, - MEMMAP_SIZE); - if (!nicintel_spibar || nicintel_spi_82599_enable_flash()) - return 1; + struct nicintel_spi_data *data = calloc(1, sizeof(*data)); + if (!data) { + msg_perr("Unable to allocate space for SPI master data\n"); + return 1; } - if (register_spi_bitbang_master(&bitbang_spi_master_nicintel, NULL)) - return 1; + if ((dev->device_id & 0xfff0) == 0x1530) { + data->nicintel_spibar = rphysmap("Intel I210 Gigabit w/ SPI flash", io_base_addr + 0x12000, + MEMMAP_SIZE); + if (!data->nicintel_spibar || nicintel_spi_i210_enable_flash(data)) { + free(data); + return 1; + } + } else if (dev->device_id < 0x10d8) { + data->nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, + MEMMAP_SIZE); + if (!data->nicintel_spibar || nicintel_spi_82599_enable_flash(data)) { + free(data); + return 1; + } + } else { + data->nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000, + MEMMAP_SIZE); + if (!data->nicintel_spibar || nicintel_spi_82599_enable_flash(data)) { + free(data); + return 1; + } + } + + if (register_spi_bitbang_master(&bitbang_spi_master_nicintel, data)) + return 1; /* shutdown function does cleanup */ return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/54995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I385d3ced19dfe6453ccc4128a7b792c2dce3a449 Gerrit-Change-Number: 54995 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: mcp6x_spi.c: Refactor singleton states into reentrant pattern
by Anastasia Klimchuk (Code Review) 27 May '21

27 May '21

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/54994 ) Change subject: mcp6x_spi.c: Refactor singleton states into reentrant pattern ...................................................................... mcp6x_spi.c: Refactor singleton states into reentrant pattern Move global singleton states into a struct and store within the bitbang_spi_master data field for the life-time of the driver. This is one of the steps on the way to move spi_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". BUG=b:185191942 TEST=builds Change-Id: Ia02c1cb9d36fb7b15bb7e09b769d8969c08c2bd5 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M mcp6x_spi.c 1 file changed, 56 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/54994/1 diff --git a/mcp6x_spi.c b/mcp6x_spi.c index de44299..083ad56 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -36,55 +36,68 @@ #define MCP6X_SPI_REQUEST 0 #define MCP6X_SPI_GRANT 8 -static void *mcp6x_spibar = NULL; - -/* Cached value of last GPIO state. */ -static uint8_t mcp_gpiostate; +struct mcp6x_spi_data { + void *mcp6x_spibar; + /* Cached value of last GPIO state. */ + uint8_t mcp_gpiostate; +}; static void mcp6x_request_spibus(void *spi_data) { - mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); - mcp_gpiostate |= 1 << MCP6X_SPI_REQUEST; - mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); + struct mcp6x_spi_data *data = spi_data; + + data->mcp_gpiostate = mmio_readb(data->mcp6x_spibar + 0x530); + data->mcp_gpiostate |= 1 << MCP6X_SPI_REQUEST; + mmio_writeb(data->mcp_gpiostate, data->mcp6x_spibar + 0x530); /* Wait until we are allowed to use the SPI bus. */ - while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) ; + while (!(mmio_readw(data->mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) ; /* Update the cache. */ - mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + data->mcp_gpiostate = mmio_readb(data->mcp6x_spibar + 0x530); } static void mcp6x_release_spibus(void *spi_data) { - mcp_gpiostate &= ~(1 << MCP6X_SPI_REQUEST); - mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); + struct mcp6x_spi_data *data = spi_data; + + data->mcp_gpiostate &= ~(1 << MCP6X_SPI_REQUEST); + mmio_writeb(data->mcp_gpiostate, data->mcp6x_spibar + 0x530); } static void mcp6x_bitbang_set_cs(int val, void *spi_data) { - mcp_gpiostate &= ~(1 << MCP6X_SPI_CS); - mcp_gpiostate |= (val << MCP6X_SPI_CS); - mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); + struct mcp6x_spi_data *data = spi_data; + + data->mcp_gpiostate &= ~(1 << MCP6X_SPI_CS); + data->mcp_gpiostate |= (val << MCP6X_SPI_CS); + mmio_writeb(data->mcp_gpiostate, data->mcp6x_spibar + 0x530); } static void mcp6x_bitbang_set_sck(int val, void *spi_data) { - mcp_gpiostate &= ~(1 << MCP6X_SPI_SCK); - mcp_gpiostate |= (val << MCP6X_SPI_SCK); - mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); + struct mcp6x_spi_data *data = spi_data; + + data->mcp_gpiostate &= ~(1 << MCP6X_SPI_SCK); + data->mcp_gpiostate |= (val << MCP6X_SPI_SCK); + mmio_writeb(data->mcp_gpiostate, data->mcp6x_spibar + 0x530); } static void mcp6x_bitbang_set_mosi(int val, void *spi_data) { - mcp_gpiostate &= ~(1 << MCP6X_SPI_MOSI); - mcp_gpiostate |= (val << MCP6X_SPI_MOSI); - mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); + struct mcp6x_spi_data *data = spi_data; + + data->mcp_gpiostate &= ~(1 << MCP6X_SPI_MOSI); + data->mcp_gpiostate |= (val << MCP6X_SPI_MOSI); + mmio_writeb(data->mcp_gpiostate, data->mcp6x_spibar + 0x530); } static int mcp6x_bitbang_get_miso(void *spi_data) { - mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); - return (mcp_gpiostate >> MCP6X_SPI_MISO) & 0x1; + struct mcp6x_spi_data *data = spi_data; + + data->mcp_gpiostate = mmio_readb(data->mcp6x_spibar + 0x530); + return (data->mcp_gpiostate >> MCP6X_SPI_MISO) & 0x1; } static const struct bitbang_spi_master bitbang_spi_master_mcp6x = { @@ -97,11 +110,19 @@ .half_period = 0, }; +static int mcp6x_shutdown(void *spi_data) +{ + free(spi_data); + return 0; +} + int mcp6x_spi_init(int want_spi) { uint16_t status; uint32_t mcp6x_spibaraddr; struct pci_dev *smbusdev; + void *mcp6x_spibar = NULL; + uint8_t mcp_gpiostate; /* Look for the SMBus device (SMBus PCI class) */ smbusdev = pci_dev_find_vendorclass(0x10de, 0x0c05); @@ -151,7 +172,19 @@ (status >> MCP6X_SPI_GRANT) & 0x1); mcp_gpiostate = status & 0xff; - if (register_spi_bitbang_master(&bitbang_spi_master_mcp6x, NULL)) { + struct mcp6x_spi_data *data = calloc(1, sizeof(*data)); + if (!data) { + msg_perr("Unable to allocate space for SPI master data\n"); + return 1; + } + data->mcp6x_spibar = mcp6x_spibar; + data->mcp_gpiostate = mcp_gpiostate; + + if (register_shutdown(mcp6x_shutdown, data)) { + free(data); + return 1; + } + if (register_spi_bitbang_master(&bitbang_spi_master_mcp6x, data)) { /* This should never happen. */ msg_perr("MCP6X bitbang SPI master init failed!\n"); return 1; -- To view, visit https://review.coreboot.org/c/flashrom/+/54994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia02c1cb9d36fb7b15bb7e09b769d8969c08c2bd5 Gerrit-Change-Number: 54994 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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