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Change subject: [RFC][WPTST] dummyflasher: add SR2 emulation harness
......................................................................
Patch Set 14:
(1 comment)
File dummyflasher.c:
https://review.coreboot.org/c/flashrom/+/59072/comment/02848e3b_492e57f2
PS14, Line 346: if (writecnt == 3)
Just checking, is this condition supposed to be the same as above line 338? They two used to be the same, but in the latest patchset line 338 got changed. Maybe this one needs to be upgraded as well?
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Change subject: flashchips: Add AT25DF011
......................................................................
Patch Set 5: Code-Review+1
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Change subject: flashchips: add writeprotect bit layout map to chips
......................................................................
Patch Set 21:
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/58477/comment/857dfa9e_3fbd45b4
PS20, Line 6353: .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */
: .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */
> Huh, I would've expected BP3 and BP4 to work like the other BPx bits.
Yeah, it's confusing especially since the complement bit is still called CMP. Inconsistency around naming has lead to a bunch of weirdly-wrong code in the cros writeprotect implementation.
I'm not sure how we prevent that inconsistency causing problems as more chips get added, but having a general policy of referring to bits by their actual function (e.g. treating BP3/BP4 as TB/SEC) while noting that they have a different name in the datasheet seems like a decent option.
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
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Change subject: spi25_statusreg: delete read_status_register()
......................................................................
spi25_statusreg: delete read_status_register()
BUG=b:195381327,b:153800563
TEST=builds
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Change-Id: I146b4b5439872e66c5d33e156451a729d248c7da
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M chipdrivers.h
M it87spi.c
M s25f.c
M spi25.c
M spi25_statusreg.c
5 files changed, 153 insertions(+), 55 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/29/59529/14
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Change subject: spi25_statusreg: make register read/write functions generic
......................................................................
spi25_statusreg: make register read/write functions generic
This patch adds new spi_{read,write}_register() functions that take the
source/destination register as an argument. Currently they can only
access SR1, support for other registers will be added in another patch.
Since we're refactoring things, this commit also makes
spi_read_register() return an error code, making it possible to identify
error conditions that spi_read_status_register() concealed.
BUG=b:195381327,b:153800563
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---
M chipdrivers.h
M flash.h
M spi25_statusreg.c
3 files changed, 75 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/75/58475/15
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Change subject: writeprotect, cli_classic: delete old writeprotect code
......................................................................
writeprotect, cli_classic: delete old writeprotect code
Delete writeprotect code that was previously extracted from the cros tree.
This is the first of a series of commits that adds working writeprotect
support. Following commits will incrementally implement writeprotect
operations, culminating in writeprotect support for three example chips:
GD25LQ128, GD25Q32, and GD25Q256.
BUG=b:195381327,b:153800563
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Change-Id: I67e9b31f86465e5a8f7d3def637198671ee818a8
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---
M cli_classic.c
M flash.h
M s25f.c
M writeprotect.c
D writeprotect.h
5 files changed, 7 insertions(+), 592 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/74/58474/12
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Change subject: flashrom.c: extract operation only uses layout files
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> > I am not sure what the concern is since read_flash_to_file() has a singular call site […]
I thought that tying/merging two patches together in a chain solves everyone's concerns... but tell me if not?
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I'd like you to reexamine a change. Please visit
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Change subject: hwaccess: move x86 port I/O related code into own files
......................................................................
hwaccess: move x86 port I/O related code into own files
Allow port I/O related code to be compiled independent from memory
mapping functionality. This enables for a better selection of needed
hardware access types.
Change-Id: I372b4a409f036da766c42bc406b596bc41b0f75a
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
---
M Makefile
M amd_imc.c
M atahpt.c
M atapromise.c
M atavia.c
M board_enable.c
M chipset_enable.c
M drkaiser.c
M gfxnvidia.c
M hwaccess.c
M hwaccess.h
A hwaccess_x86_io.c
M hwaccess_x86_io.h
M internal.c
M it8212.c
M it85spi.c
M it87spi.c
M meson.build
M nic3com.c
M nicintel.c
M nicintel_eeprom.c
M nicintel_spi.c
M nicnatsemi.c
M nicrealtek.c
M ogp_spi.c
M programmer.h
M rayer_spi.c
M satamv.c
M satasii.c
M tests/hwaccess_x86_io_unittest.h
M wbsio_spi.c
31 files changed, 118 insertions(+), 69 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/60110/4
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Change subject: Makefile: list dependencies for RAW_MEM_ACCESS, X86_PORT_IO, X86_MSR
......................................................................
Set Ready For Review
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