December 2021 - flashrom-gerrit

Change in flashrom[master]: physmap: renoame to hwaccess_physmap, create own header
by Thomas Heijligen (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Nico Huber. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/60113 ) Change subject: physmap: renoame to hwaccess_physmap, create own header ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/flashrom/+/60113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ieba6f4e94cfc3e668fcb8b3c978de5908aed2592 Gerrit-Change-Number: 60113 Gerrit-PatchSet: 2 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 14 Dec 2021 20:47:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: hwaccess physmap: move x86 msr related code into own files
by Thomas Heijligen (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Nico Huber. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/60111 ) Change subject: hwaccess physmap: move x86 msr related code into own files ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/flashrom/+/60111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idc9ce9df3ea1e291ad469de59467646b294119c4 Gerrit-Change-Number: 60111 Gerrit-PatchSet: 2 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 14 Dec 2021 20:47:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: hwaccess: move x86 port I/O related code into own files
by Thomas Heijligen (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Nico Huber, Angel Pons. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/60110 ) Change subject: hwaccess: move x86 port I/O related code into own files ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/flashrom/+/60110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I372b4a409f036da766c42bc406b596bc41b0f75a Gerrit-Change-Number: 60110 Gerrit-PatchSet: 3 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 14 Dec 2021 20:46:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: Makefile: list dependencies for RAW_MEM_ACCESS, X86_PORT_IO, X86_MSR
by Thomas Heijligen (Code Review) 14 Dec '21

14 Dec '21

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/60114 ) Change subject: Makefile: list dependencies for RAW_MEM_ACCESS, X86_PORT_IO, X86_MSR ...................................................................... Makefile: list dependencies for RAW_MEM_ACCESS, X86_PORT_IO, X86_MSR Change-Id: I588f698780b5acd65084346bcef781cbfd1203ea Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M Makefile 1 file changed, 40 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/14/60114/1 diff --git a/Makefile b/Makefile index fa728c6..49ff0ca 100644 --- a/Makefile +++ b/Makefile @@ -102,6 +102,40 @@ CONFIG_PONY_SPI \ CONFIG_RAYER_SPI \ +DEPENDS_ON_RAW_MEM_ACCESS := \ + CONFIG_ATAPROMISE \ + CONFIG_DRKAISER \ + CONFIG_GFXNVIDIA \ + CONFIG_INTERNAL \ + CONFIG_IT8212 \ + CONFIG_NICINTEL \ + CONFIG_NICINTEL_EEPROM \ + CONFIG_NICINTEL_SPI \ + CONFIG_OGP_SPI \ + CONFIG_SATAMV \ + CONFIG_SATASII \ + +DEPENDS_ON_X86_MSR := \ + CONFIG_INTERNAL \ + +DEPENDS_ON_X86_PORT_IO := \ + CONFIG_ATAHPT \ + CONFIG_ATAPROMISE \ + CONFIG_ATAVIA \ + CONFIG_DRKAISER \ + CONFIG_GFXNVIDIA \ + CONFIG_INTERNAL \ + CONFIG_NIC3COM \ + CONFIG_NICINTEL \ + CONFIG_NICINTEL_EEPROM \ + CONFIG_NICINTEL_SPI \ + CONFIG_NICNATSEMI \ + CONFIG_NICREALTEK \ + CONFIG_OGP_SPI \ + CONFIG_RAYER_SPI \ + CONFIG_SATAMV \ + CONFIG_SATASII \ + DEPENDS_ON_LIBPCI := \ CONFIG_ATAHPT \ CONFIG_ATAPROMISE \ @@ -218,7 +252,7 @@ # For now we disable all PCI-based programmers on Windows/MinGW (no libpci). $(call mark_unsupported,$(DEPENDS_ON_LIBPCI)) # And programmers that need raw access. -$(call mark_unsupported,CONFIG_RAYER_SPI) +$(call mark_unsupported,$(DEPENDS_ON_RAW_MEM_ACCESS)) else # No MinGW @@ -237,7 +271,7 @@ # libpayload does not provide the romsize field in struct pci_dev that the atapromise code requires. $(call mark_unsupported,CONFIG_ATAPROMISE) # Bus Pirate, Serprog and PonyProg are not supported with libpayload (missing serial support). -$(call mark_unsupported,CONFIG_BUSPIRATE_SPI CONFIG_SERPROG CONFIG_PONY_SPI) +$(call mark_unsupported,$(DEPENDS_ON_SERIAL)) # Dediprog, Developerbox, USB-Blaster, PICkit2, CH341A and FT2232 are not supported with libpayload (missing libusb support). $(call mark_unsupported,$(DEPENDS_ON_LIBUSB1) $(DEPENDS_ON_LIBFTDI) $(DEPENDS_ON_LIBJAYLINK)) endif @@ -256,7 +290,7 @@ ifeq ($(TARGET_OS), Android) # Android on x86 (currently) does not provide raw PCI port I/O operations. -$(call mark_unsupported,CONFIG_RAYER_SPI) +$(call mark_unsupported,$(DEPENDS_ON_X86_PORT_IO)) endif # Disable the internal programmer on unsupported architectures (everything but x86 and mipsel) @@ -274,18 +308,15 @@ # PCI port I/O support is unimplemented on PPC/MIPS/SPARC and unavailable on ARM. # Right now this means the drivers below only work on x86. ifneq ($(ARCH), x86) -$(call mark_unsupported,CONFIG_NIC3COM CONFIG_NICREALTEK CONFIG_NICNATSEMI) -$(call mark_unsupported,CONFIG_RAYER_SPI CONFIG_ATAHPT CONFIG_ATAPROMISE) -$(call mark_unsupported,CONFIG_SATAMV) +$(call mark_unsupported,$(DEPENDS_ON_X86_MSR)) +$(call mark_unsupported,$(DEPENDS_ON_X86_PORT_IO)) endif # Additionally disable all drivers needing raw access (memory, PCI, port I/O) # on architectures with unknown raw access properties. # Right now those architectures are alpha hppa m68k sh s390 ifneq ($(ARCH), $(filter $(ARCH), x86 mips ppc arm sparc arc)) -$(call mark_unsupported,CONFIG_GFXNVIDIA CONFIG_SATASII CONFIG_ATAVIA) -$(call mark_unsupported,CONFIG_DRKAISER CONFIG_NICINTEL CONFIG_NICINTEL_SPI) -$(call mark_unsupported,CONFIG_NICINTEL_EEPROM CONFIG_OGP_SPI CONFIG_IT8212) +$(call mark_unsupported,$(DEPENDS_ON_RAW_MEM_ACCESS)) endif ifeq ($(TARGET_OS), $(filter $(TARGET_OS), Linux Darwin NetBSD OpenBSD)) -- To view, visit https://review.coreboot.org/c/flashrom/+/60114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I588f698780b5acd65084346bcef781cbfd1203ea Gerrit-Change-Number: 60114 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in flashrom[master]: physmap: move to hwaccess_physmap, create own header
by Thomas Heijligen (Code Review) 14 Dec '21

14 Dec '21

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/60113 ) Change subject: physmap: move to hwaccess_physmap, create own header ...................................................................... physmap: move to hwaccess_physmap, create own header Change-Id: Ieba6f4e94cfc3e668fcb8b3c978de5908aed2592 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M Makefile M atapromise.c M cbtable.c M chipset_enable.c M dmi.c M drkaiser.c M flashrom.c M gfxnvidia.c R hwaccess_physmap.c A hwaccess_physmap.h M ichspi.c M internal.c M it8212.c M it85spi.c M mcp6x_spi.c M meson.build M nicintel.c M nicintel_eeprom.c M nicintel_spi.c M ogp_spi.c M programmer.h M satamv.c M satasii.c M sb600spi.c 24 files changed, 41 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/13/60113/1 diff --git a/Makefile b/Makefile index 72146ce..fa728c6 100644 --- a/Makefile +++ b/Makefile @@ -783,7 +783,7 @@ ifneq ($(NEED_RAW_ACCESS), ) # Raw memory, MSR or PCI port I/O access. FEATURE_CFLAGS += -D'NEED_RAW_ACCESS=1' -D'__FLASHROM_HAVE_OUTB__=1' -PROGRAMMER_OBJS += physmap.o hwaccess.o hwaccess_x86_io.o hwaccess_x86_msr.o +PROGRAMMER_OBJS += hwaccess.o hwaccess_physmap.o hwaccess_x86_io.o hwaccess_x86_msr.o ifeq ($(TARGET_OS), NetBSD) ifeq ($(ARCH), x86) diff --git a/atapromise.c b/atapromise.c index 56abc26..fb3adcb 100644 --- a/atapromise.c +++ b/atapromise.c @@ -20,6 +20,7 @@ #include "programmer.h" #include "hwaccess.h" #include "hwaccess_x86_io.h" +#include "hwaccess_physmap.h" #include "platform/pci.h" #define MAX_ROM_DECODE (32 * 1024) diff --git a/cbtable.c b/cbtable.c index d50a0cf..2b339d5 100644 --- a/cbtable.c +++ b/cbtable.c @@ -26,6 +26,7 @@ #include "flash.h" #include "programmer.h" #include "coreboot_tables.h" +#include "hwaccess_physmap.h" static char *cb_vendor = NULL, *cb_model = NULL; diff --git a/chipset_enable.c b/chipset_enable.c index 22af681..e216722 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -36,6 +36,7 @@ #include "hwaccess.h" #include "hwaccess_x86_io.h" #include "hwaccess_x86_msr.h" +#include "hwaccess_physmap.h" #include "platform/pci.h" #define NOT_DONE_YET 1 diff --git a/dmi.c b/dmi.c index d2e149d..df918f9 100644 --- a/dmi.c +++ b/dmi.c @@ -32,6 +32,7 @@ #include "flash.h" #include "hwaccess.h" +#include "hwaccess_physmap.h" #include "programmer.h" /* Enable SMBIOS decoding. Currently legacy DMI decoding is enough. */ diff --git a/drkaiser.c b/drkaiser.c index 565a45e..0930c1f 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -19,6 +19,7 @@ #include "programmer.h" #include "hwaccess.h" #include "hwaccess_x86_io.h" +#include "hwaccess_physmap.h" #include "platform/pci.h" #define PCI_VENDOR_ID_DRKAISER 0x1803 diff --git a/flashrom.c b/flashrom.c index 48d953b..85cdf87 100644 --- a/flashrom.c +++ b/flashrom.c @@ -38,6 +38,9 @@ #include "flashchips.h" #include "programmer.h" #include "hwaccess.h" +#if CONFIG_INTERNAL == 1 +#include "hwaccess_physmap.h" +#endif #include "chipdrivers.h" const char flashrom_version[] = FLASHROM_VERSION; diff --git a/gfxnvidia.c b/gfxnvidia.c index 0d3ef39..30c94b9 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -20,6 +20,7 @@ #include "programmer.h" #include "hwaccess.h" #include "hwaccess_x86_io.h" +#include "hwaccess_physmap.h" #include "platform/pci.h" #define PCI_VENDOR_ID_NVIDIA 0x10de diff --git a/physmap.c b/hwaccess_physmap.c similarity index 99% rename from physmap.c rename to hwaccess_physmap.c index 6f2896f..dcc6ed7 100644 --- a/physmap.c +++ b/hwaccess_physmap.c @@ -23,8 +23,7 @@ #include <string.h> #include <errno.h> #include "flash.h" -#include "programmer.h" -#include "hwaccess.h" +#include "hwaccess_physmap.h" #if !defined(__DJGPP__) && !defined(__LIBPAYLOAD__) /* No file access needed/possible to get mmap access permissions or access MSR. */ diff --git a/hwaccess_physmap.h b/hwaccess_physmap.h new file mode 100644 index 0000000..eccf32d --- /dev/null +++ b/hwaccess_physmap.h @@ -0,0 +1,17 @@ +/* licence + */ + +#ifndef __HWACCESS_PHYSMAP_H__ +#define __HWACCESS_PHYSMAP_H__ + +#include <stddef.h> +#include <stdint.h> + +void *physmap(const char *descr, uintptr_t phys_addr, size_t len); +void *rphysmap(const char *descr, uintptr_t phys_addr, size_t len); +void *physmap_ro(const char *descr, uintptr_t phys_addr, size_t len); +void *physmap_ro_unaligned(const char *descr, uintptr_t phys_addr, size_t len); +void physunmap(void *virt_addr, size_t len); +void physunmap_unaligned(void *virt_addr, size_t len); + +#endif /* __HWACCESS_PHYSMAP_H__ */ \ No newline at end of file diff --git a/ichspi.c b/ichspi.c index 290deaa..0bb6360 100644 --- a/ichspi.c +++ b/ichspi.c @@ -24,6 +24,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_physmap.h" #include "spi.h" #include "ich_descriptors.h" diff --git a/internal.c b/internal.c index 7de1d6a..f2f1fb1 100644 --- a/internal.c +++ b/internal.c @@ -21,6 +21,7 @@ #include "programmer.h" #include "hwaccess.h" #include "hwaccess_x86_io.h" +#include "hwaccess_physmap.h" #include "platform/pci.h" int is_laptop = 0; diff --git a/it8212.c b/it8212.c index 80da2b1..6488b15 100644 --- a/it8212.c +++ b/it8212.c @@ -19,6 +19,7 @@ #include "programmer.h" #include "hwaccess.h" #include "hwaccess_x86_io.h" +#include "hwaccess_physmap.h" #include "platform/pci.h" static uint8_t *it8212_bar = NULL; diff --git a/it85spi.c b/it85spi.c index b1074d1..17d3b57 100644 --- a/it85spi.c +++ b/it85spi.c @@ -28,6 +28,7 @@ #include "programmer.h" #include "hwaccess.h" #include "hwaccess_x86_io.h" +#include "hwaccess_physmap.h" #define MAX_TIMEOUT 100000 #define MAX_TRY 5 diff --git a/mcp6x_spi.c b/mcp6x_spi.c index 2429346..2097cf4 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -24,6 +24,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_physmap.h" #include "platform/pci.h" /* Bit positions for each pin. */ diff --git a/meson.build b/meson.build index 2e7296b..b2e2d72 100644 --- a/meson.build +++ b/meson.build @@ -349,7 +349,7 @@ srcs += 'hwaccess.c' srcs += 'hwaccess_x86_io.c' srcs += 'hwaccess_x86_msr.c' - srcs += 'physmap.c' + srcs += 'hwaccess_physmap.c' cargs += '-DNEED_RAW_ACCESS=1' cargs += '-D__FLASHROM_HAVE_OUTB__=1' endif diff --git a/nicintel.c b/nicintel.c index 7f4eb24..21dfad2 100644 --- a/nicintel.c +++ b/nicintel.c @@ -20,6 +20,7 @@ #include "programmer.h" #include "hwaccess.h" #include "hwaccess_x86_io.h" +#include "hwaccess_physmap.h" #include "platform/pci.h" static uint8_t *nicintel_bar; diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index fc2ef40..7b92958 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -36,6 +36,7 @@ #include "programmer.h" #include "hwaccess.h" #include "hwaccess_x86_io.h" +#include "hwaccess_physmap.h" #include "platform/pci.h" #define PCI_VENDOR_ID_INTEL 0x8086 diff --git a/nicintel_spi.c b/nicintel_spi.c index 25a6651..852c042 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -36,6 +36,7 @@ #include "programmer.h" #include "hwaccess.h" #include "hwaccess_x86_io.h" +#include "hwaccess_physmap.h" #include "platform/pci.h" #define PCI_VENDOR_ID_INTEL 0x8086 diff --git a/ogp_spi.c b/ogp_spi.c index 4a4934e..d4218d1 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -20,6 +20,7 @@ #include "programmer.h" #include "hwaccess.h" #include "hwaccess_x86_io.h" +#include "hwaccess_physmap.h" #include "platform/pci.h" #define PCI_VENDOR_ID_OGP 0x1227 diff --git a/programmer.h b/programmer.h index c4af35a..4dd4cad 100644 --- a/programmer.h +++ b/programmer.h @@ -231,14 +231,6 @@ int processor_flash_enable(void); #endif -/* physmap.c */ -void *physmap(const char *descr, uintptr_t phys_addr, size_t len); -void *rphysmap(const char *descr, uintptr_t phys_addr, size_t len); -void *physmap_ro(const char *descr, uintptr_t phys_addr, size_t len); -void *physmap_ro_unaligned(const char *descr, uintptr_t phys_addr, size_t len); -void physunmap(void *virt_addr, size_t len); -void physunmap_unaligned(void *virt_addr, size_t len); - #if CONFIG_INTERNAL == 1 /* cbtable.c */ int cb_parse_table(const char **vendor, const char **model); diff --git a/satamv.c b/satamv.c index 8543f53..e7c4305 100644 --- a/satamv.c +++ b/satamv.c @@ -21,6 +21,7 @@ #include "programmer.h" #include "hwaccess.h" #include "hwaccess_x86_io.h" +#include "hwaccess_physmap.h" #include "platform/pci.h" static uint8_t *mv_bar; diff --git a/satasii.c b/satasii.c index 2f220d1..f9cb5da 100644 --- a/satasii.c +++ b/satasii.c @@ -19,6 +19,7 @@ #include "programmer.h" #include "hwaccess.h" #include "hwaccess_x86_io.h" +#include "hwaccess_physmap.h" #include "platform/pci.h" #define PCI_VENDOR_ID_SII 0x1095 diff --git a/sb600spi.c b/sb600spi.c index 92fcc81..32a7420 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -23,6 +23,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_physmap.h" #include "spi.h" #include "platform/pci.h" -- To view, visit https://review.coreboot.org/c/flashrom/+/60113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ieba6f4e94cfc3e668fcb8b3c978de5908aed2592 Gerrit-Change-Number: 60113 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in flashrom[master]: hwaccess physmap: split out x86 msr code into own files
by Thomas Heijligen (Code Review) 14 Dec '21

14 Dec '21

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/60111 ) Change subject: hwaccess physmap: split out x86 msr code into own files ...................................................................... hwaccess physmap: split out x86 msr code into own files Change-Id: Idc9ce9df3ea1e291ad469de59467646b294119c4 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M Makefile M board_enable.c M chipset_enable.c M hwaccess.h A hwaccess_x86_msr.c A hwaccess_x86_msr.h M meson.build M physmap.c M programmer.h 9 files changed, 405 insertions(+), 359 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/11/60111/1 diff --git a/Makefile b/Makefile index 7207abb..72146ce 100644 --- a/Makefile +++ b/Makefile @@ -783,7 +783,7 @@ ifneq ($(NEED_RAW_ACCESS), ) # Raw memory, MSR or PCI port I/O access. FEATURE_CFLAGS += -D'NEED_RAW_ACCESS=1' -D'__FLASHROM_HAVE_OUTB__=1' -PROGRAMMER_OBJS += physmap.o hwaccess.o hwaccess_x86_io.o +PROGRAMMER_OBJS += physmap.o hwaccess.o hwaccess_x86_io.o hwaccess_x86_msr.o ifeq ($(TARGET_OS), NetBSD) ifeq ($(ARCH), x86) diff --git a/board_enable.c b/board_enable.c index 4ca7101..445e354 100644 --- a/board_enable.c +++ b/board_enable.c @@ -27,6 +27,7 @@ #include "programmer.h" #include "hwaccess.h" #include "hwaccess_x86_io.h" +#include "hwaccess_x86_msr.h" #include "platform/pci.h" #if defined(__i386__) || defined(__x86_64__) diff --git a/chipset_enable.c b/chipset_enable.c index 517918e..22af681 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -35,6 +35,7 @@ #include "programmer.h" #include "hwaccess.h" #include "hwaccess_x86_io.h" +#include "hwaccess_x86_msr.h" #include "platform/pci.h" #define NOT_DONE_YET 1 diff --git a/hwaccess.h b/hwaccess.h index 5b7b079..d80e0e3 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -122,35 +122,4 @@ #define le_to_cpu32 cpu_to_le32 #define le_to_cpu64 cpu_to_le64 -#if NEED_RAW_ACCESS == 1 && (defined (__i386__) || defined (__x86_64__) || defined(__amd64__)) - -#if !(defined(__MACH__) && defined(__APPLE__)) && !defined(__FreeBSD__) && !defined(__FreeBSD_kernel__) && !defined(__DragonFly__) && !defined(__LIBPAYLOAD__) -typedef struct { uint32_t hi, lo; } msr_t; -msr_t rdmsr(int addr); -int wrmsr(int addr, msr_t msr); -#endif -#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) -/* FreeBSD already has conflicting definitions for wrmsr/rdmsr. */ -#undef rdmsr -#undef wrmsr -#define rdmsr freebsd_rdmsr -#define wrmsr freebsd_wrmsr -typedef struct { uint32_t hi, lo; } msr_t; -msr_t freebsd_rdmsr(int addr); -int freebsd_wrmsr(int addr, msr_t msr); -#endif -#if defined(__LIBPAYLOAD__) -#include <arch/io.h> -#include <arch/msr.h> -typedef struct { uint32_t hi, lo; } msr_t; -msr_t libpayload_rdmsr(int addr); -int libpayload_wrmsr(int addr, msr_t msr); -#undef rdmsr -#define rdmsr libpayload_rdmsr -#define wrmsr libpayload_wrmsr -#endif - - -#endif - #endif /* !__HWACCESS_H__ */ diff --git a/hwaccess_x86_msr.c b/hwaccess_x86_msr.c new file mode 100644 index 0000000..fa7df72 --- /dev/null +++ b/hwaccess_x86_msr.c @@ -0,0 +1,348 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Peter Stuge <peter(a)stuge.se> + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2010 Carl-Daniel Hailfinger + * Copyright (C) 2010 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* MSR abstraction implementations for Linux, OpenBSD, FreeBSD/Dragonfly, OSX, libpayload + * and a non-working default implementation on the bottom. See also hwaccess.h for some (re)declarations. + */ + +#include "hwaccess_x86_msr.h" +#include "flash.h" + +#ifdef __linux__ +/* + * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, + * which are ring0 privileged instructions so only the kernel can do the + * read/write. This function, therefore, requires that the msr kernel module + * be loaded to access these instructions from user space using device + * /dev/cpu/0/msr. + */ + +#include <stdint.h> +#include <stdlib.h> +#include <errno.h> +#include <fcntl.h> +#include <string.h> +#include <unistd.h> + +static int fd_msr = -1; + +msr_t rdmsr(int addr) +{ + uint32_t buf[2]; + msr_t msr = { 0xffffffff, 0xffffffff }; + + if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { + msg_perr("Could not lseek() MSR: %s\n", strerror(errno)); + close(fd_msr); + exit(1); + } + + if (read(fd_msr, buf, 8) == 8) { + msr.lo = buf[0]; + msr.hi = buf[1]; + return msr; + } + + if (errno != EIO) { + // A severe error. + msg_perr("Could not read() MSR: %s\n", strerror(errno)); + close(fd_msr); + exit(1); + } + + return msr; +} + +int wrmsr(int addr, msr_t msr) +{ + uint32_t buf[2]; + buf[0] = msr.lo; + buf[1] = msr.hi; + + if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { + msg_perr("Could not lseek() MSR: %s\n", strerror(errno)); + close(fd_msr); + exit(1); + } + + if (write(fd_msr, buf, 8) != 8 && errno != EIO) { + msg_perr("Could not write() MSR: %s\n", strerror(errno)); + close(fd_msr); + exit(1); + } + + /* Some MSRs must not be written. */ + if (errno == EIO) + return -1; + + return 0; +} + +int setup_cpu_msr(int cpu) +{ + char msrfilename[64] = { 0 }; + snprintf(msrfilename, sizeof(msrfilename), "/dev/cpu/%d/msr", cpu); + + if (fd_msr != -1) { + msg_pinfo("MSR was already initialized\n"); + return -1; + } + + fd_msr = open(msrfilename, O_RDWR); + + if (fd_msr < 0) { + msg_perr("Error while opening %s: %s\n", msrfilename, strerror(errno)); + msg_pinfo("Did you run 'modprobe msr'?\n"); + return -1; + } + + return 0; +} + +void cleanup_cpu_msr(void) +{ + if (fd_msr == -1) { + msg_pinfo("No MSR initialized.\n"); + return; + } + + close(fd_msr); + + /* Clear MSR file descriptor. */ + fd_msr = -1; +} +#elif defined(__OpenBSD__) && defined (__i386__) /* This does only work for certain AMD Geode LX systems see amdmsr(4). */ +#include <stdint.h> +#include <stdio.h> +#include <sys/ioctl.h> +#include <machine/amdmsr.h> + +static int fd_msr = -1; + +msr_t rdmsr(int addr) +{ + struct amdmsr_req args; + + msr_t msr = { 0xffffffff, 0xffffffff }; + + args.addr = (uint32_t)addr; + + if (ioctl(fd_msr, RDMSR, &args) < 0) { + msg_perr("Error while executing RDMSR ioctl: %s\n", strerror(errno)); + close(fd_msr); + exit(1); + } + + msr.lo = args.val & 0xffffffff; + msr.hi = args.val >> 32; + + return msr; +} + +int wrmsr(int addr, msr_t msr) +{ + struct amdmsr_req args; + + args.addr = addr; + args.val = (((uint64_t)msr.hi) << 32) | msr.lo; + + if (ioctl(fd_msr, WRMSR, &args) < 0) { + msg_perr("Error while executing WRMSR ioctl: %s\n", strerror(errno)); + close(fd_msr); + exit(1); + } + + return 0; +} + +int setup_cpu_msr(int cpu) +{ + char msrfilename[64] = { 0 }; + snprintf(msrfilename, sizeof(msrfilename), "/dev/amdmsr"); + + if (fd_msr != -1) { + msg_pinfo("MSR was already initialized\n"); + return -1; + } + + fd_msr = open(msrfilename, O_RDWR); + + if (fd_msr < 0) { + msg_perr("Error while opening %s: %s\n", msrfilename, strerror(errno)); + return -1; + } + + return 0; +} + +void cleanup_cpu_msr(void) +{ + if (fd_msr == -1) { + msg_pinfo("No MSR initialized.\n"); + return; + } + + close(fd_msr); + + /* Clear MSR file descriptor. */ + fd_msr = -1; +} + +#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) +#include <sys/ioctl.h> + +typedef struct { + int msr; + uint64_t data; +} cpu_msr_args_t; +#define CPU_RDMSR _IOWR('c', 1, cpu_msr_args_t) +#define CPU_WRMSR _IOWR('c', 2, cpu_msr_args_t) + +static int fd_msr = -1; + +msr_t rdmsr(int addr) +{ + cpu_msr_args_t args; + + msr_t msr = { 0xffffffff, 0xffffffff }; + + args.msr = addr; + + if (ioctl(fd_msr, CPU_RDMSR, &args) < 0) { + msg_perr("Error while executing CPU_RDMSR ioctl: %s\n", strerror(errno)); + close(fd_msr); + exit(1); + } + + msr.lo = args.data & 0xffffffff; + msr.hi = args.data >> 32; + + return msr; +} + +int wrmsr(int addr, msr_t msr) +{ + cpu_msr_args_t args; + + args.msr = addr; + args.data = (((uint64_t)msr.hi) << 32) | msr.lo; + + if (ioctl(fd_msr, CPU_WRMSR, &args) < 0) { + msg_perr("Error while executing CPU_WRMSR ioctl: %s\n", strerror(errno)); + close(fd_msr); + exit(1); + } + + return 0; +} + +int setup_cpu_msr(int cpu) +{ + char msrfilename[64] = { 0 }; + snprintf(msrfilename, sizeof(msrfilename), "/dev/cpu%d", cpu); + + if (fd_msr != -1) { + msg_pinfo("MSR was already initialized\n"); + return -1; + } + + fd_msr = open(msrfilename, O_RDWR); + + if (fd_msr < 0) { + msg_perr("Error while opening %s: %s\n", msrfilename, strerror(errno)); + msg_pinfo("Did you install ports/sysutils/devcpu?\n"); + return -1; + } + + return 0; +} + +void cleanup_cpu_msr(void) +{ + if (fd_msr == -1) { + msg_pinfo("No MSR initialized.\n"); + return; + } + + close(fd_msr); + + /* Clear MSR file descriptor. */ + fd_msr = -1; +} + +#elif defined(__MACH__) && defined(__APPLE__) +/* rdmsr() and wrmsr() are provided by DirectHW which needs neither setup nor cleanup. */ +int setup_cpu_msr(int cpu) +{ + // Always succeed for now + return 0; +} + +void cleanup_cpu_msr(void) +{ + // Nothing, yet. +} +#elif defined(__LIBPAYLOAD__) +msr_t libpayload_rdmsr(int addr) +{ + msr_t msr; + unsigned long long val = _rdmsr(addr); + msr.lo = val & 0xffffffff; + msr.hi = val >> 32; + return msr; +} + +int libpayload_wrmsr(int addr, msr_t msr) +{ + _wrmsr(addr, msr.lo | ((unsigned long long)msr.hi << 32)); + return 0; +} + +int setup_cpu_msr(int cpu) +{ + return 0; +} + +void cleanup_cpu_msr(void) +{ +} +#else +/* default MSR implementation */ +msr_t rdmsr(int addr) +{ + msr_t ret = { 0xffffffff, 0xffffffff }; + + return ret; +} + +int wrmsr(int addr, msr_t msr) +{ + return -1; +} + +int setup_cpu_msr(int cpu) +{ + msg_pinfo("No MSR support for your OS yet.\n"); + return -1; +} + +void cleanup_cpu_msr(void) +{ + // Nothing, yet. +} +#endif // OS switches for MSR code diff --git a/hwaccess_x86_msr.h b/hwaccess_x86_msr.h new file mode 100644 index 0000000..4229b3b --- /dev/null +++ b/hwaccess_x86_msr.h @@ -0,0 +1,52 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __HWACCESS_X86_MSR_H__ +#define __HWACCESS_X86_MSR_H__ 1 + +#include <stdint.h> + +#if !(defined(__MACH__) && defined(__APPLE__)) && !defined(__FreeBSD__) && !defined(__FreeBSD_kernel__) && !defined(__DragonFly__) && !defined(__LIBPAYLOAD__) +typedef struct { uint32_t hi, lo; } msr_t; +msr_t rdmsr(int addr); +int wrmsr(int addr, msr_t msr); +#endif + +#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) +/* FreeBSD already has conflicting definitions for wrmsr/rdmsr. */ +#undef rdmsr +#undef wrmsr +#define rdmsr freebsd_rdmsr +#define wrmsr freebsd_wrmsr +typedef struct { uint32_t hi, lo; } msr_t; +msr_t freebsd_rdmsr(int addr); +int freebsd_wrmsr(int addr, msr_t msr); +#endif + +#if defined(__LIBPAYLOAD__) +#include <arch/io.h> +#include <arch/msr.h> +typedef struct { uint32_t hi, lo; } msr_t; +msr_t libpayload_rdmsr(int addr); +int libpayload_wrmsr(int addr, msr_t msr); +#undef rdmsr +#define rdmsr libpayload_rdmsr +#define wrmsr libpayload_wrmsr +#endif + +int setup_cpu_msr(int cpu); +void cleanup_cpu_msr(void); + +#endif /* __HWACCESS_X86_MSR_H__ */ \ No newline at end of file diff --git a/meson.build b/meson.build index 5cbcac2..2e7296b 100644 --- a/meson.build +++ b/meson.build @@ -348,6 +348,7 @@ if need_raw_access srcs += 'hwaccess.c' srcs += 'hwaccess_x86_io.c' + srcs += 'hwaccess_x86_msr.c' srcs += 'physmap.c' cargs += '-DNEED_RAW_ACCESS=1' cargs += '-D__FLASHROM_HAVE_OUTB__=1' diff --git a/physmap.c b/physmap.c index 796860c..6f2896f 100644 --- a/physmap.c +++ b/physmap.c @@ -362,327 +362,3 @@ { return physmap_common(descr, phys_addr, len, PHYSM_RO, PHYSM_NOCLEANUP, PHYSM_EXACT); } - -#if CONFIG_INTERNAL == 1 -/* MSR abstraction implementations for Linux, OpenBSD, FreeBSD/Dragonfly, OSX, libpayload - * and a non-working default implementation on the bottom. See also hwaccess.h for some (re)declarations. */ -#if defined(__i386__) || defined(__x86_64__) - -#ifdef __linux__ -/* - * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, - * which are ring0 privileged instructions so only the kernel can do the - * read/write. This function, therefore, requires that the msr kernel module - * be loaded to access these instructions from user space using device - * /dev/cpu/0/msr. - */ - -static int fd_msr = -1; - -msr_t rdmsr(int addr) -{ - uint32_t buf[2]; - msr_t msr = { 0xffffffff, 0xffffffff }; - - if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { - msg_perr("Could not lseek() MSR: %s\n", strerror(errno)); - close(fd_msr); - exit(1); - } - - if (read(fd_msr, buf, 8) == 8) { - msr.lo = buf[0]; - msr.hi = buf[1]; - return msr; - } - - if (errno != EIO) { - // A severe error. - msg_perr("Could not read() MSR: %s\n", strerror(errno)); - close(fd_msr); - exit(1); - } - - return msr; -} - -int wrmsr(int addr, msr_t msr) -{ - uint32_t buf[2]; - buf[0] = msr.lo; - buf[1] = msr.hi; - - if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { - msg_perr("Could not lseek() MSR: %s\n", strerror(errno)); - close(fd_msr); - exit(1); - } - - if (write(fd_msr, buf, 8) != 8 && errno != EIO) { - msg_perr("Could not write() MSR: %s\n", strerror(errno)); - close(fd_msr); - exit(1); - } - - /* Some MSRs must not be written. */ - if (errno == EIO) - return -1; - - return 0; -} - -int setup_cpu_msr(int cpu) -{ - char msrfilename[64] = { 0 }; - snprintf(msrfilename, sizeof(msrfilename), "/dev/cpu/%d/msr", cpu); - - if (fd_msr != -1) { - msg_pinfo("MSR was already initialized\n"); - return -1; - } - - fd_msr = open(msrfilename, O_RDWR); - - if (fd_msr < 0) { - msg_perr("Error while opening %s: %s\n", msrfilename, strerror(errno)); - msg_pinfo("Did you run 'modprobe msr'?\n"); - return -1; - } - - return 0; -} - -void cleanup_cpu_msr(void) -{ - if (fd_msr == -1) { - msg_pinfo("No MSR initialized.\n"); - return; - } - - close(fd_msr); - - /* Clear MSR file descriptor. */ - fd_msr = -1; -} -#elif defined(__OpenBSD__) && defined (__i386__) /* This does only work for certain AMD Geode LX systems see amdmsr(4). */ -#include <sys/ioctl.h> -#include <machine/amdmsr.h> - -static int fd_msr = -1; - -msr_t rdmsr(int addr) -{ - struct amdmsr_req args; - - msr_t msr = { 0xffffffff, 0xffffffff }; - - args.addr = (uint32_t)addr; - - if (ioctl(fd_msr, RDMSR, &args) < 0) { - msg_perr("Error while executing RDMSR ioctl: %s\n", strerror(errno)); - close(fd_msr); - exit(1); - } - - msr.lo = args.val & 0xffffffff; - msr.hi = args.val >> 32; - - return msr; -} - -int wrmsr(int addr, msr_t msr) -{ - struct amdmsr_req args; - - args.addr = addr; - args.val = (((uint64_t)msr.hi) << 32) | msr.lo; - - if (ioctl(fd_msr, WRMSR, &args) < 0) { - msg_perr("Error while executing WRMSR ioctl: %s\n", strerror(errno)); - close(fd_msr); - exit(1); - } - - return 0; -} - -int setup_cpu_msr(int cpu) -{ - char msrfilename[64] = { 0 }; - snprintf(msrfilename, sizeof(msrfilename), "/dev/amdmsr"); - - if (fd_msr != -1) { - msg_pinfo("MSR was already initialized\n"); - return -1; - } - - fd_msr = open(msrfilename, O_RDWR); - - if (fd_msr < 0) { - msg_perr("Error while opening %s: %s\n", msrfilename, strerror(errno)); - return -1; - } - - return 0; -} - -void cleanup_cpu_msr(void) -{ - if (fd_msr == -1) { - msg_pinfo("No MSR initialized.\n"); - return; - } - - close(fd_msr); - - /* Clear MSR file descriptor. */ - fd_msr = -1; -} - -#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) -#include <sys/ioctl.h> - -typedef struct { - int msr; - uint64_t data; -} cpu_msr_args_t; -#define CPU_RDMSR _IOWR('c', 1, cpu_msr_args_t) -#define CPU_WRMSR _IOWR('c', 2, cpu_msr_args_t) - -static int fd_msr = -1; - -msr_t rdmsr(int addr) -{ - cpu_msr_args_t args; - - msr_t msr = { 0xffffffff, 0xffffffff }; - - args.msr = addr; - - if (ioctl(fd_msr, CPU_RDMSR, &args) < 0) { - msg_perr("Error while executing CPU_RDMSR ioctl: %s\n", strerror(errno)); - close(fd_msr); - exit(1); - } - - msr.lo = args.data & 0xffffffff; - msr.hi = args.data >> 32; - - return msr; -} - -int wrmsr(int addr, msr_t msr) -{ - cpu_msr_args_t args; - - args.msr = addr; - args.data = (((uint64_t)msr.hi) << 32) | msr.lo; - - if (ioctl(fd_msr, CPU_WRMSR, &args) < 0) { - msg_perr("Error while executing CPU_WRMSR ioctl: %s\n", strerror(errno)); - close(fd_msr); - exit(1); - } - - return 0; -} - -int setup_cpu_msr(int cpu) -{ - char msrfilename[64] = { 0 }; - snprintf(msrfilename, sizeof(msrfilename), "/dev/cpu%d", cpu); - - if (fd_msr != -1) { - msg_pinfo("MSR was already initialized\n"); - return -1; - } - - fd_msr = open(msrfilename, O_RDWR); - - if (fd_msr < 0) { - msg_perr("Error while opening %s: %s\n", msrfilename, strerror(errno)); - msg_pinfo("Did you install ports/sysutils/devcpu?\n"); - return -1; - } - - return 0; -} - -void cleanup_cpu_msr(void) -{ - if (fd_msr == -1) { - msg_pinfo("No MSR initialized.\n"); - return; - } - - close(fd_msr); - - /* Clear MSR file descriptor. */ - fd_msr = -1; -} - -#elif defined(__MACH__) && defined(__APPLE__) -/* rdmsr() and wrmsr() are provided by DirectHW which needs neither setup nor cleanup. */ -int setup_cpu_msr(int cpu) -{ - // Always succeed for now - return 0; -} - -void cleanup_cpu_msr(void) -{ - // Nothing, yet. -} -#elif defined(__LIBPAYLOAD__) -msr_t libpayload_rdmsr(int addr) -{ - msr_t msr; - unsigned long long val = _rdmsr(addr); - msr.lo = val & 0xffffffff; - msr.hi = val >> 32; - return msr; -} - -int libpayload_wrmsr(int addr, msr_t msr) -{ - _wrmsr(addr, msr.lo | ((unsigned long long)msr.hi << 32)); - return 0; -} - -int setup_cpu_msr(int cpu) -{ - return 0; -} - -void cleanup_cpu_msr(void) -{ -} -#else -/* default MSR implementation */ -msr_t rdmsr(int addr) -{ - msr_t ret = { 0xffffffff, 0xffffffff }; - - return ret; -} - -int wrmsr(int addr, msr_t msr) -{ - return -1; -} - -int setup_cpu_msr(int cpu) -{ - msg_pinfo("No MSR support for your OS yet.\n"); - return -1; -} - -void cleanup_cpu_msr(void) -{ - // Nothing, yet. -} -#endif // OS switches for MSR code -#else // x86 -/* Does MSR exist on non-x86 architectures? */ -#endif // arch switches for MSR code -#endif // CONFIG_INTERNAL == 1 diff --git a/programmer.h b/programmer.h index b8b5bbc..c4af35a 100644 --- a/programmer.h +++ b/programmer.h @@ -238,10 +238,8 @@ void *physmap_ro_unaligned(const char *descr, uintptr_t phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); void physunmap_unaligned(void *virt_addr, size_t len); -#if CONFIG_INTERNAL == 1 -int setup_cpu_msr(int cpu); -void cleanup_cpu_msr(void); +#if CONFIG_INTERNAL == 1 /* cbtable.c */ int cb_parse_table(const char **vendor, const char **model); int cb_check_image(const uint8_t *bios, unsigned int size); -- To view, visit https://review.coreboot.org/c/flashrom/+/60111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idc9ce9df3ea1e291ad469de59467646b294119c4 Gerrit-Change-Number: 60111 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

1 0

Change in flashrom[master]: hwaccess: split out x86 port I/O related function into own files
by Thomas Heijligen (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Nico Huber, Angel Pons. Hello build bot (Jenkins), Nico Huber, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/60110 to look at the new patch set (#2). Change subject: hwaccess: split out x86 port I/O related function into own files ...................................................................... hwaccess: split out x86 port I/O related function into own files Change-Id: I372b4a409f036da766c42bc406b596bc41b0f75a Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M Makefile M amd_imc.c M atahpt.c M atapromise.c M atavia.c M board_enable.c M chipset_enable.c M drkaiser.c M gfxnvidia.c M hwaccess.c M hwaccess.h A hwaccess_x86_io.c M hwaccess_x86_io.h M internal.c M it8212.c M it85spi.c M it87spi.c M meson.build M nic3com.c M nicintel.c M nicintel_eeprom.c M nicintel_spi.c M nicnatsemi.c M nicrealtek.c M ogp_spi.c M programmer.h M rayer_spi.c M satamv.c M satasii.c M wbsio_spi.c 30 files changed, 116 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/60110/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/60110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I372b4a409f036da766c42bc406b596bc41b0f75a Gerrit-Change-Number: 60110 Gerrit-PatchSet: 2 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in flashrom[master]: hwaccess: split out x86 port I/O related function into own files
by Thomas Heijligen (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Nico Huber, Angel Pons. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/60110 ) Change subject: hwaccess: split out x86 port I/O related function into own files ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: TODO: warning: implicit declaration of function in tests commit message -- To view, visit https://review.coreboot.org/c/flashrom/+/60110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I372b4a409f036da766c42bc406b596bc41b0f75a Gerrit-Change-Number: 60110 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 14 Dec 2021 16:15:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: pcidev: Avoid internal relying on pacc global
by Nico Huber (Code Review) 14 Dec '21

14 Dec '21

Attention is currently required from: Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Peter Marheine. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59275 ) Change subject: pcidev: Avoid internal relying on pacc global ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/59275/comment/7983910a_7add15be PS2, Line 7: Avoid internal relying on pacc global > `internal relying` should either be `internal reliance` or `internally relying` to be grammatically […] I guess the "internal" programmer was meant. File internal.c: https://review.coreboot.org/c/flashrom/+/59275/comment/1de2fbe7_592b7eed PS2, Line 38: NULL I guess this just happened to work. We might need `pacc` here too eventually. -- To view, visit https://review.coreboot.org/c/flashrom/+/59275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id83bfd41f785f907e52a65a6689e8c7016fc1b77 Gerrit-Change-Number: 59275 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Tue, 14 Dec 2021 16:06:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in flashrom[master]: hwaccess: split out x86 port I/O related function into own files
by Thomas Heijligen (Code Review) 14 Dec '21

14 Dec '21

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/60110 ) Change subject: hwaccess: split out x86 port I/O related function into own files ...................................................................... hwaccess: split out x86 port I/O related function into own files Change-Id: I372b4a409f036da766c42bc406b596bc41b0f75a Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M Makefile M amd_imc.c M atahpt.c M atapromise.c M atavia.c M board_enable.c M chipset_enable.c M drkaiser.c M gfxnvidia.c M hwaccess.c M hwaccess.h A hwaccess_x86_io.c M hwaccess_x86_io.h M internal.c M it8212.c M it85spi.c M it87spi.c M meson.build M nic3com.c M nicintel.c M nicintel_eeprom.c M nicintel_spi.c M nicnatsemi.c M nicrealtek.c M ogp_spi.c M programmer.h M rayer_spi.c M satamv.c M satasii.c M wbsio_spi.c 30 files changed, 116 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/60110/1 diff --git a/Makefile b/Makefile index b196d98..7207abb 100644 --- a/Makefile +++ b/Makefile @@ -782,8 +782,8 @@ ifneq ($(NEED_RAW_ACCESS), ) # Raw memory, MSR or PCI port I/O access. -FEATURE_CFLAGS += -D'NEED_RAW_ACCESS=1' -PROGRAMMER_OBJS += physmap.o hwaccess.o +FEATURE_CFLAGS += -D'NEED_RAW_ACCESS=1' -D'__FLASHROM_HAVE_OUTB__=1' +PROGRAMMER_OBJS += physmap.o hwaccess.o hwaccess_x86_io.o ifeq ($(TARGET_OS), NetBSD) ifeq ($(ARCH), x86) diff --git a/amd_imc.c b/amd_imc.c index f2f0972..93096f6 100644 --- a/amd_imc.c +++ b/amd_imc.c @@ -18,6 +18,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "spi.h" #include "platform/pci.h" diff --git a/atahpt.c b/atahpt.c index d2712b8..70f0e6a 100644 --- a/atahpt.c +++ b/atahpt.c @@ -19,6 +19,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" #define BIOS_ROM_ADDR 0x90 diff --git a/atapromise.c b/atapromise.c index 92eba0c..56abc26 100644 --- a/atapromise.c +++ b/atapromise.c @@ -19,6 +19,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" #define MAX_ROM_DECODE (32 * 1024) diff --git a/atavia.c b/atavia.c index 6370d91..631c73e 100644 --- a/atavia.c +++ b/atavia.c @@ -21,6 +21,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" #define PCI_VENDOR_ID_VIA 0x1106 diff --git a/board_enable.c b/board_enable.c index 339408a..4ca7101 100644 --- a/board_enable.c +++ b/board_enable.c @@ -26,6 +26,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" #if defined(__i386__) || defined(__x86_64__) diff --git a/chipset_enable.c b/chipset_enable.c index 8588443..517918e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -34,6 +34,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" #define NOT_DONE_YET 1 diff --git a/drkaiser.c b/drkaiser.c index 34b204e..565a45e 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -18,6 +18,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" #define PCI_VENDOR_ID_DRKAISER 0x1803 diff --git a/gfxnvidia.c b/gfxnvidia.c index e85ce68..0d3ef39 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -19,6 +19,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" #define PCI_VENDOR_ID_NVIDIA 0x10de diff --git a/hwaccess.c b/hwaccess.c index 9bfd8ea..4e8a274 100644 --- a/hwaccess.c +++ b/hwaccess.c @@ -25,17 +25,8 @@ #include <fcntl.h> #endif #include "flash.h" -#include "programmer.h" #include "hwaccess.h" -#if USE_IOPERM -#include <sys/io.h> -#endif - -#if (defined (__i386__) || defined (__x86_64__) || defined(__amd64__)) && USE_DEV_IO -int io_fd; -#endif - /* Prevent reordering and/or merging of reads/writes to hardware. * Such reordering and/or merging would break device accesses which depend on the exact access order. */ @@ -70,59 +61,6 @@ #endif } -#if (defined (__i386__) || defined (__x86_64__) || defined(__amd64__)) && !(defined(__DJGPP__) || defined(__LIBPAYLOAD__)) -static int release_io_perms(void *p) -{ -#if defined (__sun) - sysi86(SI86V86, V86SC_IOPL, 0); -#elif USE_DEV_IO - close(io_fd); -#elif USE_IOPERM - ioperm(0, 65536, 0); -#elif USE_IOPL - iopl(0); -#endif - return 0; -} - -/* Get I/O permissions with automatic permission release on shutdown. */ -int rget_io_perms(void) -{ - #if defined (__sun) - if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { -#elif USE_DEV_IO - if ((io_fd = open("/dev/io", O_RDWR)) < 0) { -#elif USE_IOPERM - if (ioperm(0, 65536, 1) != 0) { -#elif USE_IOPL - if (iopl(3) != 0) { -#endif - msg_perr("ERROR: Could not get I/O privileges (%s).\n", strerror(errno)); - msg_perr("You need to be root.\n"); -#if defined (__OpenBSD__) - msg_perr("If you are root already please set securelevel=-1 in /etc/rc.securelevel and\n" - "reboot, or reboot into single user mode.\n"); -#elif defined(__NetBSD__) - msg_perr("If you are root already please reboot into single user mode or make sure\n" - "that your kernel configuration has the option INSECURE enabled.\n"); -#endif - return 1; - } else { - register_shutdown(release_io_perms, NULL); - } - return 0; -} - -#else - -/* DJGPP and libpayload environments have full PCI port I/O permissions by default. */ -/* PCI port I/O support is unimplemented on PPC/MIPS and unavailable on ARM. */ -int rget_io_perms(void) -{ - return 0; -} -#endif - void mmio_writeb(uint8_t val, void *addr) { *(volatile uint8_t *) addr = val; diff --git a/hwaccess.h b/hwaccess.h index e5edcfa..5b7b079 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -124,8 +124,6 @@ #if NEED_RAW_ACCESS == 1 && (defined (__i386__) || defined (__x86_64__) || defined(__amd64__)) -#include "hwaccess_x86_io.h" - #if !(defined(__MACH__) && defined(__APPLE__)) && !defined(__FreeBSD__) && !defined(__FreeBSD_kernel__) && !defined(__DragonFly__) && !defined(__LIBPAYLOAD__) typedef struct { uint32_t hi, lo; } msr_t; msr_t rdmsr(int addr); diff --git a/hwaccess_x86_io.c b/hwaccess_x86_io.c new file mode 100644 index 0000000..9f0eb6e --- /dev/null +++ b/hwaccess_x86_io.c @@ -0,0 +1,87 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009,2010 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <errno.h> +#include <string.h> +#if !defined (__DJGPP__) && !defined(__LIBPAYLOAD__) +/* No file access needed/possible to get hardware access permissions. */ +#include <unistd.h> +#include <fcntl.h> +#endif + +#include "hwaccess_x86_io.h" +#include "flash.h" + +#if USE_IOPERM +#include <sys/io.h> +#endif + +#if (defined (__i386__) || defined (__x86_64__) || defined(__amd64__)) && USE_DEV_IO +int io_fd; +#endif + +#if (defined (__i386__) || defined (__x86_64__) || defined(__amd64__)) && !(defined(__DJGPP__) || defined(__LIBPAYLOAD__)) +static int release_io_perms(void *p) +{ +#if defined (__sun) + sysi86(SI86V86, V86SC_IOPL, 0); +#elif USE_DEV_IO + close(io_fd); +#elif USE_IOPERM + ioperm(0, 65536, 0); +#elif USE_IOPL + iopl(0); +#endif + return 0; +} + +/* Get I/O permissions with automatic permission release on shutdown. */ +int rget_io_perms(void) +{ + #if defined (__sun) + if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { +#elif USE_DEV_IO + if ((io_fd = open("/dev/io", O_RDWR)) < 0) { +#elif USE_IOPERM + if (ioperm(0, 65536, 1) != 0) { +#elif USE_IOPL + if (iopl(3) != 0) { +#endif + msg_perr("ERROR: Could not get I/O privileges (%s).\n", strerror(errno)); + msg_perr("You need to be root.\n"); +#if defined (__OpenBSD__) + msg_perr("If you are root already please set securelevel=-1 in /etc/rc.securelevel and\n" + "reboot, or reboot into single user mode.\n"); +#elif defined(__NetBSD__) + msg_perr("If you are root already please reboot into single user mode or make sure\n" + "that your kernel configuration has the option INSECURE enabled.\n"); +#endif + return 1; + } else { + register_shutdown(release_io_perms, NULL); + } + return 0; +} + +#else + +/* DJGPP and libpayload environments have full PCI port I/O permissions by default. */ +/* PCI port I/O support is unimplemented on PPC/MIPS and unavailable on ARM. */ +int rget_io_perms(void) +{ + return 0; +} +#endif \ No newline at end of file diff --git a/hwaccess_x86_io.h b/hwaccess_x86_io.h index 63692b8..0d16fdd 100644 --- a/hwaccess_x86_io.h +++ b/hwaccess_x86_io.h @@ -29,8 +29,6 @@ #include <sys/io.h> #endif -#define __FLASHROM_HAVE_OUTB__ 1 - /* for iopl and outb under Solaris */ #if defined (__sun) #include <sys/sysi86.h> @@ -38,6 +36,8 @@ #include <asm/sunddi.h> #endif +int rget_io_perms(void); + /* Clarification about OUTB/OUTW/OUTL argument order: * OUT[BWL](val, port) */ diff --git a/internal.c b/internal.c index 4a8e27b..7de1d6a 100644 --- a/internal.c +++ b/internal.c @@ -20,6 +20,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" int is_laptop = 0; diff --git a/it8212.c b/it8212.c index 60997f7..80da2b1 100644 --- a/it8212.c +++ b/it8212.c @@ -18,6 +18,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" static uint8_t *it8212_bar = NULL; diff --git a/it85spi.c b/it85spi.c index 17e4e10..b1074d1 100644 --- a/it85spi.c +++ b/it85spi.c @@ -27,6 +27,7 @@ #include "spi.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #define MAX_TIMEOUT 100000 #define MAX_TRY 5 diff --git a/it87spi.c b/it87spi.c index 5f6fb65..0944915 100644 --- a/it87spi.c +++ b/it87spi.c @@ -26,6 +26,7 @@ #include "chipdrivers.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "spi.h" #define ITE_SUPERIO_PORT1 0x2e diff --git a/meson.build b/meson.build index 85f40ba..5cbcac2 100644 --- a/meson.build +++ b/meson.build @@ -347,8 +347,10 @@ # raw memory, MSR or PCI port I/O access if need_raw_access srcs += 'hwaccess.c' + srcs += 'hwaccess_x86_io.c' srcs += 'physmap.c' cargs += '-DNEED_RAW_ACCESS=1' + cargs += '-D__FLASHROM_HAVE_OUTB__=1' endif # raw serial IO diff --git a/nic3com.c b/nic3com.c index f7d2a97..21748cc 100644 --- a/nic3com.c +++ b/nic3com.c @@ -18,6 +18,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" #define BIOS_ROM_ADDR 0x04 diff --git a/nicintel.c b/nicintel.c index 1730ca4..7f4eb24 100644 --- a/nicintel.c +++ b/nicintel.c @@ -19,6 +19,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" static uint8_t *nicintel_bar; diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index ab75343..fc2ef40 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -35,6 +35,7 @@ #include "spi.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" #define PCI_VENDOR_ID_INTEL 0x8086 diff --git a/nicintel_spi.c b/nicintel_spi.c index f1ed129..25a6651 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -35,6 +35,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" #define PCI_VENDOR_ID_INTEL 0x8086 diff --git a/nicnatsemi.c b/nicnatsemi.c index 9dd3915..6c7bd61 100644 --- a/nicnatsemi.c +++ b/nicnatsemi.c @@ -18,6 +18,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" #define PCI_VENDOR_ID_NATSEMI 0x100b diff --git a/nicrealtek.c b/nicrealtek.c index 0bf60fd..4274e56 100644 --- a/nicrealtek.c +++ b/nicrealtek.c @@ -18,6 +18,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" #define PCI_VENDOR_ID_REALTEK 0x10ec diff --git a/ogp_spi.c b/ogp_spi.c index 105f468..4a4934e 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -19,6 +19,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" #define PCI_VENDOR_ID_OGP 0x1227 diff --git a/programmer.h b/programmer.h index b4f04e7..b8b5bbc 100644 --- a/programmer.h +++ b/programmer.h @@ -271,7 +271,6 @@ struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, uint16_t card_vendor, uint16_t card_device); #endif -int rget_io_perms(void); #if CONFIG_INTERNAL == 1 extern int is_laptop; extern int laptop_ok; diff --git a/rayer_spi.c b/rayer_spi.c index e65eb78..5fae8b9 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -29,6 +29,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" /* We have two sets of pins, out and in. The numbers for both sets are * independent and are bitshift values, not real pin numbers. diff --git a/satamv.c b/satamv.c index b69350f..8543f53 100644 --- a/satamv.c +++ b/satamv.c @@ -20,6 +20,7 @@ #include "flash.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" static uint8_t *mv_bar; diff --git a/satasii.c b/satasii.c index d015f7f..2f220d1 100644 --- a/satasii.c +++ b/satasii.c @@ -18,6 +18,7 @@ #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "platform/pci.h" #define PCI_VENDOR_ID_SII 0x1095 diff --git a/wbsio_spi.c b/wbsio_spi.c index 60b725f..805abf7 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -20,6 +20,7 @@ #include "chipdrivers.h" #include "programmer.h" #include "hwaccess.h" +#include "hwaccess_x86_io.h" #include "spi.h" #define WBSIO_PORT1 0x2e -- To view, visit https://review.coreboot.org/c/flashrom/+/60110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I372b4a409f036da766c42bc406b596bc41b0f75a Gerrit-Change-Number: 60110 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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flashrom-gerrit December 2021