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Change subject: tests: test write protection
......................................................................
tests: test write protection
Tests both WP implementation and its emulation in dummy programmer.
Change-Id: I49af7f6d173eb4c56c22d80b01a473b8c499c0f8
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
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M tests/meson.build
M tests/tests.c
M tests/tests.h
4 files changed, 443 insertions(+), 0 deletions(-)
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Change subject: dummyflasher: enforce write protection for W25Q128FV
......................................................................
dummyflasher: enforce write protection for W25Q128FV
Start taking bits related to write protection into account.
Also add "hwwp" parameter for dummy programmer that sets state of WP
pin (not inverted value).
dummyflasher doesn't store state of the chip between runs and flashrom
allows running only one command, so testing WP in this way is limited.
However, WP options can be combined with other operations and are
executed prior to them, so certain scenarios can be checked.
List possible ranges:
flashrom -p dummy:emulate=W25Q128FV,hwwp=yes --wp-list
Set a particular range and check status is correct:
flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \
--wp-enable \
--wp-range=0x00100000,0x00f00000 \
--wp-status
Enable write protection and try erasing/writing (erasing here):
# this fails
flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \
--wp-range=0,0x00c00000 \
--wp-enable \
--erase
Write protecting empty range has no effect:
# this succeeds
flashrom -p dummy:emulate=W25Q128FV,hwwp=yes \
--wp-range=0,0 \
--wp-enable \
--erase
Change-Id: I9fd1417f941186391bd213bd355530143c8f04a0
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M dummyflasher.c
M flashrom.8.tmpl
2 files changed, 155 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/74/59074/15
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Change subject: dummyflasher: emulate SR2 for W25Q128FV
......................................................................
dummyflasher: emulate SR2 for W25Q128FV
Enable emulation of SR2 for W25Q128FV and provide logic for updating
it (mask of read-only bits that can't be set from outside).
W25Q128FV has three status registers, but no plans to use the third
one yet.
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I'd like you to reexamine a change. Please visit
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Change subject: dummyflasher: add SR2 emulation harness
......................................................................
dummyflasher: add SR2 emulation harness
Prepare everything for emulating SR2 for chips that have it.
This is needed for accessing second SRP bit which is involved in write
protection. The emulated register doesn't affect anything yet and will
be tested by write-protection tests.
Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
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M flashrom.8.tmpl
2 files changed, 79 insertions(+), 15 deletions(-)
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Change subject: flashchips: enable write-protection for W25Q{64,128}.V
......................................................................
flashchips: enable write-protection for W25Q{64,128}.V
Configuration for W25Q64 was tested on hardware.
Emulation of W25Q128 in dummyflasher will be extended to support WP.
Haven't tested this one on hardware, but it's the same configuration as
for W25Q64.
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Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flashchips.c
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58736 )
Change subject: ichspi: Extract handling programmer param into a function
......................................................................
Patch Set 1: Code-Review+2
(3 comments)
Patchset:
PS1:
Tested with Panther Point (7 series PCH).
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/58736/comment/106d0bc0_59cbe342
PS1, Line 1760: *arg
Could be `*const arg`.
https://review.coreboot.org/c/flashrom/+/58736/comment/38374209_19f2ee28
PS1, Line 1776: arg);
Line break :)
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59278 )
Change subject: programmer.h: Make pacc global state static local
......................................................................
Patch Set 3:
(1 comment)
File programmer.h:
https://review.coreboot.org/c/flashrom/+/59278/comment/e21f2b88_3838eb07
PS3, Line 122: // FIXME: Fix chipset_enable.c usage and remove pcidev_set_pacc().
> Even if `pacc` no longer has global visibility, it's still global state. […]
The alternative would be to place a dedicated shutdown function around everything
that may encounter the naughty Intel spi dev. I originally decided against it,
because that would mean we have to avoid rpci_write* functions in places where
it's not obvious why we do that. For instance, we could end up placing a comment
above every affacted pci_write* call.
However, I'm not even sure if we can get rid of the `pacc` global without adding
parameters (no matter the Intel kludge). Which brings me to another awkward
solution: drop the whole rpci_write* infrastructure. I'm not sure if it solves
more problems than it invites. Eventually these functions would even need a
flashrom context parameter to register their shutdown things (because that's
also a place where we need to get rid of global state).
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Change subject: ichspi: Split very long init function into two
......................................................................
Patch Set 1: Code-Review+1
(6 comments)
Patchset:
PS1:
Looks quite nice overall, just one nit and a little whitspace.
Tested probe and read on Panther Point (7 series PCH). Data and
verbose logs look the same.
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/58735/comment/ec6e3838_aa515ac0
PS1, Line 1717: msg_pdbg("0x00: 0x%04x (SPIS)\n",
: mmio_readw(spibar + 0));
: msg_pdbg("0x02: 0x%04x (SPIC)\n",
: mmio_readw(spibar + 2));
: msg_pdbg("0x04: 0x%08x (SPIA)\n",
: mmio_readl(spibar + 4));
: ichspi_bbar = mmio_readl(spibar + 0x50);
: msg_pdbg("0x50: 0x%08x (BBAR)\n",
: ichspi_bbar);
: msg_pdbg("0x54: 0x%04x (PREOP)\n",
: mmio_readw(spibar + 0x54));
: msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
: mmio_readw(spibar + 0x56));
: msg_pdbg("0x58: 0x%08x (OPMENU)\n",
: mmio_readl(spibar + 0x58));
: msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
: mmio_readl(spibar + 0x5c));
Please remove unnecessary line breaks. If you put tabs after the commas,
it might actually look nice ;)
https://review.coreboot.org/c/flashrom/+/58735/comment/1d39bf50_93feff6e
PS1, Line 1739: mmio_readl(spibar + offs), i);
I guess this also doesn't need a line break.
https://review.coreboot.org/c/flashrom/+/58735/comment/f45726dd_4cd8430c
PS1, Line 1836: arg);
Another unnecessary line break.
https://review.coreboot.org/c/flashrom/+/58735/comment/7d6cdd3a_1da3ce53
PS1, Line 1917: );
Drop line break?
https://review.coreboot.org/c/flashrom/+/58735/comment/90b8becc_bbe3a304
PS1, Line 2068: return 0;
You've replaced the `break` statements above with `return` ones. So this
can't be reached anymore. Would the compiler mind if we drop it?
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Change subject: pcidev: Avoid internal programmer relying on pacc global
......................................................................
Patch Set 3:
(2 comments)
File internal.c:
https://review.coreboot.org/c/flashrom/+/59275/comment/d5aeccf1_12ee4ee6
PS3, Line 41: temp = pcidev_scandev(&filter, NULL);
: for (; temp; temp = pcidev_scandev(&filter, temp)) {
I guess this could also be written as
while ((temp = pcidev_scandev(&filter, temp))
with `temp` initialized to `NULL`, ofc.
https://review.coreboot.org/c/flashrom/+/59275/comment/85f936f7_86d32eda
PS3, Line 43: if (pci_filter_match(&filter, temp)) {
That's what pcidev_scandev() does, isn't it?
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Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59276 )
Change subject: pcidev: Move pci_get_dev() logic into canonical place
......................................................................
Patch Set 2:
(1 comment)
File pcidev.c:
https://review.coreboot.org/c/flashrom/+/59276/comment/045fe97c_d68e8b3e
PS2, Line 162: OLD_PCI_GET_DEV
> Thomas already looked into this and the old version practically pre-dates […]
+1
Would be nice to have an minimum version for the library set in the build system. But that's not for this patch.
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