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Change subject: dummyflasher: add SR2 emulation harness
......................................................................
Patch Set 16:
(1 comment)
File dummyflasher.c:
https://review.coreboot.org/c/flashrom/+/59072/comment/d2c33ec4_ea8f4057
PS14, Line 346: if (writecnt == 3)
> Thanks, the two conditions should be in sync.
Oh great! Also maybe I am missing something, but why two ifs are not one if? it can do the job and then print a message?
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Change subject: ichspi: Split very long init function into two
......................................................................
Patch Set 1:
(1 comment)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/58735/comment/07c2e4e3_5364da8e
PS1, Line 2049: else {
: register_spi_master(&spi_master_ich9, NULL);
: }
> Not in this commit, please.
I fully agree
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58477 )
Change subject: flashchips: add writeprotect bit layout map to chips
......................................................................
Patch Set 21:
(4 comments)
File flash.h:
https://review.coreboot.org/c/flashrom/+/58477/comment/3db77e9e_1ce7f9ca
PS21, Line 192: 0
Why give these numbers? Is there anything to sync with?
https://review.coreboot.org/c/flashrom/+/58477/comment/64a5e9cb_76f52562
PS21, Line 196: };
If we'd ignore the enum types, i.e. use `uint8_t` for all members, we could
squeeze everything in 1B, saving 92% of the space.
https://review.coreboot.org/c/flashrom/+/58477/comment/614d3a06_c9c09d6e
PS21, Line 283: */
We should generally try to find a better representation for the flash chips.
The database is already too big for some use cases. With the current `struct
reg_bit_map` definition, this bloats the database by 23%. Fairly compressable
though.
You don't have to use common definitions with a pointer btw. I played
with this once for the block erasers. The only diff in the database was
- .block_erasers =
+ .block_erasers = (const struct block_eraser[NUM_ERASEFUNCTIONS])
all over it. Together with `-fmerge-all-constants` GCC could join the
common definitions.
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/58477/comment/d963df53_9cc6cd65
PS9, Line 6760: {STATUS1, 5, RW}
> I got the bits mixed up, thanks for noticing!
You could, maybe should, extend selfcheck(), e.g. add something similar to
selfcheck_eraseblocks(). Or add a unit test (but there were always plans to
make the chip database more runtime flexible). We could definitely catch
such issues.
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Change subject: ichspi: Extract handling programmer param into a function
......................................................................
Patch Set 1:
(1 comment)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/58736/comment/6dfe6720_f0b830ab
PS1, Line 1761: if (arg && !strcmp(arg, "hwseq")) {
> Just a thought: This would be more readable (and also look better) as a switch-case I think.
If you have any idea how to achieve that in C, please in a separate commit.
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Change subject: ichspi: Split very long init function into two
......................................................................
Patch Set 1:
(1 comment)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/58735/comment/75c61f97_73f963fb
PS1, Line 2049: else {
: register_spi_master(&spi_master_ich9, NULL);
: }
> nit: Reverse the condition so that the simple case comes first
Not in this commit, please.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58570 )
Change subject: spi25_statusreg,flashchips: add SR2 read/write support
......................................................................
Patch Set 18:
(2 comments)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/58570/comment/549e9b15_1d5ea58e
PS18, Line 6711: FEATURE_WRSR_EXT
The datasheet suggests this won't work, AFAICT, and I guess this path
is not tested because the code checks `FEATURE_WRSR2` first? You could
test it by removing the latter.
https://review.coreboot.org/c/flashrom/+/58570/comment/5dbbe1d7_f85a54f2
PS18, Line 6872: .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
Spurious change?
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58475 )
Change subject: spi25_statusreg: make register read/write functions generic
......................................................................
Patch Set 15:
(2 comments)
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/58475/comment/4cc9ba4e_9de62a2c
PS15, Line 89: }
Why not use a switch/case? It would make it easier to provide proper error
messages if an unhandled reg value is passed.
https://review.coreboot.org/c/flashrom/+/58475/comment/9850dcf5_1909916b
PS15, Line 91: not supported by chip\
Or not supported by this function?
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Change subject: spi25_statusreg: make register read/write functions generic
......................................................................
Patch Set 15:
(5 comments)
File flash.h:
https://review.coreboot.org/c/flashrom/+/58475/comment/7a0ce1e9_eb7236e1
PS15, Line 170: INVALID_REG = 0,
: STATUS1,
: STATUS2,
: CONFIG1,
Please add entries in the commits that make use of them. Took me rather
long to realize that I can't find a commit for CONFIG1 probably because
it's not used?
File flash.h:
https://review.coreboot.org/c/flashrom/+/58475/comment/5e844940_7a58ff2f
PS14, Line 169: enum flash_reg {
: INVALID_REG = 0,
: STATUS1,
: STATUS2,
: CONFIG1,
: };
: #define MAX_REGISTERS 4
> Also, this is specific to SPI flash chips. I'm not sure if it should be here.
`MAX_REGISTERS` is only used in `writeprotect.c` AFAICS, so it would belong
there. Or maybe as a last enum element? It would automatically have the
correct value if starting at 0.
IMO, the enum belongs to the API functions.
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/58475/comment/07f7a6d7_10339085
PS14, Line 51: int result = spi_send_multicommand(flash, cmds);
> Would be good to check with manibuilder if this causes problems with unusual toolchains (e.g. […]
What do you mean? What could cause problems?
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/58475/comment/a1757286_129a092c
PS15, Line 63: */
I have doubts that this is true for any modern chip. "allow running RDSR
only once"? when? only once after an erase/write command? how should one
keep track of it?
So I would pretty much prefer to start testing writes to registers != SR1
without this delay. Otherwise we'd have to keep assuming forever that
it's necessary.
https://review.coreboot.org/c/flashrom/+/58475/comment/262245b3_98401a39
PS15, Line 84: *
Please drop this dangling asterisk or add a line break after the first
/ before the last.
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Change subject: ichspi: Extract initialisation of swseq and hwseq into a function
......................................................................
Patch Set 1:
(1 comment)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/58737/comment/13b86a28_6fe187bf
PS1, Line 1818: }
Add a line break here
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