October 2021 - flashrom-gerrit

Change in flashrom[master]: ich_descriptors_tool/Makefile: TARGET_OS is given as cmdline argument
by Thomas Heijligen (Code Review) 20 Oct '21

20 Oct '21

Attention is currently required from: Nico Huber. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58468 ) Change subject: ich_descriptors_tool/Makefile: TARGET_OS is given as cmdline argument ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Doesn't this break standalone builds? When building stand-alone for MinGW or DOS you have to pass TARGET_OS=MinGW/DOS ¯\_(ツ)_/¯ EXEC_SUFFIX get also passed to ich_descriptor_tool and the Makefile has some logic to determinate that too -- To view, visit https://review.coreboot.org/c/flashrom/+/58468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I353c3de250167994a4aea1edfef57d839e900d78 Gerrit-Change-Number: 58468 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 20 Oct 2021 18:53:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in flashrom[master]: [RFC] writeprotect: add range decoding function
by Nikolai Artemiev (Code Review) 20 Oct '21

20 Oct '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/58480 to look at the new patch set (#3). Change subject: [RFC] writeprotect: add range decoding function ...................................................................... [RFC] writeprotect: add range decoding function Allow chips to specify functions that map status register bits to protection ranges. These are used to enumerate available ranges and determine the protection state of chips. The patch also adds a range decoding function for the example chips. Many other chips can also be handled by it, though some will require different functions (e.g. MX25L6406 and related chips). Another approach that has been tried in cros flashrom is maintaining tables of range data, but it quickly becomes error prone and hard to validate. Using a function to interpret the ranges allows compact encoding with most chips and is flexible enough to allow chips with less predictable ranges to be handled as well. BUG=b:195381327,b:153800563 TEST=dumped range tables, checked against datasheets BRANCH=none Change-Id: Id163ed80938a946a502ed116e48e8236e36eb203 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M Makefile M chipdrivers.h M flash.h M flashchips.c M meson.build M writeprotect.c A writeprotect_ranges.c 7 files changed, 118 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/80/58480/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/58480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id163ed80938a946a502ed116e48e8236e36eb203 Gerrit-Change-Number: 58480 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: [RFC] writeprotect: implement wp_print_status()
by Nikolai Artemiev (Code Review) 20 Oct '21

20 Oct '21

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/58484 ) Change subject: [RFC] writeprotect: implement wp_print_status() ...................................................................... [RFC] writeprotect: implement wp_print_status() Change-Id: I82441c60c239a5b947b5a2a87b61e7bdf60bee89 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M writeprotect.c 1 file changed, 34 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/84/58484/1 diff --git a/writeprotect.c b/writeprotect.c index e6e8df2..526e525 100644 --- a/writeprotect.c +++ b/writeprotect.c @@ -441,8 +441,40 @@ return 0; } + +static void print_wp_mode(enum wp_mode mode) +{ + if (mode == WP_MODE_DISABLED) msg_ginfo("disabled"); + if (mode == WP_MODE_HARDWARE) msg_ginfo("hardware"); + if (mode == WP_MODE_POWER_CYCLE) msg_ginfo("powercycle"); + if (mode == WP_MODE_PERMANENT) msg_ginfo("permanent"); +} + + int wp_print_status(struct flashctx *flash) { - /* TODO */ - return 1; + struct wp_chip_state wpst; + struct wp_range range; + enum wp_mode mode; + + if (read_wp_chip_state(flash, &wpst)) + return 1; + + if (decode_wp_mode(&wpst, &mode)) + return 1; + + range.chip_len = flash->chip->total_size * 1024; + flash->chip->decode_range(&wpst, &range); + + msg_ginfo("\nWrite protect chip state: "); + print_wp_chip_state(&wpst); + + msg_ginfo("\n\nProtection range: "); + print_range(&range); + + msg_ginfo("\n\nProtection mode: "); + print_wp_mode(mode); + msg_ginfo("\n"); + + return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/58484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I82441c60c239a5b947b5a2a87b61e7bdf60bee89 Gerrit-Change-Number: 58484 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] writeprotect: implement wp_get_mode() and wp_set_mode()
by Nikolai Artemiev (Code Review) 20 Oct '21

20 Oct '21

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/58483 ) Change subject: [RFC] writeprotect: implement wp_get_mode() and wp_set_mode() ...................................................................... [RFC] writeprotect: implement wp_get_mode() and wp_set_mode() Change-Id: I7b68e940f0e1359281806c98e1da119b4caf8405 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M writeprotect.c 1 file changed, 77 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/58483/1 diff --git a/writeprotect.c b/writeprotect.c index ea10047..e6e8df2 100644 --- a/writeprotect.c +++ b/writeprotect.c @@ -310,16 +310,89 @@ return ret; } +static int decode_wp_mode(struct wp_chip_state *wpst, enum wp_mode *mode) +{ + enum wp_mode mode_table[] = { + WP_MODE_DISABLED, + WP_MODE_HARDWARE, + WP_MODE_POWER_CYCLE, + WP_MODE_PERMANENT, + }; + + uint8_t srp = 0; + for (size_t i = 0; i < wpst->srp_bit_count; i++) + srp |= wpst->srp[i] << i; + + if (srp > 3) + return 1; + + *mode = mode_table[srp]; + return 0; +} + +static int encode_wp_mode(enum wp_mode mode, struct wp_chip_state *wpst) +{ + uint8_t srp; + switch (mode) { + case WP_MODE_DISABLED: + srp = 0; + break; + case WP_MODE_HARDWARE: + srp = 1; + break; + case WP_MODE_POWER_CYCLE: + srp = 2; + break; + case WP_MODE_PERMANENT: + srp = 3; + break; + default: + msg_gerr("Unknown mode!\n"); + return 1; + }; + + /* Set SRP bits in wpst structure. */ + for (size_t i = 0; i < wpst->srp_bit_count; i++) { + wpst->srp[i] = srp & 1; + srp >>= 1; + } + + /* Left over bits => chip does not have enough SRP bits to select mode. */ + if (srp != 0) { + msg_gerr("The chip does not support the requested " + "protection mode.\n"); + return 1; + } + + return 0; +} + + int wp_get_mode(struct flashctx *flash, enum wp_mode *mode) { - /* TODO */ - return 1; + struct wp_chip_state wpst; + if (read_wp_chip_state(flash, &wpst)) + return 1; + + return decode_wp_mode(&wpst, mode); } int wp_set_mode(struct flashctx *flash, enum wp_mode mode) { - /* TODO */ - return 1; + struct wp_chip_state wpst; + if (read_wp_chip_state(flash, &wpst)) + return 1; + + if (encode_wp_mode(mode, &wpst)) { + return 1; + } + + if (write_wp_chip_state(flash, &wpst)) { + return 1; + } + + msg_ginfo("Sucessfully set the requested protection mode.\n"); + return 0; } static void print_range(struct wp_range *range) -- To view, visit https://review.coreboot.org/c/flashrom/+/58483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7b68e940f0e1359281806c98e1da119b4caf8405 Gerrit-Change-Number: 58483 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] writeprotect: implement wp_set_range()
by Nikolai Artemiev (Code Review) 20 Oct '21

20 Oct '21

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/58482 ) Change subject: [RFC] writeprotect: implement wp_set_range() ...................................................................... [RFC] writeprotect: implement wp_set_range() BUG=b:195381327,b:153800563 TEST=flashrom --wp-range BRANCH=none Change-Id: I7d26f43fb05c5828b9839bb57a28fa1088dcd9a0 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M writeprotect.c 1 file changed, 33 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/82/58482/1 diff --git a/writeprotect.c b/writeprotect.c index 884e4d6..ea10047 100644 --- a/writeprotect.c +++ b/writeprotect.c @@ -152,7 +152,6 @@ } return 0; } -void *suppress_unused_warning_for_write_wp_chip_state = write_wp_chip_state; struct wp_range_wpst_pair { struct wp_range range; @@ -276,8 +275,39 @@ int wp_set_range(struct flashctx *flash, const struct wp_range range) { - /* TODO */ - return 1; + struct wp_range_wpst_pair *ranges; + size_t range_count; + + int ret = get_available_ranges(flash, &ranges, &range_count); + if (ret) + return ret; + + /* Search for matching range */ + struct wp_chip_state wpst; + bool found = false; + for (size_t i = 0; i < range_count; i++) { + struct wp_range *range_i = &ranges[i].range; + if (range_i->start == range.start && range_i->len == range.len) { + wpst = ranges[i].wpst; + found = true; + break; + } + } + + free(ranges); + + if (!found) { + msg_gerr("The chip does not support the requested range.\n"); + return 1; + } + + ret = write_wp_chip_state(flash, &wpst); + + if (!ret) { + msg_ginfo("Sucessfully set the requested protection range.\n"); + } + + return ret; } int wp_get_mode(struct flashctx *flash, enum wp_mode *mode) -- To view, visit https://review.coreboot.org/c/flashrom/+/58482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7d26f43fb05c5828b9839bb57a28fa1088dcd9a0 Gerrit-Change-Number: 58482 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] writeprotect: implement wp_list_ranges()
by Nikolai Artemiev (Code Review) 20 Oct '21

20 Oct '21

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/58481 ) Change subject: [RFC] writeprotect: implement wp_list_ranges() ...................................................................... [RFC] writeprotect: implement wp_list_ranges() BUG=b:195381327,b:153800563 TEST=flashrom --wp-list BRANCH=none Change-Id: Id51f038f03305c8536d80313e52f77d27835f34d Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M writeprotect.c 1 file changed, 145 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/58481/1 diff --git a/writeprotect.c b/writeprotect.c index 1ca9439..884e4d6 100644 --- a/writeprotect.c +++ b/writeprotect.c @@ -154,6 +154,109 @@ } void *suppress_unused_warning_for_write_wp_chip_state = write_wp_chip_state; +struct wp_range_wpst_pair { + struct wp_range range; + struct wp_chip_state wpst; +}; + +static int range_sort_compare_func(const void *aa, const void *bb) +{ + const struct wp_range_wpst_pair + *a = (const struct wp_range_wpst_pair *)aa, + *b = (const struct wp_range_wpst_pair *)bb; + + int ord = 0; + + /* List shorter ranges first. */ + if (ord == 0) ord = a->range.len - b->range.len; + + /* For equal length ranges, list the one with a lower start address + * first. */ + if (ord == 0) ord = a->range.start - b->range.start; + + /* Ranges a and b are identical, order them by the status/config + * register bits that are used to select them. This ensures consistent + * ordering when multiple status register settings can select the same + * range. */ + if (ord == 0) ord = a->wpst.cmp - b->wpst.cmp; + if (ord == 0) ord = a->wpst.sec - b->wpst.sec; + if (ord == 0) ord = a->wpst.tb - b->wpst.tb; + if (ord == 0) ord = a->wpst.bp - b->wpst.bp; + + return ord; +} + +static bool can_write_bit(const struct reg_bit_info bit) +{ + return bit.reg != INVALID_REG && bit.writability == RW; +} + +static int get_available_ranges( + struct flashctx *flash, + struct wp_range_wpst_pair **ranges, + size_t *range_count) +{ + const struct reg_bit_map *bits = &flash->chip->reg_bits; + struct wp_chip_state wpst; + + /* Read chip the chip's current configuration. RW bits in the wpst + * structure will be overwritten while enumerating ranges, but RO/OTP + * bits will be preserved so that ranges are only enumerated if they + * can actually be selected on the chip. */ + if (read_wp_chip_state(flash, &wpst)) + return 1; + + /* Create a list of RW bits that affect the chip's protection range. */ + uint8_t *range_bits[20]; + size_t bit_count = 0; + for (size_t i = 0; can_write_bit(bits->bp[i]); i++) { + range_bits[bit_count++] = &wpst.bp[i]; + } + if (can_write_bit(bits->tb)) range_bits[bit_count++] = &wpst.tb; + if (can_write_bit(bits->sec)) range_bits[bit_count++] = &wpst.sec; + if (can_write_bit(bits->cmp)) range_bits[bit_count++] = &wpst.cmp; + + /* Allocate output array */ + *range_count = (1 << bit_count); + *ranges = calloc(*range_count, sizeof(**ranges)); + + /* Enumerate all values the range bits can take and find the range + * associated with each one. */ + for(uint32_t range_index = 0; range_index < *range_count; range_index++) { + /* Extract bits from the range index and assign them to bits in + * the wpst structure. */ + for (size_t i = 0; i < bit_count; i++) { + *range_bits[i] = (range_index >> i) & 1; + } + + /* Get range using chip-specific decoding function */ + (*ranges)[range_index].wpst = wpst; + (*ranges)[range_index].range.chip_len = flash->chip->total_size * 1024; + flash->chip->decode_range(&wpst, &(*ranges)[range_index].range); + } + + /* Sort ranges */ + qsort(*ranges, *range_count, sizeof(**ranges), range_sort_compare_func); + + /* Remove duplicates */ + size_t last = 0; + for(size_t i = 0; i < *range_count; i++) { + struct wp_range *range = &(*ranges)[i].range; + struct wp_range *last_range = &(*ranges)[last].range; + + bool duplicate = + range->start == last_range->start && + range->len == last_range->len; + + if (!duplicate) { + (*ranges)[++last] = (*ranges)[i]; + } + } + *range_count = last + 1; + + return 0; +} + bool wp_supported(struct flashctx *flash) { return flash->chip->decode_range != NULL; @@ -189,10 +292,50 @@ return 1; } +static void print_range(struct wp_range *range) +{ + /* Print start address and length */ + msg_ginfo("start=0x%08x length=0x%08x ", range->start, range->len); + + /* Print easily readable description like 'none' or 'lower 1/8' */ + if (range->len == 0) { + msg_ginfo("(none)"); + } + else if (range->len == range->chip_len) { + msg_ginfo("(all)"); + } + else { + uint32_t chip_len = range->chip_len; + uint32_t range_len = range->len; + + /* Remove common factors of 2 to simplify range length + * fraction. */ + while ((chip_len % 2) == 0 && (range_len % 2) == 0) { + chip_len /= 2; + range_len /= 2; + } + + const char *location = (range->start == 0) ? "lower" : "upper"; + msg_ginfo("(%s %d/%d)", location, range_len, chip_len); + } +} + int wp_list_ranges(struct flashctx *flash) { - /* TODO */ - return 1; + struct wp_range_wpst_pair *ranges; + size_t range_count = 0; + + if (get_available_ranges(flash, &ranges, &range_count)) + return 1; + + for (size_t i = 0; i < range_count; i++) { + print_range(&ranges[i].range); + msg_ginfo("\n"); + } + + free(ranges); + + return 0; } int wp_print_status(struct flashctx *flash) -- To view, visit https://review.coreboot.org/c/flashrom/+/58481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id51f038f03305c8536d80313e52f77d27835f34d Gerrit-Change-Number: 58481 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] writeprotect: add range decoding function
by Nikolai Artemiev (Code Review) 20 Oct '21

20 Oct '21

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/58480 ) Change subject: [RFC] writeprotect: add range decoding function ...................................................................... [RFC] writeprotect: add range decoding function Allow chips to specify functions that map status register bits to protection ranges. These are used to enumerate available ranges, and determine the protection state of chips. The patch also adds a range decoding function for the example chips. Many other chips can also be handled by it, though others will require different functions (e.g. MX25L6406). Another approach that has been tried in cros flashrom is maintaining tables of range data, but it quickly becomes error prone and hard to validate. Using a function to interpret the ranges allows compact encoding with most chips and is flexible enough to allow chips with less predictable ranges to be handled as well. BUG=b:195381327,b:153800563 TEST=dumped range tables, checked against datasheets BRANCH=none Change-Id: Id163ed80938a946a502ed116e48e8236e36eb203 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M Makefile M chipdrivers.h M flash.h M flashchips.c M meson.build M writeprotect.c A writeprotect_ranges.c 7 files changed, 118 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/80/58480/1 diff --git a/Makefile b/Makefile index bc0047f..df83586 100644 --- a/Makefile +++ b/Makefile @@ -283,7 +283,8 @@ CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \ sst28sf040.o 82802ab.o \ sst49lfxxxc.o sst_fwhub.o edi.o flashchips.o spi.o spi25.o spi25_statusreg.o \ - spi95.o opaque.o sfdp.o en29lv640b.o at45db.o writeprotect.o s25f.o + spi95.o opaque.o sfdp.o en29lv640b.o at45db.o s25f.o \ + writeprotect.o writeprotect_ranges.o ############################################################################### # Library code. diff --git a/chipdrivers.h b/chipdrivers.h index ea8d480..9ae30d9 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -216,4 +216,7 @@ int probe_spi_st95(struct flashctx *flash); int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +/* writeprotect_ranges.c */ +void decode_range_w25(const struct wp_chip_state *wpst, struct wp_range *range); + #endif /* !__CHIPDRIVERS_H__ */ diff --git a/flash.h b/flash.h index 8b3899c..1f0031a 100644 --- a/flash.h +++ b/flash.h @@ -199,6 +199,11 @@ } writability; }; +struct wp_chip_state; +struct wp_range; + +typedef void (*range_decode_fn_t)(const struct wp_chip_state *wpst, struct wp_range *range); + #define MAX_SRP_BITS 2 #define MAX_BP_BITS 4 @@ -292,6 +297,8 @@ struct reg_bit_info sec; struct reg_bit_info cmp; } reg_bits; + + range_decode_fn_t decode_range; }; typedef int (*chip_restore_fn_cb_t)(struct flashctx *flash, uint8_t status); diff --git a/flashchips.c b/flashchips.c index 65c2dcc..b49df7a 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6354,6 +6354,7 @@ .sec = {STATUS1, 6, RW}, .cmp = {STATUS2, 6, RW}, }, + .decode_range = decode_range_w25, }, { @@ -6800,6 +6801,7 @@ .sec = {STATUS1, 6, RW}, .cmp = {STATUS2, 6, RW}, }, + .decode_range = decode_range_w25, }, { @@ -6921,6 +6923,7 @@ .sec = {STATUS1, 6, RW}, .cmp = {STATUS2, 6, RW}, }, + .decode_range = decode_range_w25 }, { .vendor = "GigaDevice", @@ -8645,6 +8648,8 @@ .srp = {{STATUS1, 7, RW}}, .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}}, }, + .decode_range = decode_range_w25, + }, { @@ -18299,6 +18304,7 @@ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, .tb = {STATUS1, 5, RW}, }, + .decode_range = decode_range_w25, .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, diff --git a/meson.build b/meson.build index 1a36df8..98470c9 100644 --- a/meson.build +++ b/meson.build @@ -372,6 +372,7 @@ srcs += 'w29ee011.c' srcs += 'w39.c' srcs += 'writeprotect.c' +srcs += 'writeprotect_ranges.c' mapfile = 'libflashrom.map' vflag = '-Wl,--version-script,@0@/@1@'.format(meson.current_source_dir(), mapfile) diff --git a/writeprotect.c b/writeprotect.c index fa347f8..1ca9439 100644 --- a/writeprotect.c +++ b/writeprotect.c @@ -150,21 +150,25 @@ return 1; } - return 0; } void *suppress_unused_warning_for_write_wp_chip_state = write_wp_chip_state; bool wp_supported(struct flashctx *flash) { - /* TODO */ - return false; + return flash->chip->decode_range != NULL; } int wp_get_range(struct flashctx *flash, struct wp_range *range) { - /* TODO */ - return 1; + struct wp_chip_state wpst; + if (read_wp_chip_state(flash, &wpst)) + return 1; + + range->chip_len = flash->chip->total_size * 1024; + flash->chip->decode_range(&wpst, range); + + return 0; } int wp_set_range(struct flashctx *flash, const struct wp_range range) diff --git a/writeprotect_ranges.c b/writeprotect_ranges.c new file mode 100644 index 0000000..ea34f7b --- /dev/null +++ b/writeprotect_ranges.c @@ -0,0 +1,90 @@ +/* + * This file is part of the flashrom project. + * + * Copyright 2021 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "flash.h" +#include "chipdrivers.h" +#include "writeprotect.h" + +/* Protection range calculation that is applicable to many chips. TODO: Rename + * the function when the extent of it's compatibility with various chips is + * more fully known. */ +void decode_range_w25(const struct wp_chip_state *wpst, struct wp_range *range) +{ + /* Interpret BP bits as an integer */ + uint32_t bp = 0; + uint32_t bp_max = 0; + for(size_t i = 0; i < wpst->bp_bit_count; i++) { + bp |= wpst->bp[i] << i; + bp_max |= 1 << i; + } + + if (wpst->bp == 0) { + /* Special case: all BP bits are 0 => no write protection */ + range->len = 0; + } + else if (bp == bp_max) { + /* Special case: all BP bits are 1 => full write protection */ + range->len = range->chip_len; + } + else { + /* Usual case: the BP bits encode a coefficient in the form + * `coeff = 2 ** (bp - 1)`. + * + * The range's length is given by multiplying the coefficient + * by a base unit, usually a 4K sector or a 64K block. */ + + uint32_t coeff = 1 << (bp - 1); + uint32_t max_coeff = 1 << (bp_max - 2); + + uint32_t sector_len = 4 * 1024; + uint32_t default_block_len = 64 * 1024; + + if (wpst->sec_bit_present && wpst->sec == 1) { + /* SEC=1, protect 4K sectors. Flash chips clamp the + * protection length at 32K, probably to avoid overlap + * with the SEC=0 case. + */ + range->len = min(sector_len * coeff, default_block_len / 2); + } else { + /* SEC=0 or is not present, protect blocks. + * + * With very large chips, the 'block' size can be + * larger than 64K. This occurs when a larger block + * size is needed so that half the chip can be + * protected by the maximum possible coefficient. + */ + uint32_t min_block_len = range->chip_len / 2 / max_coeff; + uint32_t block_len = max(min_block_len, default_block_len); + + range->len = min(block_len * coeff, range->chip_len); + } + } + + /* Apply TB bit */ + bool protect_top = wpst->tb_bit_present ? (wpst->tb == 0) : 1; + + /* Apply CMP bit */ + if (wpst->cmp_bit_present && wpst->cmp == 1) { + range->len = range->chip_len - range->len; + protect_top = !protect_top; + } + + /* Calculate start address, ensuring that empty ranges have start + * address of 0. */ + if (protect_top && range->len > 0) + range->start = range->chip_len - range->len; + else + range->start = 0; +} -- To view, visit https://review.coreboot.org/c/flashrom/+/58480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id163ed80938a946a502ed116e48e8236e36eb203 Gerrit-Change-Number: 58480 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] writeprotect: add functions to write and print chip wp state
by Nikolai Artemiev (Code Review) 20 Oct '21

20 Oct '21

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/58479 ) Change subject: [RFC] writeprotect: add functions to write and print chip wp state ...................................................................... [RFC] writeprotect: add functions to write and print chip wp state BUG=b:195381327,b:153800563 TEST=writeprotect commands BRANCH=none Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M writeprotect.c 1 file changed, 84 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/58479/1 diff --git a/writeprotect.c b/writeprotect.c index 24239db..fa347f8 100644 --- a/writeprotect.c +++ b/writeprotect.c @@ -24,6 +24,21 @@ #include "writeprotect.h" +static void print_wp_chip_state(struct wp_chip_state *wpst) +{ + for (int i = wpst->srp_bit_count - 1; i >= 0; i--) { + msg_ginfo("SRP%d=%u ", i, wpst->srp[i]); + } + + if (wpst->cmp_bit_present) msg_ginfo("CMP=%u ", wpst->cmp); + if (wpst->sec_bit_present) msg_ginfo("SEC=%u ", wpst->sec); + if (wpst->tb_bit_present) msg_ginfo("TB=%u ", wpst->tb); + + for (int i = wpst->bp_bit_count - 1; i >= 0; i--) { + msg_ginfo("BP%d=%u ", i, wpst->bp[i]); + } +} + static int read_reg_bit( const struct flashctx *flash, const struct reg_bit_info bit, @@ -71,6 +86,75 @@ } void *suppress_unused_warning_for_read_wp_chip_state = read_wp_chip_state; +static void set_reg_bit( + uint8_t *reg_values, uint8_t *write_masks, + struct reg_bit_info bit, uint8_t value) +{ + if (bit.reg != INVALID_REG) { + reg_values[bit.reg] |= value << bit.bit_index; + write_masks[bit.reg] |= 1 << bit.bit_index; + } +} + +static int write_wp_chip_state(struct flashctx *flash, struct wp_chip_state *wpst) +{ + const struct reg_bit_map *bits = &flash->chip->reg_bits; + + /* Convert wp_chip_state to register values / write masks */ + uint8_t reg_values[MAX_REGISTERS] = {0}; + uint8_t write_masks[MAX_REGISTERS] = {0}; + + for (size_t i = 0; i < wpst->srp_bit_count; i++) { + set_reg_bit(reg_values, write_masks, bits->srp[i], wpst->srp[i]); + } + for (size_t i = 0; i < wpst->bp_bit_count; i++) { + set_reg_bit(reg_values, write_masks, bits->bp[i], wpst->bp[i]); + } + set_reg_bit(reg_values, write_masks, bits->tb, wpst->tb); + set_reg_bit(reg_values, write_masks, bits->sec, wpst->sec); + set_reg_bit(reg_values, write_masks, bits->cmp, wpst->cmp); + + /* Write each register */ + for (enum flash_reg reg = INVALID_REG; reg < MAX_REGISTERS; reg++) { + if (!write_masks[reg]) + continue; + + uint8_t value = 0; + int ret = spi_read_register(flash, reg, &value); + + value = (value & ~write_masks[reg]) | + (reg_values[reg] & write_masks[reg]); + + if (!ret) + spi_write_register(flash, reg, value); + + if (ret) { + msg_gerr("Writing wp configuration to chip failed!\n"); + return 1; + } + } + + /* Verify */ + struct wp_chip_state wpst_readback; + if (read_wp_chip_state(flash, &wpst_readback)) { + return 1; + } + + if (memcmp(wpst, &wpst_readback, sizeof(wpst_readback))) { + msg_gerr("Writing wp configuration to chip failed during " + "verification:\nExpected: "); + print_wp_chip_state(wpst); + msg_gerr("\nActual: "); + print_wp_chip_state(&wpst_readback); + msg_gerr("\n"); + + return 1; + } + + return 0; +} +void *suppress_unused_warning_for_write_wp_chip_state = write_wp_chip_state; + bool wp_supported(struct flashctx *flash) { /* TODO */ -- To view, visit https://review.coreboot.org/c/flashrom/+/58479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad Gerrit-Change-Number: 58479 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] writeprotect.h: add structure to represent chip wp state
by Nikolai Artemiev (Code Review) 20 Oct '21

20 Oct '21

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/58478 ) Change subject: [RFC] writeprotect.h: add structure to represent chip wp state ...................................................................... [RFC] writeprotect.h: add structure to represent chip wp state Adds a wp_chip_state structure to capture the complete state of a chip's wp-related status bits and serve as an intermediate representation throughout writeprotect code. Also adds a function that fills out the wp_chip_state strucutre by reading the chip's registers and intrepreting them using the status register bit map. BUG=b:195381327,b:153800563 TEST=writeprotect commands BRANCH=none Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M writeprotect.c M writeprotect.h 2 files changed, 67 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/58478/1 diff --git a/writeprotect.c b/writeprotect.c index 1d907f6..24239db 100644 --- a/writeprotect.c +++ b/writeprotect.c @@ -23,6 +23,54 @@ #include "chipdrivers.h" #include "writeprotect.h" + +static int read_reg_bit( + const struct flashctx *flash, + const struct reg_bit_info bit, + uint8_t *value, + bool *present) +{ + *value = 0; + *present = bit.reg != INVALID_REG; + + if (*present) { + if (spi_read_register(flash, bit.reg, value)) + return 1; + *value = (*value >> bit.bit_index) & 1; + } + + return 0; +} + +static int read_wp_chip_state(struct flashctx *flash, struct wp_chip_state *wpst) +{ + const struct reg_bit_map *bits = &flash->chip->reg_bits; + bool tmp; + + *wpst = (struct wp_chip_state) {0}; + + int ret = 0; + ret |= read_reg_bit(flash, bits->tb, &wpst->tb, &wpst->tb_bit_present); + ret |= read_reg_bit(flash, bits->sec, &wpst->sec, &wpst->sec_bit_present); + ret |= read_reg_bit(flash, bits->cmp, &wpst->cmp, &wpst->cmp_bit_present); + + for(size_t i = 0; bits->bp[i].reg != INVALID_REG; i++) { + ret |= read_reg_bit(flash, bits->bp[i], &wpst->bp[i], &tmp); + wpst->bp_bit_count = i + 1; + } + + for(size_t i = 0; bits->srp[i].reg != INVALID_REG; i++) { + ret |= read_reg_bit(flash, bits->srp[i], &wpst->srp[i], &tmp); + wpst->srp_bit_count = i + 1; + } + + if (ret) + msg_gerr("Reading write protection configuration failed!\n"); + + return ret; +} +void *suppress_unused_warning_for_read_wp_chip_state = read_wp_chip_state; + bool wp_supported(struct flashctx *flash) { /* TODO */ diff --git a/writeprotect.h b/writeprotect.h index db7f3aa..21d1484 100644 --- a/writeprotect.h +++ b/writeprotect.h @@ -42,4 +42,23 @@ int wp_list_ranges(struct flashctx *flash); int wp_print_status(struct flashctx *flash); +/* Complete description of a chip's wp-related state */ +struct wp_chip_state { + size_t srp_bit_count; + uint8_t srp[MAX_SRP_BITS]; + + size_t bp_bit_count; + uint8_t bp[MAX_BP_BITS]; + + bool tb_bit_present; + uint8_t tb; + + bool sec_bit_present; + uint8_t sec; + + bool cmp_bit_present; + uint8_t cmp; + + /* TODO: WPS, sector registers */ +}; #endif -- To view, visit https://review.coreboot.org/c/flashrom/+/58478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809 Gerrit-Change-Number: 58478 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] flashchips: add register bit defintions
by Nikolai Artemiev (Code Review) 20 Oct '21

20 Oct '21

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/58477 ) Change subject: [RFC] flashchips: add register bit defintions ...................................................................... [RFC] flashchips: add register bit defintions This patch adds a representation for the location and properties of register bits and fills it out for a few example flashchips. The representation is centered around describing how bits can be accessed and modified, rather than the layout of registers. This is generally easier to work with in code that needs to access specific bits and typically requires specifying the locations of fewer bits overall. BUG=b:195381327,b:153800563 TEST=ran writeprotect commands that accessed status register bits BRANCH=none Change-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M flash.h M flashchips.c 2 files changed, 65 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/58477/1 diff --git a/flash.h b/flash.h index ccae05d..8b3899c 100644 --- a/flash.h +++ b/flash.h @@ -183,6 +183,25 @@ }; #define MAX_REGISTERS 4 +struct reg_bit_info { + /* Register containing the bit */ + enum flash_reg reg; + + /* Bit index within register */ + uint8_t bit_index; + + /* Writability of the bit. RW does not guarentee the bit will be + * writable, for example if status register protection is enabled. */ + enum { + RO = 0, + RW = 1, + OTP = 2 + } writability; +}; + +#define MAX_SRP_BITS 2 +#define MAX_BP_BITS 4 + struct flashchip { const char *vendor; const char *name; @@ -262,6 +281,17 @@ /* SPI specific options (TODO: Make it a union in case other bustypes get specific options.) */ uint8_t wrea_override; /**< override opcode for write extended address register */ + /* TODO: make this a pointer instead of an embedded structure to avoid + * duplication. For now though, it is better to define these values for + * each chip to avoid accidentally reusing an incompatible definition. + */ + struct reg_bit_map { + struct reg_bit_info srp[MAX_SRP_BITS + 1]; /* Extra element for terminator */ + struct reg_bit_info bp[MAX_BP_BITS + 1]; /* Extra element for terminator */ + struct reg_bit_info tb; + struct reg_bit_info sec; + struct reg_bit_info cmp; + } reg_bits; }; typedef int (*chip_restore_fn_cb_t)(struct flashctx *flash, uint8_t status); diff --git a/flashchips.c b/flashchips.c index 0d0a8e2..65c2dcc 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6346,6 +6346,14 @@ .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1695, 1950}, + .reg_bits = + { + .srp = {{STATUS1, 7, RW}, {STATUS2, 0, RW}}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + }, }, { @@ -6784,6 +6792,14 @@ .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {{STATUS1, 7, RW}, {STATUS2, 0, RW}}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + }, }, { @@ -6897,8 +6913,15 @@ .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {{STATUS1, 7, RW}, {STATUS2, 0, RW}}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + .sec = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + }, }, - { .vendor = "GigaDevice", .name = "GD25Q80(B)", @@ -8617,6 +8640,11 @@ .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {{STATUS1, 7, RW}}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}}, + }, }, { @@ -18265,6 +18293,12 @@ .block_erase = spi_block_erase_c7, } }, + .reg_bits = + { + .srp = {{STATUS1, 7, RW}}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, + }, .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, -- To view, visit https://review.coreboot.org/c/flashrom/+/58477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id08d77e6d4ca5109c0d698271146d026dbc21284 Gerrit-Change-Number: 58477 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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