October 2021 - flashrom-gerrit

Change in flashrom[master]: [RFC] writeprotect, cli_classic: create writeprotect foundation
by Nikolai Artemiev (Code Review) 25 Oct '21

25 Oct '21

Attention is currently required from: Nico Huber, Edward O'Callaghan, Nikolai Artemiev, Anastasia Klimchuk. Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/58474 to look at the new patch set (#4). Change subject: [RFC] writeprotect, cli_classic: create writeprotect foundation ...................................................................... [RFC] writeprotect, cli_classic: create writeprotect foundation This is the first of a series of commits that adds working writeprotect support to flashrom. It deletes most writeprotect code previously extracted from the cros tree as not much of it can be reused. This commit also revises the writeprotect interface to reduce duplication and make writeprotect functionality easier to expose through libflashrom. Call sites in cli_classic have been updated. The patch series initially adds support for a small set of chips as examples. These are: GD25LQ128, GD25Q32, GD25Q64, GD25Q256, MX25L2006E, and W25X40. Writeprotect commands have been tested with all chips. BUG=b:195381327,b:153800563 TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series BRANCH=none Change-Id: I67e9b31f86465e5a8f7d3def637198671ee818a8 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M cli_classic.c M flash.h M writeprotect.c M writeprotect.h 4 files changed, 80 insertions(+), 420 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/74/58474/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/58474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I67e9b31f86465e5a8f7d3def637198671ee818a8 Gerrit-Change-Number: 58474 Gerrit-PatchSet: 4 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: [RFC] writeprotect, cli_classic: create new writeprotect foundation
by Angel Pons (Code Review) 25 Oct '21

25 Oct '21

Attention is currently required from: Nico Huber, Edward O'Callaghan, Nikolai Artemiev, Anastasia Klimchuk. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58474 ) Change subject: [RFC] writeprotect, cli_classic: create new writeprotect foundation ...................................................................... Patch Set 3: (7 comments) File cli_classic.c: https://review.coreboot.org/c/flashrom/+/58474/comment/82cec5c7_98313ad8 PS3, Line 691: bool const bool https://review.coreboot.org/c/flashrom/+/58474/comment/aec7d380_20132477 PS3, Line 695: | nit: missing space before `|` For another patch: Shouldn't these be short-circuiting logical OR `||` instead? The `|` is a bit-wise OR. File writeprotect.h: https://review.coreboot.org/c/flashrom/+/58474/comment/1a1c8be6_23a423db PS3, Line 21: #define MAX_WP_RANGES 128 Why 128? https://review.coreboot.org/c/flashrom/+/58474/comment/b002f482_20525797 PS3, Line 31: uint32_t Missing header include https://review.coreboot.org/c/flashrom/+/58474/comment/0cdc4625_85f25602 PS3, Line 36: bool Missing header include https://review.coreboot.org/c/flashrom/+/58474/comment/04361dc1_7ea9eb1f PS3, Line 38: size_t Missing header include File writeprotect.c: PS3: I find it hard to evaluate an interface without seeing its implementation. I think it would be better to remove everything in one commit, then gradually (re)implement the write-protect functionality in subsequent patches. I imagine the reason to go with this approach is to minimize changes in cli_classic.c code, especially if the CLI remains the same. I understand that removing and re-adding the CLI code is cumbersome, but I don't think it's that much effort to do. I'd like to know what others think about this. -- To view, visit https://review.coreboot.org/c/flashrom/+/58474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I67e9b31f86465e5a8f7d3def637198671ee818a8 Gerrit-Change-Number: 58474 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 25 Oct 2021 10:13:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: Makefile: meson.build: remove unused CONFIG_I2C_SUPPORT
by Angel Pons (Code Review) 25 Oct '21

25 Oct '21

Attention is currently required from: Thomas Heijligen. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58495 ) Change subject: Makefile: meson.build: remove unused CONFIG_I2C_SUPPORT ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/58495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2e19335e1b8d39f44dda14edc0a496dda6bc8c9c Gerrit-Change-Number: 58495 Gerrit-PatchSet: 4 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Mon, 25 Oct 2021 09:46:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: Makefile: remove NEED_LIBUSB1 from FEATURE_CFLAGS
by Nico Huber (Code Review) 25 Oct '21

25 Oct '21

Attention is currently required from: Thomas Heijligen. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58518 ) Change subject: Makefile: remove NEED_LIBUSB1 from FEATURE_CFLAGS ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/58518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie7cb3df39daf22cb954186d38ba32812b05d92f9 Gerrit-Change-Number: 58518 Gerrit-PatchSet: 3 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Mon, 25 Oct 2021 09:31:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: Makefile: meson.build: remove unused CONFIG_I2C_SUPPORT
by Nico Huber (Code Review) 25 Oct '21

25 Oct '21

Attention is currently required from: Thomas Heijligen. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58495 ) Change subject: Makefile: meson.build: remove unused CONFIG_I2C_SUPPORT ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/58495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2e19335e1b8d39f44dda14edc0a496dda6bc8c9c Gerrit-Change-Number: 58495 Gerrit-PatchSet: 4 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Mon, 25 Oct 2021 09:30:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: Makefile, ich_descriptors_tool/Makefile: unify behavior
by Nico Huber (Code Review) 25 Oct '21

25 Oct '21

Attention is currently required from: Thomas Heijligen, Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58468 ) Change subject: Makefile, ich_descriptors_tool/Makefile: unify behavior ...................................................................... Patch Set 4: (1 comment) File Makefile: https://review.coreboot.org/c/flashrom/+/58468/comment/1363441e_2d8caa8c PS4, Line 877: # This. -- To view, visit https://review.coreboot.org/c/flashrom/+/58468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I353c3de250167994a4aea1edfef57d839e900d78 Gerrit-Change-Number: 58468 Gerrit-PatchSet: 4 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 25 Oct 2021 09:28:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: Makefile: unify the use of filter
by Nico Huber (Code Review) 25 Oct '21

25 Oct '21

Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/58451 ) Change subject: Makefile: unify the use of filter ...................................................................... Makefile: unify the use of filter Make a filter statement easier to read and fix some cosmetics. Change-Id: I6cd1e169b435cadb06423836cd9d64cdd2f51a94 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58451 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Makefile 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/Makefile b/Makefile index 18651bc..e8bf8fc 100644 --- a/Makefile +++ b/Makefile @@ -235,7 +235,7 @@ endif # Android is handled internally as separate OS, but it supports about the same drivers as Linux. -ifeq ($(filter $(TARGET_OS),Linux Android), ) +ifneq ($(TARGET_OS), $(filter $(TARGET_OS), Linux Android)) $(call mark_unsupported,CONFIG_LINUX_MTD CONFIG_LINUX_SPI) $(call mark_unsupported,CONFIG_MSTARDDC_SPI CONFIG_LSPCON_I2C_SPI CONFIG_REALTEK_MST_I2C_SPI) endif @@ -250,7 +250,7 @@ endif # Disable the internal programmer on unsupported architectures (everything but x86 and mipsel) -ifneq ($(ARCH)-little, $(filter $(ARCH),x86 mips)-$(ENDIAN)) +ifneq ($(ARCH)-little, $(filter $(ARCH), x86 mips)-$(ENDIAN)) $(call mark_unsupported,CONFIG_INTERNAL) endif @@ -272,7 +272,7 @@ # Additionally disable all drivers needing raw access (memory, PCI, port I/O) # on architectures with unknown raw access properties. # Right now those architectures are alpha hppa m68k sh s390 -ifneq ($(ARCH),$(filter $(ARCH),x86 mips ppc arm sparc arc)) +ifneq ($(ARCH), $(filter $(ARCH), x86 mips ppc arm sparc arc)) $(call mark_unsupported,CONFIG_GFXNVIDIA CONFIG_SATASII CONFIG_ATAVIA) $(call mark_unsupported,CONFIG_DRKAISER CONFIG_NICINTEL CONFIG_NICINTEL_SPI) $(call mark_unsupported,CONFIG_NICINTEL_EEPROM CONFIG_OGP_SPI CONFIG_IT8212) @@ -805,7 +805,7 @@ FEATURE_CFLAGS += -D'NEED_LIBUSB1=1' PROGRAMMER_OBJS += usbdev.o usb_device.o # FreeBSD and DragonflyBSD use a reimplementation of libusb-1.0 that is simply called libusb -ifeq ($(TARGET_OS),$(filter $(TARGET_OS),FreeBSD DragonFlyBSD)) +ifeq ($(TARGET_OS), $(filter $(TARGET_OS), FreeBSD DragonFlyBSD)) USB1LIBS += -lusb else ifeq ($(TARGET_OS),NetBSD) 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/flashrom/+/58451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6cd1e169b435cadb06423836cd9d64cdd2f51a94 Gerrit-Change-Number: 58451 Gerrit-PatchSet: 4 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in flashrom[master]: [RFC] spi25_statusreg, flashchips: add SR2 read/write support
by Nikolai Artemiev (Code Review) 25 Oct '21

25 Oct '21

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/58570 ) Change subject: [RFC] spi25_statusreg, flashchips: add SR2 read/write support ...................................................................... [RFC] spi25_statusreg, flashchips: add SR2 read/write support This patch adds support for reading and writing the second status register and enables it on a limited set of flash chips. Chip support for RDSR2/WRSR2/extended WRSR is represented using feature flags to be consistent with how other SPI capabilities are represented. BUG=b:195381327,b:153800563 TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series TEST=logged SR2 read/write values during wp commands BRANCH=none Change-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M flash.h M flashchips.c M spi.h M spi25_statusreg.c 4 files changed, 48 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/70/58570/1 diff --git a/flash.h b/flash.h index de66362..448ded8 100644 --- a/flash.h +++ b/flash.h @@ -140,6 +140,11 @@ #define FEATURE_ERASED_ZERO (1 << 17) #define FEATURE_NO_ERASE (1 << 18) +#define FEATURE_WRSR_EXT (1 << 19) +#define FEATURE_WRSR2 (1 << 20) +#define FEATURE_RDSR2 (1 << 21) + + #define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff) enum test_state { diff --git a/flashchips.c b/flashchips.c index 434c46d..81523e8 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6317,7 +6317,8 @@ .total_size = 16384, .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | + FEATURE_WRSR_EXT | FEATURE_RDSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -6706,7 +6707,8 @@ .model_id = GIGADEVICE_GD25Q256D, .total_size = 32768, .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN | + FEATURE_WRSR2 | FEATURE_RDSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -6754,7 +6756,8 @@ .total_size = 4096, .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | + FEATURE_WRSR2 | FEATURE_RDSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -6866,7 +6869,8 @@ .total_size = 8192, .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | + FEATURE_WRSR_EXT | FEATURE_RDSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, diff --git a/spi.h b/spi.h index 09da579..845b6c2 100644 --- a/spi.h +++ b/spi.h @@ -131,6 +131,11 @@ #define JEDEC_RDSR_OUTSIZE 0x01 #define JEDEC_RDSR_INSIZE 0x01 +/* Read Status Register 2 */ +#define JEDEC_RDSR2 0x35 +#define JEDEC_RDSR2_OUTSIZE 0x01 +#define JEDEC_RDSR2_INSIZE 0x01 + /* Status Register Bits */ #define SPI_SR_WIP (0x01 << 0) #define SPI_SR_WEL (0x01 << 1) @@ -146,6 +151,12 @@ #define JEDEC_WRSR 0x01 #define JEDEC_WRSR_OUTSIZE 0x02 #define JEDEC_WRSR_INSIZE 0x00 +#define JEDEC_WRSR_EXT_OUTSIZE 0x03 + +/* Write Status Register 2 */ +#define JEDEC_WRSR2 0x31 +#define JEDEC_WRSR2_OUTSIZE 0x02 +#define JEDEC_WRSR2_INSIZE 0x00 /* Enter 4-byte Address Mode */ #define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 9fb9648..7f631c0 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -91,6 +91,26 @@ write_cmd[1] = value; write_cmd_len = JEDEC_WRSR_OUTSIZE; } + else if (reg == STATUS2) { + if (feature_bits & FEATURE_WRSR_EXT) { + /* Writing SR2 with an extended WRSR command requires + * writing SR1 along with SR2, so just read SR1 and + * write it back. */ + uint8_t sr1; + if (spi_read_register(flash, STATUS1, &sr1)) + return 1; + + write_cmd[0] = JEDEC_WRSR; + write_cmd[1] = sr1; + write_cmd[2] = value; + write_cmd_len = JEDEC_WRSR_EXT_OUTSIZE; + } + else if (feature_bits & FEATURE_WRSR2) { + write_cmd[0] = JEDEC_WRSR2; + write_cmd[1] = value; + write_cmd_len = JEDEC_WRSR2_OUTSIZE; + } + } if(write_cmd_len == 0) { msg_cerr("Cannot write register: not supported by chip\n"); return 1; @@ -112,11 +132,15 @@ int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t *value) { + int feature_bits = flash->chip->feature_bits; uint8_t read_cmd; if (reg == STATUS1) { read_cmd = JEDEC_RDSR; } + else if (reg == STATUS2 && (feature_bits & FEATURE_RDSR2)) { + read_cmd = JEDEC_RDSR2; + } else { msg_cerr("Cannot read register: not supported by chip\n"); return 1; @@ -125,7 +149,6 @@ /* FIXME: No workarounds for driver/hardware bugs in generic code. */ /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */ uint8_t readarr[2]; - int ret = spi_send_command( flash, sizeof(read_cmd), sizeof(readarr), &read_cmd, readarr); -- To view, visit https://review.coreboot.org/c/flashrom/+/58570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db Gerrit-Change-Number: 58570 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: [RFC] writeprotect: implement wp_print_status() and wp_list_ranges()
by Nikolai Artemiev (Code Review) 25 Oct '21

25 Oct '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/58484 to look at the new patch set (#3). Change subject: [RFC] writeprotect: implement wp_print_status() and wp_list_ranges() ...................................................................... [RFC] writeprotect: implement wp_print_status() and wp_list_ranges() BUG=b:195381327,b:153800563 TEST=flashrom --wp-{list,status} BRANCH=none Change-Id: I82441c60c239a5b947b5a2a87b61e7bdf60bee89 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M writeprotect.c 1 file changed, 72 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/84/58484/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/58484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I82441c60c239a5b947b5a2a87b61e7bdf60bee89 Gerrit-Change-Number: 58484 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: [RFC] writeprotect: implement wp_get_mode() and wp_set_mode()
by Nikolai Artemiev (Code Review) 25 Oct '21

25 Oct '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/58483 to look at the new patch set (#3). Change subject: [RFC] writeprotect: implement wp_get_mode() and wp_set_mode() ...................................................................... [RFC] writeprotect: implement wp_get_mode() and wp_set_mode() BUG=b:195381327,b:153800563 TEST=flashrom --wp-{enable,disable,status} BRANCH=none Change-Id: I7b68e940f0e1359281806c98e1da119b4caf8405 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M writeprotect.c 1 file changed, 77 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/58483/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/58483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7b68e940f0e1359281806c98e1da119b4caf8405 Gerrit-Change-Number: 58483 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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flashrom-gerrit October 2021