August 2020 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: Add support for Comet Lake-U/400-series PCH
by Matt DeVillier (Code Review) Sept. 24, 2020

Sept. 24, 2020

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44420 ) Change subject: Add support for Comet Lake-U/400-series PCH ...................................................................... Add support for Comet Lake-U/400-series PCH Add enum CHIPSET_400_SERIES_COMET_POINT and treat it identically to CHIPSET_300_SERIES_CANNON_POINT. Add PCI ID for Comet Lake-U Premium and classify as CHIPSET_400_SERIES_COMET_POINT. Test: read/write unlocked CML-U board Change-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M chipset_enable.c M ich_descriptors.c M ichspi.c M programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 5 files changed, 32 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/20/44420/1 diff --git a/chipset_enable.c b/chipset_enable.c index d56a547..c01deb2 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -599,6 +599,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: reg_name = "BIOS_SPI_BC"; gcs = pci_read_long(dev, 0xdc); @@ -694,6 +695,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: boot_straps = boot_straps_pch8_lp; break; case CHIPSET_APOLLO_LAKE: @@ -722,6 +724,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: bbs = (gcs >> 6) & 0x1; break; @@ -963,6 +966,11 @@ return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT); } +static int enable_flash_pch400(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_400_SERIES_COMET_POINT); +} + static int enable_flash_apl(struct pci_dev *const dev, const char *const name) { return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); @@ -2004,6 +2012,7 @@ {0x8086, 0x9d56, B_S, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100}, {0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100}, {0x8086, 0x9d84, B_S, DEP, "Intel", "Cannon Lake U Premium", enable_flash_pch300}, + {0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, {0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100}, diff --git a/ich_descriptors.c b/ich_descriptors.c index 120d3fe..315e086 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -42,6 +42,7 @@ return 6; case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: return 16; case CHIPSET_100_SERIES_SUNRISE_POINT: return 10; @@ -196,6 +197,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: { uint8_t size_enc; if (idx == 0) { @@ -264,6 +266,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: return freq_str[1][value]; case CHIPSET_APOLLO_LAKE: return freq_str[2][value]; @@ -281,6 +284,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: has_flill1 = true; break; @@ -399,7 +403,8 @@ msg_pdbg2("--- Details ---\n"); if (cs == CHIPSET_100_SERIES_SUNRISE_POINT || - cs == CHIPSET_300_SERIES_CANNON_POINT) { + cs == CHIPSET_300_SERIES_CANNON_POINT || + cs == CHIPSET_400_SERIES_COMET_POINT) { const char *const master_names[] = { "BIOS", "ME", "GbE", "unknown", "EC", }; @@ -957,6 +962,7 @@ switch (guess) { case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: /* `freq_read` was repurposed, so can't check on it any more. */ return guess; case CHIPSET_100_SERIES_SUNRISE_POINT: @@ -1111,6 +1117,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; @@ -1146,6 +1153,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: mmio_le_writel(control, spibar + PCH100_REG_FDOC); return mmio_le_readl(spibar + PCH100_REG_FDOD); diff --git a/ichspi.c b/ichspi.c index 4dbe69a..4209d60 100644 --- a/ichspi.c +++ b/ichspi.c @@ -399,6 +399,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: break; default: pprint_reg(HSFS, BERASE, reg_val, ", "); @@ -409,6 +410,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", "); pprint_reg(HSFS, WRSDIS, reg_val, ", "); break; @@ -428,6 +430,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", "); pprint_reg(HSFC, WET, reg_val, ", "); break; @@ -1741,6 +1744,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: num_pr = 6; /* Includes GPR0 */ reg_pr0 = PCH100_REG_FPR0; @@ -1772,6 +1776,7 @@ num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ break; case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: num_freg = 16; break; @@ -1867,6 +1872,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: tmp = mmio_readl(spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); @@ -1941,6 +1947,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_BAYTRAIL: break; @@ -1973,6 +1980,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: break; default: @@ -2004,7 +2012,8 @@ if (ich_spi_mode == ich_auto && (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || - ich_gen == CHIPSET_300_SERIES_CANNON_POINT)) { + ich_gen == CHIPSET_300_SERIES_CANNON_POINT || + ich_gen == CHIPSET_400_SERIES_COMET_POINT)) { msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n"); ich_spi_mode = ich_hwseq; } diff --git a/programmer.h b/programmer.h index c5cab18..780fcb0 100644 --- a/programmer.h +++ b/programmer.h @@ -660,6 +660,7 @@ CHIPSET_C620_SERIES_LEWISBURG, CHIPSET_300_SERIES_CANNON_POINT, CHIPSET_APOLLO_LAKE, + CHIPSET_400_SERIES_COMET_POINT, }; /* ichspi.c */ diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 6f13749..32eea12 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -225,6 +225,9 @@ else if ((strcmp(csn, "300") == 0) || (strcmp(csn, "cannon") == 0)) cs = CHIPSET_300_SERIES_CANNON_POINT; + else if ((strcmp(csn, "400") == 0) || + (strcmp(csn, "comet") == 0)) + cs = CHIPSET_400_SERIES_COMET_POINT; else if (strcmp(csn, "apollo") == 0) cs = CHIPSET_APOLLO_LAKE; } -- To view, visit https://review.coreboot.org/c/flashrom/+/44420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b Gerrit-Change-Number: 44420 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 16

Change in flashrom[master]: allow 0x34 as ICCRIBA for CHIPSET_C620_SERIES_LEWISBURG
by Jonathan Zhang (Code Review) Sept. 10, 2020

Sept. 10, 2020

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44621 ) Change subject: allow 0x34 as ICCRIBA for CHIPSET_C620_SERIES_LEWISBURG ...................................................................... allow 0x34 as ICCRIBA for CHIPSET_C620_SERIES_LEWISBURG Intel C621A Lewisburg PCH belongs to C620 series, it has 0x34 as ICCRIBA. Fix guess_ich_chipset_from_content() accordingly. Print error status info for read_ich_descriptors_from_dump(). Change-Id: I363aaccfb90e0a127c0f0bb0072e9e85c210b669 Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> --- M ich_descriptors.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/44621/1 diff --git a/ich_descriptors.c b/ich_descriptors.c index 120d3fe..cd8e13a 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -932,7 +932,7 @@ return CHIPSET_8_SERIES_LYNX_POINT; msg_pwarn("Peculiar firmware descriptor, assuming Wildcat Point compatibility.\n"); return CHIPSET_9_SERIES_WILDCAT_POINT; - } else if (content->ICCRIBA < 0x34) { + } else if (content->ICCRIBA <= 0x34) { if (content->NM == 6) return CHIPSET_C620_SERIES_LEWISBURG; else @@ -1243,8 +1243,11 @@ struct ich_descriptors desc; enum ich_chipset cs = CHIPSET_ICH_UNKNOWN; - if (read_ich_descriptors_from_dump(dump, len, &cs, &desc)) + int ret = read_ich_descriptors_from_dump(dump, len, &cs, &desc); + if (ret) { + msg_cerr("__FUNC__, __LINE__ Failed with value %d.\n", ret); return 1; + } memset(layout, 0x00, sizeof(*layout)); -- To view, visit https://review.coreboot.org/c/flashrom/+/44621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I363aaccfb90e0a127c0f0bb0072e9e85c210b669 Gerrit-Change-Number: 44621 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

4 21

Change in flashrom[master]: support 4-byte address format for VARIOUS_SIZE dummy flash device
by Namyoon Woo (Code Review) Sept. 7, 2020

Sept. 7, 2020

Namyoon Woo has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44881 ) Change subject: support 4-byte address format for VARIOUS_SIZE dummy flash device ...................................................................... support 4-byte address format for VARIOUS_SIZE dummy flash device This patch adds a support of 4-byte address format for VARIOUS_SIZE dummy flash device, so that it can emulate an flash size larger than 16 MBytes. TEST=ran the command line below: $ flashrom -p dummy:image=${TMP_FILE},size=33554432, \ emulate=VARIABLE_SIZE -w ${IMG_32MB} -V -f $ flashrom -p dummy:image=${TMP_FILE},size=16777216, \ emulate=VARIABLE_SIZE -w ${IMG_16MB} -V -f $ flashrom -p dummy:image=${TMP_FILE},size=8388608, \ emulate=VARIABLE_SIZE -w ${IMG_8MB} -V -f Signed-off-by: Namyoon Woo <namyoon(a)google.com> Change-Id: Ia59eecfcbe798d50f8dacea98c3c508edf8ec77e --- M dummyflasher.c M flashchips.c 2 files changed, 25 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/44881/1 diff --git a/dummyflasher.c b/dummyflasher.c index 4024f2a..b5a0f1b 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -719,6 +719,13 @@ if (readcnt > 0) memcpy(readarr, flashchip_contents + offs, readcnt); break; + case JEDEC_READ_4BA: + offs = writearr[1] << 24 | writearr[2] << 16 | writearr[3] << 8 | writearr[4]; + /* Truncate to emu_chip_size. */ + offs %= emu_chip_size; + if (readcnt > 0) + memcpy(readarr, flashchip_contents + offs, readcnt); + break; case JEDEC_BYTE_PROGRAM: offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; /* Truncate to emu_chip_size. */ @@ -733,6 +740,20 @@ } memcpy(flashchip_contents + offs, writearr + 4, writecnt - 4); break; + case JEDEC_BYTE_PROGRAM_4BA: + offs = writearr[1] << 24 | writearr[2] << 16 | writearr[3] << 8 | writearr[4]; + /* Truncate to emu_chip_size. */ + offs %= emu_chip_size; + if (writecnt < 6) { + msg_perr("BYTE PROGRAM size too short!\n"); + return 1; + } + if (writecnt - 5 > emu_max_byteprogram_size) { + msg_perr("Max BYTE PROGRAM size exceeded!\n"); + return 1; + } + memcpy(flashchip_contents + offs, writearr + 5, writecnt - 5); + break; case JEDEC_AAI_WORD_PROGRAM: if (!emu_max_aai_size) break; @@ -978,8 +999,8 @@ if (eraser->block_erase == NULL) break; - eraser->eraseblocks[0].count = emu_chip_size / - eraser->eraseblocks[0].size; + eraser->eraseblocks[0].count = 1; + eraser->eraseblocks[0].size = emu_chip_size; msg_cdbg("%s: eraser.size=%d, .count=%d\n", __func__, eraser->eraseblocks[0].size, eraser->eraseblocks[0].count); diff --git a/flashchips.c b/flashchips.c index e99073b..34b7702 100644 --- a/flashchips.c +++ b/flashchips.c @@ -18765,13 +18765,14 @@ .model_id = VARIABLE_SIZE_DEVICE_ID, .total_size = 64, /* This size is set temporarily */ .page_size = 256, + .feature_bits = FEATURE_4BA, .tested = TEST_OK_PREW, .probe = probe_variable_size, .block_erasers = { { .eraseblocks = { {64 * 1024, 1} }, - .block_erase = spi_block_erase_d8, + .block_erase = spi_block_erase_c7, } }, .write = spi_chip_write_256, -- To view, visit https://review.coreboot.org/c/flashrom/+/44881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia59eecfcbe798d50f8dacea98c3c508edf8ec77e Gerrit-Change-Number: 44881 Gerrit-PatchSet: 1 Gerrit-Owner: Namyoon Woo <namyoon(a)google.com> Gerrit-MessageType: newchange

2 9

Change in flashrom[master]: Only write back emulated image if modified
by Namyoon Woo (Code Review) Sept. 7, 2020

Sept. 7, 2020

Namyoon Woo has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44907 ) Change subject: Only write back emulated image if modified ...................................................................... Only write back emulated image if modified When the image is not modified, there is no point in writing it back. In fact we may not have file permissions to do so. Signed-off-by: Namyoon Woo <namyoon(a)google.com> Change-Id: I3bf2d7edb28a9a1e5406b67a88a0ee6e07db83e3 --- M dummyflasher.c 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/44907/1 diff --git a/dummyflasher.c b/dummyflasher.c index d1b7366..ea3907e 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -50,6 +50,7 @@ static enum emu_chip emu_chip = EMULATE_NONE; static char *emu_persistent_image = NULL; static unsigned int emu_chip_size = 0; +static int emu_modified; /* is the image modified since reading it? */ #if EMULATE_SPI_CHIP static unsigned int emu_max_byteprogram_size = 0; static unsigned int emu_max_aai_size = 0; @@ -137,7 +138,7 @@ msg_pspew("%s\n", __func__); #if EMULATE_CHIP if (emu_chip != EMULATE_NONE) { - if (emu_persistent_image) { + if (emu_persistent_image && emu_modified) { msg_pdbg("Writing %s\n", emu_persistent_image); write_buf_to_file(flashchip_contents, emu_chip_size, emu_persistent_image); free(emu_persistent_image); @@ -727,6 +728,7 @@ return 1; } memcpy(flashchip_contents + offs, writearr + 4, writecnt - 4); + emu_modified = 1; break; case JEDEC_AAI_WORD_PROGRAM: if (!emu_max_aai_size) @@ -763,6 +765,7 @@ memcpy(flashchip_contents + aai_offs, writearr + 1, 2); aai_offs += 2; } + emu_modified = 1; break; case JEDEC_WRDI: if (emu_max_aai_size) @@ -784,6 +787,7 @@ msg_pdbg("Unaligned SECTOR ERASE 0x20: 0x%x\n", offs); offs &= ~(emu_jedec_se_size - 1); memset(flashchip_contents + offs, 0xff, emu_jedec_se_size); + emu_modified = 1; break; case JEDEC_BE_52: if (!emu_jedec_be_52_size) @@ -801,6 +805,7 @@ msg_pdbg("Unaligned BLOCK ERASE 0x52: 0x%x\n", offs); offs &= ~(emu_jedec_be_52_size - 1); memset(flashchip_contents + offs, 0xff, emu_jedec_be_52_size); + emu_modified = 1; break; case JEDEC_BE_D8: if (!emu_jedec_be_d8_size) @@ -818,6 +823,7 @@ msg_pdbg("Unaligned BLOCK ERASE 0xd8: 0x%x\n", offs); offs &= ~(emu_jedec_be_d8_size - 1); memset(flashchip_contents + offs, 0xff, emu_jedec_be_d8_size); + emu_modified = 1; break; case JEDEC_CE_60: if (!emu_jedec_ce_60_size) @@ -833,6 +839,7 @@ /* JEDEC_CE_60_OUTSIZE is 1 (no address) -> no offset. */ /* emu_jedec_ce_60_size is emu_chip_size. */ memset(flashchip_contents, 0xff, emu_jedec_ce_60_size); + emu_modified = 1; break; case JEDEC_CE_C7: if (!emu_jedec_ce_c7_size) @@ -848,6 +855,7 @@ /* JEDEC_CE_C7_OUTSIZE is 1 (no address) -> no offset. */ /* emu_jedec_ce_c7_size is emu_chip_size. */ memset(flashchip_contents, 0xff, emu_jedec_ce_c7_size); + emu_modified = 1; break; case JEDEC_SFDP: if (emu_chip != EMULATE_MACRONIX_MX25L6436) -- To view, visit https://review.coreboot.org/c/flashrom/+/44907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3bf2d7edb28a9a1e5406b67a88a0ee6e07db83e3 Gerrit-Change-Number: 44907 Gerrit-PatchSet: 1 Gerrit-Owner: Namyoon Woo <namyoon(a)google.com> Gerrit-MessageType: newchange

2 7

Change in flashrom[master]: chipset_enable.c: Add PCI ID for Comet Lake.
by Joshua Wise (Code Review) Aug. 29, 2020

Aug. 29, 2020

Joshua Wise has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44921 ) Change subject: chipset_enable.c: Add PCI ID for Comet Lake. ...................................................................... chipset_enable.c: Add PCI ID for Comet Lake. Change-Id: Ic6eec4a650155810dc8430bec5b4f5d3091cf37f --- M chipset_enable.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/44921/1 diff --git a/chipset_enable.c b/chipset_enable.c index 5fc222b..dbb4f7c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2068,6 +2068,7 @@ {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, {0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300}, {0x8086, 0x3482, B_S, DEP, "Intel", "Ice Lake U Premium", enable_flash_pch300}, + {0x8086, 0x02a4, B_S, NT, "Intel", "Comet Lake", enable_flash_pch300}, #endif {0}, }; -- To view, visit https://review.coreboot.org/c/flashrom/+/44921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic6eec4a650155810dc8430bec5b4f5d3091cf37f Gerrit-Change-Number: 44921 Gerrit-PatchSet: 1 Gerrit-Owner: Joshua Wise <joshua(a)joshuawise.com> Gerrit-MessageType: newchange

3 5

Change in flashrom[master]: chipset_enable: Mark Intel Q77 as DEP
by Jacob Garber (Code Review) Aug. 29, 2020

Aug. 29, 2020

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44910 ) Change subject: chipset_enable: Mark Intel Q77 as DEP ...................................................................... chipset_enable: Mark Intel Q77 as DEP Tested reading and writing internal flash on Dell Optiplex 9010 SFF. Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I4717959be1b79aa986f1276589d01ce7475bda8f --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/44910/1 diff --git a/chipset_enable.c b/chipset_enable.c index 4772a1c..0810488 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1830,7 +1830,7 @@ {0x8086, 0x1d41, B_FS, DEP, "Intel", "C60x/X79", enable_flash_pch6}, {0x8086, 0x1e44, B_FS, DEP, "Intel", "Z77", enable_flash_pch7}, {0x8086, 0x1e46, B_FS, NT, "Intel", "Z75", enable_flash_pch7}, - {0x8086, 0x1e47, B_FS, NT, "Intel", "Q77", enable_flash_pch7}, + {0x8086, 0x1e47, B_FS, DEP, "Intel", "Q77", enable_flash_pch7}, {0x8086, 0x1e48, B_FS, DEP, "Intel", "Q75", enable_flash_pch7}, {0x8086, 0x1e49, B_FS, DEP, "Intel", "B75", enable_flash_pch7}, {0x8086, 0x1e4a, B_FS, DEP, "Intel", "H77", enable_flash_pch7}, -- To view, visit https://review.coreboot.org/c/flashrom/+/44910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I4717959be1b79aa986f1276589d01ce7475bda8f Gerrit-Change-Number: 44910 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in flashrom[master]: add PCI IDs for additional c620 serials PCH chips
by Jonathan Zhang (Code Review) Aug. 27, 2020

Aug. 27, 2020

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44620 ) Change subject: add PCI IDs for additional c620 serials PCH chips ...................................................................... add PCI IDs for additional c620 serials PCH chips Add PCI IDs for C621A, C627A and C629A. Change-Id: I636becd9f08bdf604c6af81ce396049655353b04 Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> --- M chipset_enable.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/20/44620/1 diff --git a/chipset_enable.c b/chipset_enable.c index d56a547..a9e1e0b 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2034,6 +2034,9 @@ {0x8086, 0xa1c8, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c9, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1ca, B_S, NT, "Intel", "C629 Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1cb, B_S, NT, "Intel", "C621A Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1cc, B_S, NT, "Intel", "C627A Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa1cd, B_S, NT, "Intel", "C629A Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa240, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa241, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa242, B_S, NT, "Intel", "C624 Series Chipset Supersku", enable_flash_c620}, -- To view, visit https://review.coreboot.org/c/flashrom/+/44620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I636becd9f08bdf604c6af81ce396049655353b04 Gerrit-Change-Number: 44620 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: spi: Allow cached ID bytes to be cleared
by Edward O'Callaghan (Code Review) Aug. 26, 2020

Aug. 26, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41399 ) Change subject: spi: Allow cached ID bytes to be cleared ...................................................................... spi: Allow cached ID bytes to be cleared This does two things: 1. Removes the static variables from various ID functions and moves them to a single struct. 2. Adds a function to clear the struct. The idea of the original caching mechanism introduced years ago was simply to speed up probe_flash() by not issuing the same read ID commands dozens or hundreds of times for a single chip. That implementation assumed that we would only call probe_flash() once. However, there are cases when we want to call probe_flash() multiple times, for example, if using an external programmer and using different voltages (for probing the chip). This patch is extremely similar to the original works of: `commit 57b7524b1448189d3630d6c4735e60dbbdf14d51`. Author: David Hendricks <dhendrix(a)chromium.org> && `commit 7f7c711ee1a41649607f81f1533e5135fc1361fc`. Author: David Hendricks <dhendrix(a)chromium.org> BUG=b:15656443 BRANCH=none TEST=none Change-Id: I879cb08dbe66db9ab0c3b8a7f93b04fe1c5980f4 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M spi.h M spi25.c 2 files changed, 50 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/99/41399/1 diff --git a/spi.h b/spi.h index 3f45038..c1ca46a 100644 --- a/spi.h +++ b/spi.h @@ -192,4 +192,6 @@ #define SPI_FLASHROM_BUG -5 #define SPI_PROGRAMMER_ERROR -6 +void clear_spi_id_cache(void); + #endif /* !__SPI_H__ */ diff --git a/spi25.c b/spi25.c index fb91903..b4fbe6d 100644 --- a/spi25.c +++ b/spi25.c @@ -27,6 +27,26 @@ #include "programmer.h" #include "spi.h" +enum id_type { + RDID, + RDID4, + REMS, + RES2, + RES3, + NUM_ID_TYPES, +}; + +static struct { + int is_cached; + unsigned char bytes[4]; /* enough to hold largest ID type */ +} id_cache[NUM_ID_TYPES]; + +void clear_spi_id_cache(void) +{ + memset(id_cache, 0, sizeof(id_cache)); + return; +} + static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes) { static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; @@ -138,18 +158,20 @@ static int probe_spi_rdid_generic(struct flashctx *flash, int bytes) { const struct flashchip *chip = flash->chip; - unsigned char readarr[4]; uint32_t id1; uint32_t id2; + enum id_type idty = bytes == 3 ? RDID : RDID4; - const int ret = spi_rdid(flash, readarr, bytes); - if (ret == SPI_INVALID_LENGTH) - msg_cinfo("%d byte RDID not supported on this SPI controller\n", bytes); - if (ret) - return 0; + if (!id_cache[idty].is_cached) { + const int ret = spi_rdid(flash, id_cache[idty].bytes, bytes); + if (ret == SPI_INVALID_LENGTH) + msg_cinfo("%d byte RDID not supported on this SPI controller\n", bytes); + if (ret) + return 0; + id_cache[idty].is_cached = 1; + } - rdid_get_ids(readarr, bytes, &id1, &id2); - + rdid_get_ids(id_cache[idty].bytes, bytes, &id1, &id2); return compare_id(chip, id1, id2); } @@ -166,16 +188,16 @@ int probe_spi_rems(struct flashctx *flash) { const struct flashchip *chip = flash->chip; - unsigned char readarr[JEDEC_REMS_INSIZE]; uint32_t id1, id2; - if (spi_rems(flash, readarr)) { - return 0; + if (!id_cache[REMS].is_cached) { + if (spi_rems(flash, id_cache[REMS].bytes)) + return 0; + id_cache[REMS].is_cached = 1; } - id1 = readarr[0]; - id2 = readarr[1]; - + id1 = id_cache[REMS].bytes[0]; + id2 = id_cache[REMS].bytes[1]; return compare_id(chip, id1, id2); } @@ -222,16 +244,16 @@ int probe_spi_res2(struct flashctx *flash) { - unsigned char readarr[2]; uint32_t id1, id2; - if (spi_res(flash, readarr, 2)) { - return 0; + if (!id_cache[RES2].is_cached) { + if (spi_res(flash, id_cache[RES2].bytes, 2)) + return 0; + id_cache[RES2].is_cached = 1; } - id1 = readarr[0]; - id2 = readarr[1]; - + id1 = id_cache[RES2].bytes[0]; + id2 = id_cache[RES2].bytes[1]; msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2); if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id) @@ -242,16 +264,16 @@ int probe_spi_res3(struct flashctx *flash) { - unsigned char readarr[3]; uint32_t id1, id2; - if (spi_res(flash, readarr, 3)) { - return 0; + if (!id_cache[RES3].is_cached) { + if (spi_res(flash, id_cache[RES3].bytes, 3)) + return 0; + id_cache[RES3].is_cached = 1; } - id1 = (readarr[0] << 8) | readarr[1]; - id2 = readarr[2]; - + id1 = (id_cache[RES3].bytes[0] << 8) | id_cache[RES3].bytes[1]; + id2 = id_cache[RES3].bytes[3]; msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2); if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id) -- To view, visit https://review.coreboot.org/c/flashrom/+/41399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I879cb08dbe66db9ab0c3b8a7f93b04fe1c5980f4 Gerrit-Change-Number: 41399 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: spi25.c: Factor out rdid_get_ids() and compare_id()
by Edward O'Callaghan (Code Review) Aug. 26, 2020

Aug. 26, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41398 ) Change subject: spi25.c: Factor out rdid_get_ids() and compare_id() ...................................................................... spi25.c: Factor out rdid_get_ids() and compare_id() This is in preparation for implementing a cache for the probe results of RDID and REMS (3&4-byte variant) commands. The intention is to make probing of SPI rom's slightly faster, a few 10's of ms dependant upon the spi master used. BUG=b:15656443 BRANCH=none TEST=builds Change-Id: I1556e97a7c70425069e3d1dc0d5daf0aeec4e7bf Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M spi25.c 1 file changed, 30 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/98/41398/1 diff --git a/spi25.c b/spi25.c index 0a939e7..fb91903 100644 --- a/spi25.c +++ b/spi25.c @@ -93,19 +93,9 @@ return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); } -static int probe_spi_rdid_generic(struct flashctx *flash, int bytes) +static void rdid_get_ids(unsigned char *readarr, int bytes, + uint32_t *id1, uint32_t *id2) { - const struct flashchip *chip = flash->chip; - unsigned char readarr[4]; - uint32_t id1; - uint32_t id2; - - const int ret = spi_rdid(flash, readarr, bytes); - if (ret == SPI_INVALID_LENGTH) - msg_cinfo("%d byte RDID not supported on this SPI controller\n", bytes); - if (ret) - return 0; - if (!oddparity(readarr[0])) msg_cdbg("RDID byte 0 parity violation. "); @@ -115,17 +105,20 @@ if (readarr[0] == 0x7f) { if (!oddparity(readarr[1])) msg_cdbg("RDID byte 1 parity violation. "); - id1 = (readarr[0] << 8) | readarr[1]; - id2 = readarr[2]; + *id1 = (readarr[0] << 8) | readarr[1]; + *id2 = readarr[2]; if (bytes > 3) { - id2 <<= 8; - id2 |= readarr[3]; + *id2 <<= 8; + *id2 |= readarr[3]; } } else { - id1 = readarr[0]; - id2 = (readarr[1] << 8) | readarr[2]; + *id1 = readarr[0]; + *id2 = (readarr[1] << 8) | readarr[2]; } +} +static int compare_id(const struct flashchip *chip, uint32_t id1, uint32_t id2) +{ msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); if (id1 == chip->manufacture_id && id2 == chip->model_id) @@ -142,6 +135,24 @@ return 0; } +static int probe_spi_rdid_generic(struct flashctx *flash, int bytes) +{ + const struct flashchip *chip = flash->chip; + unsigned char readarr[4]; + uint32_t id1; + uint32_t id2; + + const int ret = spi_rdid(flash, readarr, bytes); + if (ret == SPI_INVALID_LENGTH) + msg_cinfo("%d byte RDID not supported on this SPI controller\n", bytes); + if (ret) + return 0; + + rdid_get_ids(readarr, bytes, &id1, &id2); + + return compare_id(chip, id1, id2); +} + int probe_spi_rdid(struct flashctx *flash) { return probe_spi_rdid_generic(flash, 3); @@ -165,20 +176,7 @@ id1 = readarr[0]; id2 = readarr[1]; - msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2); - - if (id1 == chip->manufacture_id && id2 == chip->model_id) - return 1; - - /* Test if this is a pure vendor match. */ - if (id1 == chip->manufacture_id && GENERIC_DEVICE_ID == chip->model_id) - return 1; - - /* Test if there is any vendor ID. */ - if (GENERIC_MANUF_ID == chip->manufacture_id && id1 != 0xff && id1 != 0x00) - return 1; - - return 0; + return compare_id(chip, id1, id2); } int probe_spi_res1(struct flashctx *flash) -- To view, visit https://review.coreboot.org/c/flashrom/+/41398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1556e97a7c70425069e3d1dc0d5daf0aeec4e7bf Gerrit-Change-Number: 41398 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: chipset_enable.c: Add support for Intel C620 Series Chipset SPI Contr...
by Luka Kovacic (Code Review) Aug. 25, 2020

Aug. 25, 2020

Luka Kovacic has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44162 ) Change subject: chipset_enable.c: Add support for Intel C620 Series Chipset SPI Controller ...................................................................... chipset_enable.c: Add support for Intel C620 Series Chipset SPI Controller Support for the Intel C620 Series Chipset SPI Controller (rev 04) is added to enable SPI flash access on the following platform: - Intel Xeon D-2187NT Support for this controller was shortly tested on the platform above. The flash is recognized, some regions of the flash are locked. Signed-off-by: Luka Kovacic <luka.kovacic(a)sartura.hr> Tested-by: Jakov Petrina <jakov.petrina(a)sartura.hr> Cc: Luka Perkov <luka.perkov(a)sartura.hr> Change-Id: If39d9bb1acd4029f802a44a2940dd23f66ba09b1 --- M chipset_enable.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/44162/1 diff --git a/chipset_enable.c b/chipset_enable.c index d56a547..4772a1c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2023,6 +2023,7 @@ {0x8086, 0xa153, B_S, NT, "Intel", "QM175", enable_flash_pch100}, {0x8086, 0xa154, B_S, NT, "Intel", "CM238", enable_flash_pch100}, {0x8086, 0xa155, B_S, NT, "Intel", "QMU185", enable_flash_pch100}, + {0x8086, 0xa1a4, B_S, DEP, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c0, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c1, B_S, NT, "Intel", "C621 Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1c2, B_S, NT, "Intel", "C622 Series Chipset (QS/PRQ)", enable_flash_c620}, -- To view, visit https://review.coreboot.org/c/flashrom/+/44162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If39d9bb1acd4029f802a44a2940dd23f66ba09b1 Gerrit-Change-Number: 44162 Gerrit-PatchSet: 1 Gerrit-Owner: Luka Kovacic <luka.kovacic(a)sartura.hr> Gerrit-MessageType: newchange

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