October 2020 - flashrom-gerrit

Change in flashrom[master]: internal.c: De-maze the pre-processor wraps a little
by Edward O'Callaghan (Code Review) 28 Oct '20

28 Oct '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46815 ) Change subject: internal.c: De-maze the pre-processor wraps a little ...................................................................... internal.c: De-maze the pre-processor wraps a little This makes it again easier to parse internal.c by consolidating some processor wraps and labeling the ends of others. BUG=none BRANCH=none TEST=builds Change-Id: I32fb1a3fff7afa671f08fb2cc2ad406772f5e10f Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M internal.c 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/15/46815/1 diff --git a/internal.c b/internal.c index 5d74f92..4390b45 100644 --- a/internal.c +++ b/internal.c @@ -113,7 +113,7 @@ return 0; } -#endif +#endif /* IS_X86 */ static void internal_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) @@ -281,9 +281,7 @@ msg_pinfo("Continuing anyway.\n"); } } -#endif -#if IS_X86 is_laptop = 2; /* Assume that we don't know by default. */ dmi_init(); @@ -299,7 +297,7 @@ * FIXME: Find a replacement for DMI on non-x86. * FIXME: Enable Super I/O probing once port I/O is possible. */ -#endif +#endif /* IS_X86 */ /* Check laptop whitelist. */ board_handle_before_laptop(); @@ -333,7 +331,7 @@ ret = 1; goto internal_init_exit; } -#endif +#endif /* IS_X86 */ if (internal_buses_supported & BUS_NONSPI) register_par_master(&par_master_internal, internal_buses_supported); -- To view, visit https://review.coreboot.org/c/flashrom/+/46815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I32fb1a3fff7afa671f08fb2cc2ad406772f5e10f Gerrit-Change-Number: 46815 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: Makefile: Fix typo NEED_LIBUSB0 -> NEED_LIBUSB1
by Edward O'Callaghan (Code Review) 28 Oct '20

28 Oct '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46869 ) Change subject: Makefile: Fix typo NEED_LIBUSB0 -> NEED_LIBUSB1 ...................................................................... Makefile: Fix typo NEED_LIBUSB0 -> NEED_LIBUSB1 BUG=none BRANCH=none TEST=none Change-Id: I5a402d9530f73419d8317d94a8d6f745d09675ea Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/69/46869/1 diff --git a/Makefile b/Makefile index 241814a..d2b1637 100644 --- a/Makefile +++ b/Makefile @@ -1024,7 +1024,7 @@ FTDI_INCLUDES := $(call debug_shell,[ -n "$(PKG_CONFIG_LIBDIR)" ] && export PKG_CONFIG_LIBDIR="$(PKG_CONFIG_LIBDIR)" ; $(PKG_CONFIG) --cflags-only-I libftdi1) FEATURE_CFLAGS += $(FTDI_INCLUDES) FEATURE_LIBS += $(call debug_shell,grep -q "FTDISUPPORT := yes" .features && printf "%s" "$(FTDILIBS)") -# We can't set NEED_LIBUSB0 here because that would transform libftdi auto-enabling +# We can't set NEED_LIBUSB1 here because that would transform libftdi auto-enabling # into a hard requirement for libusb, defeating the purpose of auto-enabling. endif -- To view, visit https://review.coreboot.org/c/flashrom/+/46869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5a402d9530f73419d8317d94a8d6f745d09675ea Gerrit-Change-Number: 46869 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: Makefile: remove LSPCON and MST device dependency from libusb
by Shiyu Sun (Code Review) 28 Oct '20

28 Oct '20

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46870 ) Change subject: Makefile: remove LSPCON and MST device dependency from libusb ...................................................................... Makefile: remove LSPCON and MST device dependency from libusb LSPCON and MST does not depends on libusb. Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> Change-Id: If6db3a318aca349fc1ccd343d3d6d47b809eac8e --- M Makefile 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/70/46870/1 diff --git a/Makefile b/Makefile index 241814a..4a78287 100644 --- a/Makefile +++ b/Makefile @@ -812,8 +812,6 @@ override CONFIG_PICKIT2_SPI = no override CONFIG_RAIDEN = no override CONFIG_STLINKV3_SPI = no -override CONFIG_LSPCON_I2C_SPI = no -override CONFIG_REALTEK_MST_I2C_SPI = no endif ifeq ($(CONFIG_ENABLE_LIBPCI_PROGRAMMERS), no) override CONFIG_INTERNAL = no -- To view, visit https://review.coreboot.org/c/flashrom/+/46870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If6db3a318aca349fc1ccd343d3d6d47b809eac8e Gerrit-Change-Number: 46870 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: dummyflasher: fixes on VARIABLE_SIZE chip support
by Namyoon Woo (Code Review) 27 Oct '20

27 Oct '20

Namyoon Woo has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46536 ) Change subject: dummyflasher: fixes on VARIABLE_SIZE chip support ...................................................................... dummyflasher: fixes on VARIABLE_SIZE chip support This patches fixes a few bugs that two patches (https://review.coreboot.org/c/flashrom/+/44879 and https://review.coreboot.org/c/flashrom/+/45230) brought: - dummy_init() used to fail for the absence of "size" argument, which broke the run on non VARIABLE_SIZE emulation target. Now the run fails without "size" only for VARIABLE_SIZE. - probe_variable_size() used to fail if the bus type is either PARALLEL, LPC or FWH because flash->mst->par.data is null. Now dummy_init() sets up par_master_dummy.data as well as spi_master_dummyflasher.data. - atoi() is replaced with strtol(). - man page is revised to describe how to use VARIABLE_SIZE emulation target. TEST: $ flashrom -p dummy:image=dummy.bin,emulate=VARIABLE_SIZE,size=16777216 \ -w ${IMG} -V -f ... Verifying flash... VERIFIED. Writing dummy.bin $ flashrom -p dummy:image=dummy.bin,emulate=VARIABLE_SIZE -w ${IMG} -V -f ... dummy_init: the size parameter is not given. Unhandled programmer parameters (possibly due to another failure): image=dummy.bin, Error: Programmer initialization failed $ flashrom -p dummy:image=dummy.bin,emulate=SST25VF040.REMS -c SST25LF040A -w ${IMG} ... Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. Signed-off-by: Namyoon Woo <namyoon(a)google.com> Change-Id: Ie6481943a831b946a91b643b4d79e684c27e48b8 --- M dummyflasher.c M flashrom.8.tmpl 2 files changed, 20 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/36/46536/1 diff --git a/dummyflasher.c b/dummyflasher.c index 6426ad2..93d0635 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -126,7 +126,7 @@ .write_aai = default_spi_write_aai, }; -static const struct par_master par_master_dummy = { +static struct par_master par_master_dummy = { .chip_readb = dummy_chip_readb, .chip_readw = dummy_chip_readw, .chip_readl = dummy_chip_readl, @@ -166,7 +166,7 @@ unsigned int i; #if EMULATE_SPI_CHIP char *status = NULL; - int size = -1; /* size for VARIOUS_SIZE chip device */ + int size = -1; /* size for VARIABLE_SIZE chip device */ #endif #if EMULATE_CHIP struct stat image_stat; @@ -180,6 +180,7 @@ data->emu_chip = EMULATE_NONE; data->delay_us = 0; spi_master_dummyflasher.data = data; + par_master_dummy.data = data; msg_pspew("%s\n", __func__); @@ -343,7 +344,7 @@ #if EMULATE_SPI_CHIP tmp = extract_programmer_param("size"); if (tmp) { - size = atoi(tmp); + size = strtol(tmp, NULL, 10); if (size <= 0 || (size % 1024 != 0)) { msg_perr("%s: Chip size is not a multipler of 1024: %s\n", __func__, tmp); @@ -351,9 +352,6 @@ return 1; } free(tmp); - } else { - msg_perr("%s: the size parameter is not given.\n", __func__); - return 1; } #endif @@ -433,6 +431,11 @@ * flashrom -p dummy:emulate=VARIABLE_SIZE,size=4194304 */ if (!strcmp(tmp, "VARIABLE_SIZE")) { + if (size == -1) { + msg_perr("%s: the size parameter is not given.\n", __func__); + free(tmp); + return 1; + } data->emu_chip = EMULATE_VARIABLE_SIZE; data->emu_chip_size = size; data->emu_max_byteprogram_size = 256; diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index db50d59..5df0aff 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -646,8 +646,19 @@ .sp .RB "* Macronix " MX25L6436 " SPI flash chip (8192 kB, RDID, SFDP)" .sp +.RB "* Dummy vendor " VARIABLE_SIZE " SPI flash chip (configurable size, page write)" +.sp Example: .B "flashrom -p dummy:emulate=SST25VF040.REMS" +.sp +To use +.B VARIABLE_SIZE +chip, +.B size +must be specified to configure the size of the flash chip, which is a power of two. +.sp +Example: +.B "flashrom -p dummy:emulate=VARIABLE_SIZE,size=16777216,image=dummy.bin" .TP .B Persistent images .sp -- To view, visit https://review.coreboot.org/c/flashrom/+/46536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie6481943a831b946a91b643b4d79e684c27e48b8 Gerrit-Change-Number: 46536 Gerrit-PatchSet: 1 Gerrit-Owner: Namyoon Woo <namyoon(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: Mark ENE_LPC and MEC1308 as NEED_LIBPCI
by Victor Ding (Code Review) 27 Oct '20

27 Oct '20

Victor Ding has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46812 ) Change subject: Mark ENE_LPC and MEC1308 as NEED_LIBPCI ...................................................................... Mark ENE_LPC and MEC1308 as NEED_LIBPCI Both depend on functions from chipset_enable.c and board_enable.c, which requires libpci; fixing. Signed-off-by: Victor Ding <victording(a)google.com> Change-Id: I9505d7f18f4781a264e29e9667b717c061ba33b8 --- M Makefile 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/12/46812/1 diff --git a/Makefile b/Makefile index 3a0748c..241814a 100644 --- a/Makefile +++ b/Makefile @@ -823,8 +823,10 @@ override CONFIG_ATAHPT = no override CONFIG_ATAVIA = no override CONFIG_ATAPROMISE = no +override CONFIG_ENE_LPC = no override CONFIG_IT8212 = no override CONFIG_DRKAISER = no +override CONFIG_MEC1308 = no override CONFIG_NICREALTEK = no override CONFIG_NICNATSEMI = no override CONFIG_NICINTEL = no @@ -899,12 +901,14 @@ FEATURE_CFLAGS += -D'CONFIG_ENE_LPC=1' PROGRAMMER_OBJS += ene_lpc.o NEED_RAW_ACCESS += CONFIG_ENE_LPC +NEED_LIBPCI += CONFIG_ENE_LPC endif ifeq ($(CONFIG_MEC1308), yes) FEATURE_CFLAGS += -D'CONFIG_MEC1308=1' PROGRAMMER_OBJS += mec1308.o NEED_RAW_ACCESS += CONFIG_MEC1308 +NEED_LIBPCI += CONFIG_MEC1308 endif ifeq ($(CONFIG_SERPROG), yes) -- To view, visit https://review.coreboot.org/c/flashrom/+/46812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9505d7f18f4781a264e29e9667b717c061ba33b8 Gerrit-Change-Number: 46812 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Ding <victording(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: dummyflasher.c: Do not print an error if probing fails
by Angel Pons (Code Review) 27 Oct '20

27 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46524 ) Change subject: dummyflasher.c: Do not print an error if probing fails ...................................................................... dummyflasher.c: Do not print an error if probing fails This line gets printed even when not using dummyflasher at all. Drop it. TEST=Check that no spurious error message appears with ft2232_spi. Change-Id: I1a81a735db391357d1b6ee6f3e9844255efd0e19 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M dummyflasher.c 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/24/46524/1 diff --git a/dummyflasher.c b/dummyflasher.c index d233db4..afcbeb6 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -1029,13 +1029,9 @@ { unsigned int i; const struct emu_data *emu_data = get_data_from_context(flash); - if (!emu_data) { - msg_perr("No data in flash context!\n"); - return 0; - } /* Skip the probing if we don't emulate this chip. */ - if (emu_data->emu_chip != EMULATE_VARIABLE_SIZE) + if (!emu_data || emu_data->emu_chip != EMULATE_VARIABLE_SIZE) return 0; /* -- To view, visit https://review.coreboot.org/c/flashrom/+/46524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1a81a735db391357d1b6ee6f3e9844255efd0e19 Gerrit-Change-Number: 46524 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: chipset_enable.c: check return value from rphysmap() call
by Edward O'Callaghan (Code Review) 27 Oct '20

27 Oct '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46444 ) Change subject: chipset_enable.c: check return value from rphysmap() call ...................................................................... chipset_enable.c: check return value from rphysmap() call Port from the ChromiumOS fork of flashrom. Change-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M chipset_enable.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/44/46444/1 diff --git a/chipset_enable.c b/chipset_enable.c index 9769ba4..4273478 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1010,6 +1010,8 @@ uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00; msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase); void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */ + if (spibar == ERROR_PTR) + return ERROR_FATAL; /* Enable Flash Writes. * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C). -- To view, visit https://review.coreboot.org/c/flashrom/+/46444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476 Gerrit-Change-Number: 46444 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: internal.c: Co-locate global variables to top of file
by Edward O'Callaghan (Code Review) 27 Oct '20

27 Oct '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46814 ) Change subject: internal.c: Co-locate global variables to top of file ...................................................................... internal.c: Co-locate global variables to top of file This just makes internal.c at bit easier to parse and helps the read get a view of all the singleton state in one go. BUG=none BRANCH=none TEST=builds Change-Id: Id4109dfb17f63d80fb3fb3f2a1d0ab54d9eddc6e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M internal.c 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/14/46814/1 diff --git a/internal.c b/internal.c index abd90a8..5d74f92 100644 --- a/internal.c +++ b/internal.c @@ -21,6 +21,14 @@ #include "programmer.h" #include "hwaccess.h" +int is_laptop = 0; +int laptop_ok = 0; + +int force_boardenable = 0; +int force_boardmismatch = 0; + +enum chipbustype internal_buses_supported = BUS_NONE; + struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass) { struct pci_dev *temp; @@ -79,9 +87,6 @@ return NULL; } -int force_boardenable = 0; -int force_boardmismatch = 0; - #if IS_X86 void probe_superio(void) { @@ -110,9 +115,6 @@ #endif -int is_laptop = 0; -int laptop_ok = 0; - static void internal_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { @@ -167,8 +169,6 @@ .chip_writen = fallback_chip_writen, }; -enum chipbustype internal_buses_supported = BUS_NONE; - int internal_init(void) { int ret = 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/46814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id4109dfb17f63d80fb3fb3f2a1d0ab54d9eddc6e Gerrit-Change-Number: 46814 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: internal.c: Reshuffle functions to avoid forward decls
by Edward O'Callaghan (Code Review) 27 Oct '20

27 Oct '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46813 ) Change subject: internal.c: Reshuffle functions to avoid forward decls ...................................................................... internal.c: Reshuffle functions to avoid forward decls This just makes internal.c a little easier to parse and avoids some fn prototypes on the metal stack. BUG=none BRANCH=none TEST=builds Change-Id: I693e30068e6a53b5fc161d895af451540650a8fe Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M internal.c 1 file changed, 36 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/13/46813/1 diff --git a/internal.c b/internal.c index 44570a5..abd90a8 100644 --- a/internal.c +++ b/internal.c @@ -114,19 +114,48 @@ int laptop_ok = 0; static void internal_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr); + chipaddr addr) +{ + mmio_writeb(val, (void *) addr); +} + static void internal_chip_writew(const struct flashctx *flash, uint16_t val, - chipaddr addr); + chipaddr addr) +{ + mmio_writew(val, (void *) addr); +} + static void internal_chip_writel(const struct flashctx *flash, uint32_t val, - chipaddr addr); + chipaddr addr) +{ + mmio_writel(val, (void *) addr); +} + static uint8_t internal_chip_readb(const struct flashctx *flash, - const chipaddr addr); + const chipaddr addr) +{ + return mmio_readb((void *) addr); +} + static uint16_t internal_chip_readw(const struct flashctx *flash, - const chipaddr addr); + const chipaddr addr) +{ + return mmio_readw((void *) addr); +} + static uint32_t internal_chip_readl(const struct flashctx *flash, - const chipaddr addr); + const chipaddr addr) +{ + return mmio_readl((void *) addr); +} + static void internal_chip_readn(const struct flashctx *flash, uint8_t *buf, - const chipaddr addr, size_t len); + const chipaddr addr, size_t len) +{ + mmio_readn((void *)addr, buf, len); + return; +} + static const struct par_master par_master_internal = { .chip_readb = internal_chip_readb, .chip_readw = internal_chip_readw, @@ -344,46 +373,3 @@ return ret; } - -static void internal_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr) -{ - mmio_writeb(val, (void *) addr); -} - -static void internal_chip_writew(const struct flashctx *flash, uint16_t val, - chipaddr addr) -{ - mmio_writew(val, (void *) addr); -} - -static void internal_chip_writel(const struct flashctx *flash, uint32_t val, - chipaddr addr) -{ - mmio_writel(val, (void *) addr); -} - -static uint8_t internal_chip_readb(const struct flashctx *flash, - const chipaddr addr) -{ - return mmio_readb((void *) addr); -} - -static uint16_t internal_chip_readw(const struct flashctx *flash, - const chipaddr addr) -{ - return mmio_readw((void *) addr); -} - -static uint32_t internal_chip_readl(const struct flashctx *flash, - const chipaddr addr) -{ - return mmio_readl((void *) addr); -} - -static void internal_chip_readn(const struct flashctx *flash, uint8_t *buf, - const chipaddr addr, size_t len) -{ - mmio_readn((void *)addr, buf, len); - return; -} -- To view, visit https://review.coreboot.org/c/flashrom/+/46813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I693e30068e6a53b5fc161d895af451540650a8fe Gerrit-Change-Number: 46813 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: programmer: Introduce programmer alias mechanism
by Edward O'Callaghan (Code Review) 27 Oct '20

27 Oct '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38671 ) Change subject: programmer: Introduce programmer alias mechanism ...................................................................... programmer: Introduce programmer alias mechanism Originally introduced in the downstream commit ba0827acee4da6740133345f43aae386923bbaad . This was originally authored by David Hendricks so that the various flash peripheral in ChromeOS devices can be flashed. For example, flashrom -p ec -r ec.bin flashrom -p host -r host.bin Note that this requires, `CONFIG_DEFAULT_PROGRAMMER=PROGRAMMER_INTERNAL make` to be defined as build-time. BUG=b:148755493 BRANCH=none TEST=ran ./flashrom -p host --flash-name Change-Id: I73766451cd8900a9e0fe08efc7a4d81b2a35ac8d Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M cli_classic.c M it85spi.c M linux_mtd.c M linux_spi.c M programmer.c M programmer.h 6 files changed, 98 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/38671/1 diff --git a/cli_classic.c b/cli_classic.c index 73cc417..d58562b 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -329,13 +329,51 @@ break; } } - if (prog == PROGRAMMER_INVALID) { + + for (i = 0; aliases[i].name; i++) { + name = aliases[i].name; + namelen = strlen(aliases[i].name); + + if (strncmp(optarg, name, namelen)) + continue; + + switch (optarg[namelen]) { + case ':': + pparam = strdup(optarg + namelen + 1); + if (!strlen(pparam)) { + free(pparam); + pparam = NULL; + } + break; + case '\0': + break; + default: + /* The continue refers to the for-loop. + * It is here to be able to + * differentiate between foo and foobar. + */ + continue; + } + + alias = &aliases[i]; + msg_gdbg("Programmer alias: \"%s\", parameter: " + " \"%s\",\n", alias->name, pparam); + break; + } + + if ((prog == PROGRAMMER_INVALID) && !alias) { fprintf(stderr, "Error: Unknown programmer \"%s\". Valid choices are:\n", optarg); list_programmers_linebreak(0, 80, 0); msg_ginfo(".\n"); cli_classic_abort_usage(NULL); } + + if ((prog != PROGRAMMER_INVALID) && alias) { + fprintf(stderr, "Error: Alias cannot be used " + "with programmer name.\n"); + cli_classic_abort_usage(NULL); + } break; case 'R': /* print_version() is always called during startup. */ diff --git a/it85spi.c b/it85spi.c index 5ce9193..47e2337 100644 --- a/it85spi.c +++ b/it85spi.c @@ -289,6 +289,9 @@ { int ret; + if (!programming_ec()) + return 1; + if (!(internal_buses_supported & BUS_FWH)) { msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); return 1; diff --git a/linux_mtd.c b/linux_mtd.c index d2df95e..bee7cc5 100644 --- a/linux_mtd.c +++ b/linux_mtd.c @@ -363,6 +363,9 @@ int dev_num = 0; int ret = 1; + if (!programming_host()) + return 1; + param = extract_programmer_param("dev"); if (param) { char *endptr; diff --git a/linux_spi.c b/linux_spi.c index aa73c18..221a36e 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -78,6 +78,14 @@ const uint8_t mode = SPI_MODE_0; const uint8_t bits = 8; + /* + * FIXME: There might be other programmers with flash memory (such as + * an EC) connected via SPI. For now we rely on the device's driver to + * distinguish it and assume generic SPI implies host. + */ + if (!programming_host()) + return 1; + p = extract_programmer_param("spispeed"); if (p && strlen(p)) { speed_hz = (uint32_t)strtoul(p, &endp, 10) * 1000; diff --git a/programmer.c b/programmer.c index f4b4384..ffad784 100644 --- a/programmer.c +++ b/programmer.c @@ -128,6 +128,13 @@ return 0; } +struct programmer_alias aliases[] = { + { "ec", ALIAS_EC }, + { "host", ALIAS_HOST }, + { NULL }, +}; +struct programmer_alias *alias; + enum chipbustype get_buses_supported(void) { int i; diff --git a/programmer.h b/programmer.h index 3cf53b9..a7bd947 100644 --- a/programmer.h +++ b/programmer.h @@ -130,6 +130,44 @@ PROGRAMMER_INVALID /* This must always be the last entry. */ }; +enum alias_type { + ALIAS_NONE = 0, /* no alias (default) */ + ALIAS_EC, /* embedded controller */ + ALIAS_HOST, /* chipset / PCH / SoC / etc. */ +}; + +struct programmer_alias { + const char *name; + enum alias_type type; +}; + +extern struct programmer_alias *alias; +extern struct programmer_alias aliases[]; + +/** + * This function returns 'true' if current flashrom invocation is programming + * NONE. + */ +static inline int programming_none(void) { + return alias && (alias->type == ALIAS_NONE); +} + +/** + * This function returns 'true' if current flashrom invocation is programming + * the EC. + */ +static inline int programming_ec(void) { + return alias && (alias->type == ALIAS_EC); +} + +/** + * This function returns 'true' if current flashrom invocation is programming + * the HOST. + */ +static inline int programming_host(void) { + return alias && (alias->type == ALIAS_HOST); +} + enum programmer_type { PCI = 1, /* to detect uninitialized values */ USB, -- To view, visit https://review.coreboot.org/c/flashrom/+/38671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I73766451cd8900a9e0fe08efc7a4d81b2a35ac8d Gerrit-Change-Number: 38671 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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flashrom-gerrit October 2020