October 2020 - flashrom-gerrit

Change in flashrom[master]: programmer: Introduce programmer alias mechanism
by Edward O'Callaghan (Code Review) 27 Oct '20

27 Oct '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38671 ) Change subject: programmer: Introduce programmer alias mechanism ...................................................................... programmer: Introduce programmer alias mechanism Originally introduced in the downstream commit ba0827acee4da6740133345f43aae386923bbaad . This was originally authored by David Hendricks so that the various flash peripheral in ChromeOS devices can be flashed. For example, flashrom -p ec -r ec.bin flashrom -p host -r host.bin Note that this requires, `CONFIG_DEFAULT_PROGRAMMER=PROGRAMMER_INTERNAL make` to be defined as build-time. BUG=b:148755493 BRANCH=none TEST=ran ./flashrom -p host --flash-name Change-Id: I73766451cd8900a9e0fe08efc7a4d81b2a35ac8d Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M cli_classic.c M it85spi.c M linux_mtd.c M linux_spi.c M programmer.c M programmer.h 6 files changed, 98 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/38671/1 diff --git a/cli_classic.c b/cli_classic.c index 73cc417..d58562b 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -329,13 +329,51 @@ break; } } - if (prog == PROGRAMMER_INVALID) { + + for (i = 0; aliases[i].name; i++) { + name = aliases[i].name; + namelen = strlen(aliases[i].name); + + if (strncmp(optarg, name, namelen)) + continue; + + switch (optarg[namelen]) { + case ':': + pparam = strdup(optarg + namelen + 1); + if (!strlen(pparam)) { + free(pparam); + pparam = NULL; + } + break; + case '\0': + break; + default: + /* The continue refers to the for-loop. + * It is here to be able to + * differentiate between foo and foobar. + */ + continue; + } + + alias = &aliases[i]; + msg_gdbg("Programmer alias: \"%s\", parameter: " + " \"%s\",\n", alias->name, pparam); + break; + } + + if ((prog == PROGRAMMER_INVALID) && !alias) { fprintf(stderr, "Error: Unknown programmer \"%s\". Valid choices are:\n", optarg); list_programmers_linebreak(0, 80, 0); msg_ginfo(".\n"); cli_classic_abort_usage(NULL); } + + if ((prog != PROGRAMMER_INVALID) && alias) { + fprintf(stderr, "Error: Alias cannot be used " + "with programmer name.\n"); + cli_classic_abort_usage(NULL); + } break; case 'R': /* print_version() is always called during startup. */ diff --git a/it85spi.c b/it85spi.c index 5ce9193..47e2337 100644 --- a/it85spi.c +++ b/it85spi.c @@ -289,6 +289,9 @@ { int ret; + if (!programming_ec()) + return 1; + if (!(internal_buses_supported & BUS_FWH)) { msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); return 1; diff --git a/linux_mtd.c b/linux_mtd.c index d2df95e..bee7cc5 100644 --- a/linux_mtd.c +++ b/linux_mtd.c @@ -363,6 +363,9 @@ int dev_num = 0; int ret = 1; + if (!programming_host()) + return 1; + param = extract_programmer_param("dev"); if (param) { char *endptr; diff --git a/linux_spi.c b/linux_spi.c index aa73c18..221a36e 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -78,6 +78,14 @@ const uint8_t mode = SPI_MODE_0; const uint8_t bits = 8; + /* + * FIXME: There might be other programmers with flash memory (such as + * an EC) connected via SPI. For now we rely on the device's driver to + * distinguish it and assume generic SPI implies host. + */ + if (!programming_host()) + return 1; + p = extract_programmer_param("spispeed"); if (p && strlen(p)) { speed_hz = (uint32_t)strtoul(p, &endp, 10) * 1000; diff --git a/programmer.c b/programmer.c index f4b4384..ffad784 100644 --- a/programmer.c +++ b/programmer.c @@ -128,6 +128,13 @@ return 0; } +struct programmer_alias aliases[] = { + { "ec", ALIAS_EC }, + { "host", ALIAS_HOST }, + { NULL }, +}; +struct programmer_alias *alias; + enum chipbustype get_buses_supported(void) { int i; diff --git a/programmer.h b/programmer.h index 3cf53b9..a7bd947 100644 --- a/programmer.h +++ b/programmer.h @@ -130,6 +130,44 @@ PROGRAMMER_INVALID /* This must always be the last entry. */ }; +enum alias_type { + ALIAS_NONE = 0, /* no alias (default) */ + ALIAS_EC, /* embedded controller */ + ALIAS_HOST, /* chipset / PCH / SoC / etc. */ +}; + +struct programmer_alias { + const char *name; + enum alias_type type; +}; + +extern struct programmer_alias *alias; +extern struct programmer_alias aliases[]; + +/** + * This function returns 'true' if current flashrom invocation is programming + * NONE. + */ +static inline int programming_none(void) { + return alias && (alias->type == ALIAS_NONE); +} + +/** + * This function returns 'true' if current flashrom invocation is programming + * the EC. + */ +static inline int programming_ec(void) { + return alias && (alias->type == ALIAS_EC); +} + +/** + * This function returns 'true' if current flashrom invocation is programming + * the HOST. + */ +static inline int programming_host(void) { + return alias && (alias->type == ALIAS_HOST); +} + enum programmer_type { PCI = 1, /* to detect uninitialized values */ USB, -- To view, visit https://review.coreboot.org/c/flashrom/+/38671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I73766451cd8900a9e0fe08efc7a4d81b2a35ac8d Gerrit-Change-Number: 38671 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

4 10

Change in flashrom[master]: Mark ENE_LPC and MEC1308 as NEED_RAW_ACCESS
by Victor Ding (Code Review) 27 Oct '20

27 Oct '20

Victor Ding has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46811 ) Change subject: Mark ENE_LPC and MEC1308 as NEED_RAW_ACCESS ...................................................................... Mark ENE_LPC and MEC1308 as NEED_RAW_ACCESS Both uses INB/OUTB and hence should be marked as NEED_RAW_ACCESS in the makefiles; fixing. Signed-off-by: Victor Ding <victording(a)google.com> Change-Id: I6fafd9f59d06f60e9491e3e059c1205d48d8232e --- M Makefile 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/11/46811/1 diff --git a/Makefile b/Makefile index 8af7042..3a0748c 100644 --- a/Makefile +++ b/Makefile @@ -898,11 +898,13 @@ ifeq ($(CONFIG_ENE_LPC), yes) FEATURE_CFLAGS += -D'CONFIG_ENE_LPC=1' PROGRAMMER_OBJS += ene_lpc.o +NEED_RAW_ACCESS += CONFIG_ENE_LPC endif ifeq ($(CONFIG_MEC1308), yes) FEATURE_CFLAGS += -D'CONFIG_MEC1308=1' PROGRAMMER_OBJS += mec1308.o +NEED_RAW_ACCESS += CONFIG_MEC1308 endif ifeq ($(CONFIG_SERPROG), yes) -- To view, visit https://review.coreboot.org/c/flashrom/+/46811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6fafd9f59d06f60e9491e3e059c1205d48d8232e Gerrit-Change-Number: 46811 Gerrit-PatchSet: 1 Gerrit-Owner: Victor Ding <victording(a)google.com> Gerrit-MessageType: newchange

3 5

Change in flashrom[master]: flashrom.c,flash.h: Kill dead fn shutdown_free()
by Edward O'Callaghan (Code Review) 25 Oct '20

25 Oct '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46546 ) Change subject: flashrom.c,flash.h: Kill dead fn shutdown_free() ...................................................................... flashrom.c,flash.h: Kill dead fn shutdown_free() Seems to be dead code with no call sites. BUG=none BRANCH=none TEST=builds Change-Id: Ic9f33415b8a357916891cb2006612cbf5e6aa559 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M flash.h M flashrom.c 2 files changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/46/46546/1 diff --git a/flash.h b/flash.h index fefca9d..203d32d 100644 --- a/flash.h +++ b/flash.h @@ -54,7 +54,6 @@ #define PRIxPTR_WIDTH ((int)(sizeof(uintptr_t)*2)) int register_shutdown(int (*function) (void *data), void *data); -int shutdown_free(void *data); void *programmer_map_flash_region(const char *descr, uintptr_t phys_addr, size_t len); void programmer_unmap_flash_region(void *virt_addr, size_t len); void programmer_delay(unsigned int usecs); diff --git a/flashrom.c b/flashrom.c index c18a04f..26e2df8 100644 --- a/flashrom.c +++ b/flashrom.c @@ -553,12 +553,6 @@ static int check_block_eraser(const struct flashctx *flash, int k, int log); -int shutdown_free(void *data) -{ - free(data); - return 0; -} - /* Register a function to be executed on programmer shutdown. * The advantage over atexit() is that you can supply a void pointer which will * be used as parameter to the registered function upon programmer shutdown. -- To view, visit https://review.coreboot.org/c/flashrom/+/46546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic9f33415b8a357916891cb2006612cbf5e6aa559 Gerrit-Change-Number: 46546 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 3

Change in flashrom[master]: realtek_mst_i2c_spi.c: Introduce ISP enter param
by Shiyu Sun (Code Review) 24 Oct '20

24 Oct '20

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46623 ) Change subject: realtek_mst_i2c_spi.c: Introduce ISP enter param ...................................................................... realtek_mst_i2c_spi.c: Introduce ISP enter param This is needed to avoid attempt entering ISP mode multiple times. The ISP mode can only exit after a reset, so once the reset MCU parameter is set to 0, the device will not able to exit from ISP mode and hence shouldn't enter ISP again on the next operation. Without exit ISP mode, the device data, like firmware version, will not show the correct value, this param will also help to identify this situation. Example on update a firmware with A/B udpate: flashrom -p realtek_mst_i2c_spi:bus=x,reset-mcu=0,enter-isp=1 write fw flashrom -p realtek_mst_i2c_spi:bus=x,reset-mcu=0,enter-isp=0 write flag -> then either reset computer to allow update to take effect, or: flashrom -p realtek_mst_i2c_spi:bus=x,reset-mcu=1,enter-isp=0 command to trigger the update. BUG=b:152558985,b:148745673 BRANCH=none TEST=build Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> Change-Id: I58931ac8b42ab55829f102d243aea6fcfd632e3e --- M realtek_mst_i2c_spi.c 1 file changed, 24 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/23/46623/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 43cf25b..538b07a 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -432,10 +432,10 @@ return ret; } -static int get_params(int *i2c_bus, int *reset) +static int get_params(int *i2c_bus, int *reset, int *enter_isp) { - char *bus_str = NULL, *reset_str = NULL; - int ret = SPI_GENERIC_ERROR; + char *bus_str = NULL, *reset_str = NULL, *isp_str = NULL; + int ret = SPI_GENERIC_ERROR; bus_str = extract_programmer_param("bus"); if (bus_str) { @@ -478,6 +478,20 @@ *reset = 0; /* Default behaviour is no MCU reset on tear-down. */ free(reset_str); + isp_str = extract_programmer_param("enter-isp"); + if (isp_str) { + if (isp_str[0] == '1') + *enter_isp = 1; + else if (isp_str[0] == '0') + *enter_isp = 0; + else { + msg_perr("%s: Incorrect param format, enter-isp=1 or 0.\n", __func__); + ret = SPI_GENERIC_ERROR; + } + } else + *enter_isp = 1; /* Default behaviour is enter ISP on setup. */ + free(isp_str); + _get_params_failed: if (bus_str) free(bus_str); @@ -488,18 +502,20 @@ int realtek_mst_i2c_spi_init(void) { int ret = 0; - int i2c_bus = 0, reset = 0; + int i2c_bus = 0, reset = 0, enter_isp = 0; - if (get_params(&i2c_bus, &reset)) + if (get_params(&i2c_bus, &reset, &enter_isp)) return SPI_GENERIC_ERROR; int fd = i2c_open(i2c_bus, REGISTER_ADDRESS, 0); if (fd < 0) return fd; - ret |= realtek_mst_i2c_spi_enter_isp_mode(fd); - if (ret) - return ret; + if (enter_isp) { + ret |= realtek_mst_i2c_spi_enter_isp_mode(fd); + if (ret) + return ret; + } struct realtek_mst_i2c_spi_data *data = calloc(1, sizeof(struct realtek_mst_i2c_spi_data)); if (!data) { -- To view, visit https://review.coreboot.org/c/flashrom/+/46623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I58931ac8b42ab55829f102d243aea6fcfd632e3e Gerrit-Change-Number: 46623 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: Add support for Fudan SPI flash chips
by Septs (Code Review) 23 Oct '20

23 Oct '20

Septs has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46513 ) Change subject: Add support for Fudan SPI flash chips ...................................................................... Add support for Fudan SPI flash chips Signed-off-by: Jakob Petersson <github(a)jakobpetersson.se> Change-Id: I8045ecb8778fd6111fcccc075e69928f131a926a --- M flashchips.c M flashchips.h 2 files changed, 282 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/13/46513/1 diff --git a/flashchips.c b/flashchips.c index 7d10abf..48efb85 100644 --- a/flashchips.c +++ b/flashchips.c @@ -5691,6 +5691,278 @@ }, { + .vendor = "Fudan", + .name = "FM25F005", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25F005, + .total_size = 64, + .page_size = 256, + /* OTP: 256B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 16} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 2} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O (0x3B) supported */ + .voltage = {2700, 3600}, /* 2.3-2.7V acceptable results in lower performance */ + }, + + { + .vendor = "Fudan", + .name = "FM25F01", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25F01, + .total_size = 128, + .page_size = 256, + /* OTP: 256B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 2} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O (0x3B) supported */ + .voltage = {2700, 3600}, /* 2.3-2.7V acceptable results in lower performance */ + }, + + { + .vendor = "Fudan", + .name = "FM25F02(A)", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25F02, + .total_size = 256, + .page_size = 256, + /* OTP: 256B total; enter 0x3A, (A version only:) read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 8} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 256, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 256, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O (0x3B) supported */ + .voltage = {2700, 3600}, /* 2.3-2.7V acceptable results in lower performance */ + }, + + { + .vendor = "Fudan", + .name = "FM25F04(A)", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25F04, + .total_size = 512, + .page_size = 256, + /* OTP: 256B total; enter 0x3A, (A version only:) read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 512, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 512, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B), dual I/O (0x3B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Fudan", + .name = "FM25Q08", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25Q08, + .total_size = 1024, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, /* bit6 selects size of protected blocks; TODO: SR2 */ + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Fudan", + .name = "FM25Q16", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25Q16, + .total_size = 2048, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, /* bit6 selects size of protected blocks; TODO: SR2 */ + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Fudan", + .name = "FM25Q32", + .bustype = BUS_SPI, + .manufacture_id = FUDAN_ID_NOPREFIX, + .model_id = FUDAN_FM25Q32, + .total_size = 4096, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_bp2_tb_bpl, /* bit6 selects size of protected blocks; TODO: SR2 */ + .unlock = spi_disable_blockprotect_bp2_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { .vendor = "Fujitsu", .name = "MBM29F004BC", .bustype = BUS_PARALLEL, diff --git a/flashchips.h b/flashchips.h index 5b7937f..87aedc2 100644 --- a/flashchips.h +++ b/flashchips.h @@ -329,6 +329,16 @@ #define FIDELIX_FM25Q32 0x3216 #define FIDELIX_FM25Q64 0x3217 +#define FUDAN_ID 0x7F7F7F7F7F7F7FA1 /* Shanghai Fudan Microelectronics resides in bank 8 */ +#define FUDAN_ID_NOPREFIX 0xA1 /* Fudan, missing 0x7F prefix */ +#define FUDAN_FM25F005 0x3110 +#define FUDAN_FM25F01 0x3111 +#define FUDAN_FM25F02 0x3112 /* Same as FM25F02A */ +#define FUDAN_FM25F04 0x3113 /* Same as FM25F04A */ +#define FUDAN_FM25Q08 0x4014 +#define FUDAN_FM25Q16 0x4015 +#define FUDAN_FM25Q32 0x4016 + #define FUJITSU_ID 0x04 /* Fujitsu */ #define FUJITSU_MBM29DL400BC 0x0F #define FUJITSU_MBM29DL400TC 0x0C -- To view, visit https://review.coreboot.org/c/flashrom/+/46513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8045ecb8778fd6111fcccc075e69928f131a926a Gerrit-Change-Number: 46513 Gerrit-PatchSet: 1 Gerrit-Owner: Septs <github(a)septs.pw> Gerrit-MessageType: newchange

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Change in flashrom[master]: realtek_mst_i2c_spi.c: Trigger gpio 88 toggle down after write
by Shiyu Sun (Code Review) 23 Oct '20

23 Oct '20

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46448 ) Change subject: realtek_mst_i2c_spi.c: Trigger gpio 88 toggle down after write ...................................................................... realtek_mst_i2c_spi.c: Trigger gpio 88 toggle down after write BUG=b:152558985,b:148745673 BRANCH=none TEST=builds Change-Id: I1407714e1bb4cf2472090bae8a613c7103a5938c Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> --- M realtek_mst_i2c_spi.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/48/46448/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 63ff510..43cf25b 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -393,8 +393,7 @@ break; } - - /* TODO: re-enable the write protection? */ + ret |= realtek_mst_i2c_spi_toggle_gpio_88_strap(fd, false); return ret; } -- To view, visit https://review.coreboot.org/c/flashrom/+/46448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1407714e1bb4cf2472090bae8a613c7103a5938c Gerrit-Change-Number: 46448 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: it87spi.c: Prevent use-after-free bug
by Angel Pons (Code Review) 22 Oct '20

22 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46551 ) Change subject: it87spi.c: Prevent use-after-free bug ...................................................................... it87spi.c: Prevent use-after-free bug The memory for the `param` string is aliased by `dualbiosindex_suffix`. Therefore, only free the former when there are no more uses of either. Change-Id: I79f18f6077c77c0cbb8bfa431e17f9b079f11c95 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M it87spi.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/51/46551/1 diff --git a/it87spi.c b/it87spi.c index e34f5e8..79b4448 100644 --- a/it87spi.c +++ b/it87spi.c @@ -134,12 +134,13 @@ char *dualbiosindex_suffix; errno = 0; long chip_index = strtol(param, &dualbiosindex_suffix, 0); - free(param); if (errno != 0 || *dualbiosindex_suffix != '\0' || chip_index < 0 || chip_index > 1) { msg_perr("DualBIOS: Invalid chip index requested - choose 0 or 1.\n"); + free(param); exit_conf_mode_ite(port); return 1; } + free(param); if (chip_index != (tmp & 1)) { msg_pdbg("DualBIOS: Previous chip index: %d\n", tmp & 1); sio_write(port, 0xEF, (tmp & 0xFE) | chip_index); -- To view, visit https://review.coreboot.org/c/flashrom/+/46551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I79f18f6077c77c0cbb8bfa431e17f9b079f11c95 Gerrit-Change-Number: 46551 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: it87spi.c: return error when probe fails
by Nikolai Artemiev (Code Review) 21 Oct '20

21 Oct '20

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46439 ) Change subject: it87spi.c: return error when probe fails ...................................................................... it87spi.c: return error when probe fails Make it87spi_probe() return error to match CrOS flashrom. Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Change-Id: Ie122c4f954d14c713fb719ec44200b2def00fed6 --- M it87spi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/39/46439/1 diff --git a/it87spi.c b/it87spi.c index e34f5e8..90c6655 100644 --- a/it87spi.c +++ b/it87spi.c @@ -161,7 +161,7 @@ msg_pdbg("No IT87* serial flash segment enabled.\n"); exit_conf_mode_ite(port); /* Nothing to do. */ - return 0; + return 1; } msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis"); -- To view, visit https://review.coreboot.org/c/flashrom/+/46439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie122c4f954d14c713fb719ec44200b2def00fed6 Gerrit-Change-Number: 46439 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: spi: Define _XOPEN_SOURCE to get ffs() from strings.h
by Septs (Code Review) 17 Oct '20

17 Oct '20

Hello build bot (Jenkins), Nico Huber, Paul Menzel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/46512 to review the following change. Change subject: spi: Define _XOPEN_SOURCE to get ffs() from strings.h ...................................................................... spi: Define _XOPEN_SOURCE to get ffs() from strings.h Fixes build with Musl libc. Change-Id: I92b69300a302c4491e234666ac371027571801c9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/22951 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> --- M spi.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/12/46512/1 diff --git a/spi.c b/spi.c index aed2a92..f124533 100644 --- a/spi.c +++ b/spi.c @@ -18,6 +18,8 @@ * Contains the generic SPI framework */ +#define _XOPEN_SOURCE 700 /* for ffs() */ + #include <strings.h> #include <string.h> #include "flash.h" -- To view, visit https://review.coreboot.org/c/flashrom/+/46512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I92b69300a302c4491e234666ac371027571801c9 Gerrit-Change-Number: 46512 Gerrit-PatchSet: 1 Gerrit-Owner: Septs <github(a)septs.pw> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: ich7_run_opcode() fail early on transact error
by Edward O'Callaghan (Code Review) 17 Oct '20

17 Oct '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46325 ) Change subject: ichspi.c: ich7_run_opcode() fail early on transact error ...................................................................... ichspi.c: ich7_run_opcode() fail early on transact error This patch is adapted from the ChromiumOS fork. While we no longer ship and support the devices: - Lenovo S10-t3, - EEEPC, - Alex and Mario. I did however want to preserve the support for the community as the right thing to do. Downstream commit d2129f1cc036394fcf3c5232647a6e11eb1674fd http://codereview.chromium.org/6698020 Change-Id: I93198cb8536705e9b71b7fbe43a20e151c2a72a8 Original-author-by: Louis Yung-Chieh Lo <yjlou(a)chromium.org> Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/25/46325/1 diff --git a/ichspi.c b/ichspi.c index 4209d60..3668a82 100644 --- a/ichspi.c +++ b/ichspi.c @@ -929,9 +929,11 @@ while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) && --timeout) { programmer_delay(10); + if (REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) + break; /* Transaction error */ } if (!timeout) { - msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n", + msg_perr("CDS timeout, ICH7_REG_SPIS=0x%04x\n", REGREAD16(ICH7_REG_SPIS)); return 1; } -- To view, visit https://review.coreboot.org/c/flashrom/+/46325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I93198cb8536705e9b71b7fbe43a20e151c2a72a8 Gerrit-Change-Number: 46325 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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