October 2020 - flashrom-gerrit

Change in flashrom[master]: flashchips: Mark Intel 25F640S33B8 as TESTED_PREW
by Miklós Márton (Code Review) 11 Dec '20

11 Dec '20

Miklós Márton has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44342 ) Change subject: flashchips: Mark Intel 25F640S33B8 as TESTED_PREW ...................................................................... flashchips: Mark Intel 25F640S33B8 as TESTED_PREW Tested with ch341a_spi from an Atheros AP81 reference board. Change-Id: I67b5962a1ae26fd1bc7e3889f1616def28b599ef Signed-off-by: Zoltan HERPAI <wigyori(a)uid0.hu> --- M flashchips.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/42/44342/1 diff --git a/flashchips.c b/flashchips.c index 09ac9b4..1506410 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7503,7 +7503,7 @@ .page_size = 256, /* OTP: 506B total (2x 8B, 30x 16B, 1x 10B); read 0x4B; write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = -- To view, visit https://review.coreboot.org/c/flashrom/+/44342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I67b5962a1ae26fd1bc7e3889f1616def28b599ef Gerrit-Change-Number: 44342 Gerrit-PatchSet: 1 Gerrit-Owner: Miklós Márton <martonmiklosqdev(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: WIP: flashchips.c: import chips from cros flashrom
by Nikolai Artemiev (Code Review) 03 Dec '20

03 Dec '20

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46064 ) Change subject: WIP: flashchips.c: import chips from cros flashrom ...................................................................... WIP: flashchips.c: import chips from cros flashrom Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Change-Id: If6b23ad2e65258143e0045133828d9db119fb665 --- M flashchips.c 1 file changed, 217 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/46064/1 diff --git a/flashchips.c b/flashchips.c index 7d10abf..82dbf70 100644 --- a/flashchips.c +++ b/flashchips.c @@ -15814,6 +15814,68 @@ { .vendor = "Spansion", + .name = "S25FL128S_UL Uniform 128 kB Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL128S_UL, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {128 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", + .name = "S25FL128S_US Uniform 64 kB Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL128S_US, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", .name = "S25FL129P......0", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */ .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, @@ -16038,6 +16100,62 @@ { .vendor = "Spansion", + .name = "S25FL256S Large Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL256S_UL, + .total_size = 16384, /* This is just half the size.... */ + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {256 * 1024, 64} }, + .block_erase = s25fl_block_erase, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", + .name = "S25FL256S Small Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FL256S_US, + .total_size = 16384, /* This is just half the size.... */ + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = s25fl_block_erase, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", .name = "S25FL256S......0", /* hybrid: 32 (top or bottom) 4 kB sub-sectors + 64 kB sectors */ .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, @@ -16116,6 +16234,68 @@ }, { + .vendor = "Spansion", + .name = "S25FS128S Large Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FS128S_L, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = s25fs_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { + .vendor = "Spansion", + .name = "S25FS128S Small Sectors", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FS128S_S, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_big_spansion, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = s25fs_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 2000}, + }, + + { .vendor = "SyncMOS/MoselVitelic", .name = "{F,S,V}29C51001B", .bustype = BUS_PARALLEL, @@ -17014,6 +17194,43 @@ { .vendor = "Winbond", + .name = "W25Q32JW", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q32JW, + .total_size = 4096, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, + }, + + { + .vendor = "Winbond", .name = "W25Q40.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, -- To view, visit https://review.coreboot.org/c/flashrom/+/46064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If6b23ad2e65258143e0045133828d9db119fb665 Gerrit-Change-Number: 46064 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: WIP: s25f.c: import file from cros flashrom
by Nikolai Artemiev (Code Review) 03 Dec '20

03 Dec '20

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46140 ) Change subject: WIP: s25f.c: import file from cros flashrom ...................................................................... WIP: s25f.c: import file from cros flashrom Imported from cros flashrom at hash `9c4c9a56b6a0370b383df9c75d71b3bd469e672d` Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Change-Id: I2d23f9c36ce8b2959807fbeee7f60e02444e3763 --- M Makefile M chipdrivers.h M flash.h M flashrom.c A s25f.c M spi.h 6 files changed, 585 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/46140/1 diff --git a/Makefile b/Makefile index 8af7042..2de7131 100644 --- a/Makefile +++ b/Makefile @@ -638,7 +638,7 @@ CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \ sst28sf040.o 82802ab.o \ sst49lfxxxc.o sst_fwhub.o edi.o flashchips.o spi.o spi25.o spi25_statusreg.o \ - spi95.o opaque.o sfdp.o en29lv640b.o at45db.o writeprotect.o + spi95.o opaque.o sfdp.o en29lv640b.o at45db.o writeprotect.o s25f.o ############################################################################### # Library code. diff --git a/chipdrivers.h b/chipdrivers.h index cf03811..225dce7 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -20,7 +20,8 @@ #ifndef __CHIPDRIVERS_H__ #define __CHIPDRIVERS_H__ 1 -#include "flash.h" /* for chipaddr and flashctx */ +#include "flash.h" /* for chipaddr and flashctx */ +#include "writeprotect.h" /* for modifier_bits */ /* spi.c */ int spi_aai_write(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); @@ -170,6 +171,15 @@ int printlock_sst_fwhub(struct flashctx *flash); int unlock_sst_fwhub(struct flashctx *flash); +/* s25fl.c */ +int probe_spi_big_spansion(struct flashctx *flash); +int s25fl_block_erase(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + +/* s25f.c */ +int s25f_get_modifier_bits(const struct flashctx *flash, struct modifier_bits *m); +int s25f_set_modifier_bits(const struct flashctx *flash, struct modifier_bits *m); +int s25fs_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + /* w39.c */ int printlock_w39f010(struct flashctx * flash); int printlock_w39l010(struct flashctx * flash); diff --git a/flash.h b/flash.h index fefca9d..db64966 100644 --- a/flash.h +++ b/flash.h @@ -49,11 +49,17 @@ #define ERROR_OOM -100 #define TIMEOUT_ERROR -101 +struct flashrom_flashctx; +#define flashctx flashrom_flashctx /* TODO: Agree on a name and convert all occurences. */ + /* TODO: check using code for correct usage of types */ typedef uintptr_t chipaddr; #define PRIxPTR_WIDTH ((int)(sizeof(uintptr_t)*2)) int register_shutdown(int (*function) (void *data), void *data); +#define CHIP_RESTORE_CALLBACK int (*func) (struct flashctx *flash, uint8_t status) + +int register_chip_restore(CHIP_RESTORE_CALLBACK, struct flashctx *flash, uint8_t status); int shutdown_free(void *data); void *programmer_map_flash_region(const char *descr, uintptr_t phys_addr, size_t len); void programmer_unmap_flash_region(void *virt_addr, size_t len); @@ -163,8 +169,6 @@ #define TEST_BAD_PRE (struct tested){ .probe = BAD, .read = BAD, .erase = BAD, .write = NT } #define TEST_BAD_PREW (struct tested){ .probe = BAD, .read = BAD, .erase = BAD, .write = BAD } -struct flashrom_flashctx; -#define flashctx flashrom_flashctx /* TODO: Agree on a name and convert all occurences. */ typedef int (erasefunc_t)(struct flashctx *flash, unsigned int addr, unsigned int blocklen); struct flashchip { diff --git a/flashrom.c b/flashrom.c index c18a04f..6ed863b 100644 --- a/flashrom.c +++ b/flashrom.c @@ -536,6 +536,15 @@ {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; +#define CHIP_RESTORE_MAXFN 4 +static int chip_restore_fn_count = 0; +static struct chip_restore_func_data { + CHIP_RESTORE_CALLBACK; + struct flashctx *flash; + uint8_t status; +} chip_restore_fn[CHIP_RESTORE_MAXFN]; + + #define SHUTDOWN_MAXFN 32 static int shutdown_fn_count = 0; /** @private */ @@ -586,6 +595,23 @@ return 0; } +//int register_chip_restore(int (*function) (void *data), void *data) +int register_chip_restore(CHIP_RESTORE_CALLBACK, + struct flashctx *flash, uint8_t status) +{ + if (chip_restore_fn_count >= CHIP_RESTORE_MAXFN) { + msg_perr("Tried to register more than %i chip restore" + " functions.\n", CHIP_RESTORE_MAXFN); + return 1; + } + chip_restore_fn[chip_restore_fn_count].func = func; /* from macro */ + chip_restore_fn[chip_restore_fn_count].flash = flash; + chip_restore_fn[chip_restore_fn_count].status = status; + chip_restore_fn_count++; + + return 0; +} + int programmer_init(enum programmer prog, const char *param) { int ret; diff --git a/s25f.c b/s25f.c new file mode 100644 index 0000000..a30618c --- /dev/null +++ b/s25f.c @@ -0,0 +1,535 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * Neither the name of Google or the names of contributors or + * licensors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * This software is provided "AS IS," without a warranty of any kind. + * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, + * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. + * GOOGLE INC AND ITS LICENSORS SHALL NOT BE LIABLE + * FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING + * OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL + * GOOGLE OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, + * OR FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR + * PUNITIVE DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF + * LIABILITY, ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, + * EVEN IF GOOGLE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * + * s25f.c - Helper functions for Spansion S25FL and S25FS SPI flash chips. + * Uses 24 bit addressing for the FS chips and 32 bit addressing for the FL + * chips (which is required by the overlayed sector size devices). + * TODO: Implement fancy hybrid sector architecture helpers. + */ + +#include <string.h> + +#include "chipdrivers.h" +#include "hwaccess.h" +#include "spi.h" +#include "writeprotect.h" + +/* + * RDAR and WRAR are supported on chips which have more than one set of status + * and control registers and take an address of the register to read/write. + * WRR, RDSR2, and RDCR are used on chips with a more limited set of control/ + * status registers. + * + * WRR is somewhat peculiar. It shares the same opcode as JEDEC_WRSR, and if + * given one data byte (following the opcode) it acts the same way. If it's + * given two data bytes, the first data byte overwrites status register 1 + * and the second data byte overwrites config register 1. + */ +#define CMD_WRR 0x01 +#define CMD_WRDI 0x04 +#define CMD_RDSR2 0x07 /* note: read SR1 with JEDEC RDSR opcode */ +#define CMD_RDCR 0x35 +#define CMD_RDAR 0x65 +#define CMD_WRAR 0x71 + +/* TODO: For now, commands which use an address assume 24-bit addressing */ +#define CMD_WRR_LEN 3 +#define CMD_WRDI_LEN 1 +#define CMD_RDAR_LEN 4 +#define CMD_WRAR_LEN 5 + +#define CMD_RSTEN 0x66 +#define CMD_RST 0x99 + +#define CR1NV_ADDR 0x000002 +#define CR1_BPNV_O (1 << 3) +#define CR1_TBPROT_O (1 << 5) +#define CR3NV_ADDR 0x000004 +#define CR3NV_20H_NV (1 << 3) + +/* See "Embedded Algorithm Performance Tables for additional timing specs. */ +#define T_W 145 * 1000 /* NV register write time (145ms) */ +#define T_RPH 35 /* Reset pulse hold time (35us) */ +#define S25FS_T_SE 145 * 1000 /* Sector Erase Time (145ms) */ +#define S25FL_T_SE 130 * 1000 /* Sector Erase Time (130ms) */ + +static int s25f_legacy_software_reset(const struct flashctx *flash) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = 1, + .writearr = (const unsigned char[]){ CMD_RSTEN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 1, + .writearr = (const unsigned char[]){ 0xf0 }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + return result; + } + + /* Allow time for reset command to execute. The datasheet specifies + * Trph = 35us, double that to be safe. */ + programmer_delay(T_RPH * 2); + + return 0; +} + +/* "Legacy software reset" is disabled by default on S25FS, use this instead. */ +static int s25fs_software_reset(struct flashctx *flash) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = 1, + .writearr = (const unsigned char[]){ CMD_RSTEN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 1, + .writearr = (const unsigned char[]){ CMD_RST }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + return result; + } + + /* Allow time for reset command to execute. Double tRPH to be safe. */ + programmer_delay(T_RPH * 2); + + return 0; +} + +static int s25f_poll_status(const struct flashctx *flash) +{ + uint8_t tmp = spi_read_status_register(flash); + + while (tmp & SPI_SR_WIP) { + /* + * The WIP bit on S25F chips remains set to 1 if erase or + * programming errors occur, so we must check for those + * errors here. If an error is encountered, do a software + * reset to clear WIP and other volatile bits, otherwise + * the chip will be unresponsive to further commands. + */ + if (tmp & SPI_SR_ERA_ERR) { + msg_cerr("Erase error occurred\n"); + s25f_legacy_software_reset(flash); + return -1; + } + + if (tmp & (1 << 6)) { + msg_cerr("Programming error occurred\n"); + s25f_legacy_software_reset(flash); + return -1; + } + + programmer_delay(1000 * 10); + tmp = spi_read_status_register(flash); + } + + return 0; +} + +/* "Read Any Register" instruction only supported on S25FS */ +static int s25fs_read_cr(const struct flashctx *flash, uint32_t addr) +{ + int result; + uint8_t cfg; + /* By default, 8 dummy cycles are necessary for variable-latency + commands such as RDAR (see CR2NV[3:0]). */ + unsigned char read_cr_cmd[] = { + CMD_RDAR, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + }; + + result = spi_send_command(flash, sizeof(read_cr_cmd), 1, read_cr_cmd, &cfg); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return -1; + } + + return cfg; +} + +static int s25f_read_cr1(const struct flashctx *flash) +{ + int result; + uint8_t cfg; + unsigned char read_cr_cmd[] = { CMD_RDCR }; + + result = spi_send_command(flash, sizeof(read_cr_cmd), 1, read_cr_cmd, &cfg); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + return -1; + } + + return cfg; +} + +/* "Write Any Register" instruction only supported on S25FS */ +static int s25fs_write_cr(const struct flashctx *flash, + uint32_t addr, uint8_t data) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = CMD_WRAR_LEN, + .writearr = (const unsigned char[]){ + CMD_WRAR, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + data + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return -1; + } + + programmer_delay(T_W); + return s25f_poll_status(flash); +} + +static int s25f_write_cr1(const struct flashctx *flash, uint8_t data) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = CMD_WRR_LEN, + .writearr = (const unsigned char[]){ + CMD_WRR, + spi_read_status_register(flash), + data, + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + return -1; + } + + programmer_delay(T_W); + return s25f_poll_status(flash); +} + +static int s25fs_restore_cr3nv(struct flashctx *flash, uint8_t cfg) +{ + int ret = 0; + + msg_cdbg("Restoring CR3NV value to 0x%02x\n", cfg); + ret |= s25fs_write_cr(flash, CR3NV_ADDR, cfg); + ret |= s25fs_software_reset(flash); + return ret; +} + +/* returns state of top/bottom block protection, or <0 to indicate error */ +static int s25f_get_tbprot_o(const struct flashctx *flash) +{ + int cr1 = s25f_read_cr1(flash); + + if (cr1 < 0) + return -1; + + /* + * 1 = BP starts at bottom (low address) + * 0 = BP start at top (high address) + */ + return cr1 & CR1_TBPROT_O ? 1 : 0; +} + +/* fills modifier_bits struct, returns 0 to indicate success */ +int s25f_get_modifier_bits(const struct flashctx *flash, + struct modifier_bits *m) +{ + int tmp; + + memset(m, 0, sizeof(*m)); + + tmp = s25f_get_tbprot_o(flash); + if (tmp < 0) + return -1; + m->tb = tmp; + + return 0; +} + +int s25f_set_modifier_bits(const struct flashctx *flash, + struct modifier_bits *m) +{ + int cr1, cr1_orig; + + cr1 = cr1_orig = s25f_read_cr1(flash); + if (cr1 < 0) + return -1; + + /* + * Clear BPNV so that setting BP2-0 in status register gets + * written to non-volatile memory. + * + * For TBPROT: + * 1 = BP starts at bottom (low address) + * 0 = BP start at top (high address) + */ + cr1 &= ~(CR1_BPNV_O | CR1_TBPROT_O); + cr1 |= m->tb ? CR1_TBPROT_O : 0; + + if (cr1 != cr1_orig) { + msg_cdbg("%s: setting cr1 bits to 0x%02x\n", __func__, cr1); + if (s25f_write_cr1(flash, cr1) < 0) + return -1; + if (s25f_read_cr1(flash) != cr1) { + msg_cerr("%s: failed to set CR1 value\n", __func__); + return -1; + } + } else { + msg_cdbg("%s: cr1 bits already match desired value: " + "0x%02x\n", __func__, cr1); + } + + return 0; +} + +int s25fs_block_erase_d8(struct flashctx *flash, + unsigned int addr, unsigned int blocklen) +{ + unsigned char cfg; + int result; + static int cr3nv_checked = 0; + + struct spi_command erase_cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_D8, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + /* Check if hybrid sector architecture is in use and, if so, + * switch to uniform sectors. */ + if (!cr3nv_checked) { + cfg = s25fs_read_cr(flash, CR3NV_ADDR); + if (!(cfg & CR3NV_20H_NV)) { + s25fs_write_cr(flash, CR3NV_ADDR, cfg | CR3NV_20H_NV); + s25fs_software_reset(flash); + + cfg = s25fs_read_cr(flash, CR3NV_ADDR); + if (!(cfg & CR3NV_20H_NV)) { + msg_cerr("%s: Unable to enable uniform " + "block sizes.\n", __func__); + return 1; + } + + msg_cdbg("\n%s: CR3NV updated (0x%02x -> 0x%02x)\n", + __func__, cfg, + s25fs_read_cr(flash, CR3NV_ADDR)); + /* Restore CR3V when flashrom exits */ + register_chip_restore(s25fs_restore_cr3nv, flash, cfg); + } + + cr3nv_checked = 1; + } + + result = spi_send_multicommand(flash, erase_cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + + programmer_delay(S25FS_T_SE); + return s25f_poll_status(flash); +} + +int s25fl_block_erase(struct flashctx *flash, + unsigned int addr, unsigned int blocklen) +{ + int result; + + struct spi_command erase_cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_WREN + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_DC_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_DC, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .readcnt = 0, + } + }; + + result = spi_send_multicommand(flash, erase_cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + + programmer_delay(S25FL_T_SE); + return s25f_poll_status(flash); +} + + +int probe_spi_big_spansion(struct flashctx *flash) +{ + static const unsigned char cmd = JEDEC_RDID; + int ret; + unsigned char dev_id[6]; /* We care only about 6 first bytes */ + + ret = spi_send_command(flash, sizeof(cmd), sizeof(dev_id), &cmd, dev_id); + + if (!ret) { + for (size_t i = 0; i < sizeof(dev_id); i++) + msg_gdbg(" 0x%02x", dev_id[i]); + msg_gdbg(".\n"); + + if (dev_id[0] == flash->chip->manufacture_id) { + union { + uint8_t array[4]; + uint32_t whole; + } model_id; + + /* + * The structure of the RDID output is as follows: + * + * offset value meaning + * 00h 01h Manufacturer ID for Spansion + * 01h 20h 128 Mb capacity + * 01h 02h 256 Mb capacity + * 02h 18h 128 Mb capacity + * 02h 19h 256 Mb capacity + * 03h 4Dh Full size of the RDID output (ignored) + * 04h 00h FS: 256-kB physical sectors + * 04h 01h FS: 64-kB physical sectors + * 04h 00h FL: 256-kB physical sectors + * 04h 01h FL: Mix of 64-kB and 4KB overlayed sectors + * 05h 80h FL family + * 05h 81h FS family + * + * Need to use bytes 1, 2, 4, and 5 to properly identify one of eight + * possible chips: + * + * 2 types * 2 possible sizes * 2 possible sector layouts + * + */ + memcpy(model_id.array, dev_id + 1, 2); + memcpy(model_id.array + 2, dev_id + 4, 2); + if (be_to_cpu32(model_id.whole) == flash->chip->model_id) + return 1; + } + } + return 0; +} diff --git a/spi.h b/spi.h index c1ca46a..09da579 100644 --- a/spi.h +++ b/spi.h @@ -111,6 +111,11 @@ #define JEDEC_BE_D7_OUTSIZE 0x04 #define JEDEC_BE_D7_INSIZE 0x00 +/* Block Erase 0xdc is supported by Spansion chips, takes 4 byte address */ +#define JEDEC_BE_DC 0xdc +#define JEDEC_BE_DC_OUTSIZE 0x05 +#define JEDEC_BE_DC_INSIZE 0x00 + /* Sector Erase 0x20 is supported by Macronix/SST chips. */ #define JEDEC_SE 0x20 #define JEDEC_SE_OUTSIZE 0x04 @@ -129,6 +134,7 @@ /* Status Register Bits */ #define SPI_SR_WIP (0x01 << 0) #define SPI_SR_WEL (0x01 << 1) +#define SPI_SR_ERA_ERR (0x01 << 5) #define SPI_SR_AAI (0x01 << 6) /* Write Status Enable */ -- To view, visit https://review.coreboot.org/c/flashrom/+/46140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2d23f9c36ce8b2959807fbeee7f60e02444e3763 Gerrit-Change-Number: 46140 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

3 27

Change in flashrom[master]: sb600spi.c: Don't access spibar directly
by Edward O'Callaghan (Code Review) 26 Nov '20

26 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36433 ) Change subject: sb600spi.c: Don't access spibar directly ...................................................................... sb600spi.c: Don't access spibar directly Constrain the manner in which the global state of spibar is set and then subsequently accessed. This makes it easier to write unit-tests and instrument the code. Change-Id: Ic26372b9c1baebb20716eea1db1e942239ed3e48 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M sb600spi.c 1 file changed, 53 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/33/36433/1 diff --git a/sb600spi.c b/sb600spi.c index 23b36ee..7bdd11f 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -40,7 +40,13 @@ *}; */ -static uint8_t *sb600_spibar = NULL; +static uint8_t *g_sb600_spibar = NULL; + +static inline uint8_t * get_spibar(void) +{ + return g_sb600_spibar; +} + enum amd_chipset { CHIPSET_AMD_UNKNOWN, CHIPSET_SB6XX, @@ -180,16 +186,18 @@ static void reset_internal_fifo_pointer(void) { - mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2); + uint8_t *spibar = get_spibar(); + mmio_writeb(mmio_readb(spibar + 2) | 0x10, spibar + 2); /* FIXME: This loop needs a timeout and a clearer message. */ - while (mmio_readb(sb600_spibar + 0xD) & 0x7) + while (mmio_readb(spibar + 0xD) & 0x7) msg_pspew("reset\n"); } static int compare_internal_fifo_pointer(uint8_t want) { - uint8_t have = mmio_readb(sb600_spibar + 0xd) & 0x07; + uint8_t *spibar = get_spibar(); + uint8_t have = mmio_readb(spibar + 0xd) & 0x07; want %= FIFO_SIZE_OLD; if (have != want) { msg_perr("AMD SPI FIFO pointer corruption! Pointer is %d, wanted %d\n", have, want); @@ -224,8 +232,9 @@ static void execute_command(void) { msg_pspew("Executing... "); - mmio_writeb(mmio_readb(sb600_spibar + 2) | 1, sb600_spibar + 2); - while (mmio_readb(sb600_spibar + 2) & 1) + uint8_t *spibar = get_spibar(); + mmio_writeb(mmio_readb(spibar + 2) | 1, spibar + 2); + while (mmio_readb(spibar + 2) & 1) ; msg_pspew("done\n"); } @@ -239,7 +248,8 @@ unsigned char cmd = *writearr++; writecnt--; msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt); - mmio_writeb(cmd, sb600_spibar + 0); + uint8_t *spibar = get_spibar(); + mmio_writeb(cmd, spibar + 0); int ret = check_readwritecnt(flash, writecnt, readcnt); if (ret != 0) @@ -253,14 +263,14 @@ */ unsigned int readoffby1 = (writecnt > 0) ? 0 : 1; uint8_t readwrite = (readcnt + readoffby1) << 4 | (writecnt); - mmio_writeb(readwrite, sb600_spibar + 1); + mmio_writeb(readwrite, spibar + 1); reset_internal_fifo_pointer(); msg_pspew("Filling FIFO: "); unsigned int count; for (count = 0; count < writecnt; count++) { msg_pspew("[%02x]", writearr[count]); - mmio_writeb(writearr[count], sb600_spibar + 0xC); + mmio_writeb(writearr[count], spibar + 0xC); } msg_pspew("\n"); if (compare_internal_fifo_pointer(writecnt)) @@ -291,7 +301,7 @@ /* Skip the bytes we sent. */ msg_pspew("Skipping: "); for (count = 0; count < writecnt; count++) { - msg_pspew("[%02x]", mmio_readb(sb600_spibar + 0xC)); + msg_pspew("[%02x]", mmio_readb(spibar + 0xC)); } msg_pspew("\n"); if (compare_internal_fifo_pointer(writecnt)) @@ -299,14 +309,14 @@ msg_pspew("Reading FIFO: "); for (count = 0; count < readcnt; count++) { - readarr[count] = mmio_readb(sb600_spibar + 0xC); + readarr[count] = mmio_readb(spibar + 0xC); msg_pspew("[%02x]", readarr[count]); } msg_pspew("\n"); if (compare_internal_fifo_pointer(writecnt+readcnt)) return SPI_PROGRAMMER_ERROR; - if (mmio_readb(sb600_spibar + 1) != readwrite) { + if (mmio_readb(spibar + 1) != readwrite) { msg_perr("Unexpected change in AMD SPI read/write count!\n"); msg_perr("Something else is accessing the flash chip and causes random corruption.\n" "Please stop all applications and drivers and IPMI which access the flash chip.\n"); @@ -325,21 +335,22 @@ unsigned char cmd = *writearr++; writecnt--; msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt); - mmio_writeb(cmd, sb600_spibar + 0); + uint8_t *spibar = get_spibar(); + mmio_writeb(cmd, spibar + 0); int ret = check_readwritecnt(flash, writecnt, readcnt); if (ret != 0) return ret; /* Use the extended TxByteCount and RxByteCount registers. */ - mmio_writeb(writecnt, sb600_spibar + 0x48); - mmio_writeb(readcnt, sb600_spibar + 0x4b); + mmio_writeb(writecnt, spibar + 0x48); + mmio_writeb(readcnt, spibar + 0x4b); msg_pspew("Filling buffer: "); unsigned int count; for (count = 0; count < writecnt; count++) { msg_pspew("[%02x]", writearr[count]); - mmio_writeb(writearr[count], sb600_spibar + 0x80 + count); + mmio_writeb(writearr[count], spibar + 0x80 + count); } msg_pspew("\n"); @@ -347,7 +358,7 @@ msg_pspew("Reading buffer: "); for (count = 0; count < readcnt; count++) { - readarr[count] = mmio_readb(sb600_spibar + 0x80 + (writecnt + count) % FIFO_SIZE_YANGTZE); + readarr[count] = mmio_readb(spibar + 0x80 + (writecnt + count) % FIFO_SIZE_YANGTZE); msg_pspew("[%02x]", readarr[count]); } msg_pspew("\n"); @@ -375,16 +386,17 @@ { bool success = false; uint8_t speed = spispeed->speed; + uint8_t *spibar = get_spibar(); msg_pdbg("Setting SPI clock to %s (0x%x).\n", spispeed->name, speed); if (amd_gen >= CHIPSET_YANGTZE) { - rmmio_writew((speed << 12) | (speed << 8) | (speed << 4) | speed, sb600_spibar + 0x22); - uint16_t tmp = mmio_readw(sb600_spibar + 0x22); + rmmio_writew((speed << 12) | (speed << 8) | (speed << 4) | speed, spibar + 0x22); + uint16_t tmp = mmio_readw(spibar + 0x22); success = (((tmp >> 12) & 0xf) == speed && ((tmp >> 8) & 0xf) == speed && ((tmp >> 4) & 0xf) == speed && ((tmp >> 0) & 0xf) == speed); } else { - rmmio_writeb((mmio_readb(sb600_spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), sb600_spibar + 0xd); - success = (speed == ((mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3)); + rmmio_writeb((mmio_readb(spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), spibar + 0xd); + success = (speed == ((mmio_readb(spibar + 0xd) >> 4) & 0x3)); } if (!success) { @@ -396,11 +408,12 @@ static int set_mode(struct pci_dev *dev, uint8_t read_mode) { - uint32_t tmp = mmio_readl(sb600_spibar + 0x00); + uint8_t *spibar = get_spibar(); + uint32_t tmp = mmio_readl(spibar + 0x00); tmp &= ~(0x6 << 28 | 0x1 << 18); /* Clear mode bits */ tmp |= ((read_mode & 0x6) << 28) | ((read_mode & 0x1) << 18); - rmmio_writel(tmp, sb600_spibar + 0x00); - if (tmp != mmio_readl(sb600_spibar + 0x00)) + rmmio_writel(tmp, spibar + 0x00); + if (tmp != mmio_readl(spibar + 0x00)) return 1; return 0; } @@ -409,6 +422,7 @@ { uint32_t tmp; uint8_t spispeed_idx = 3; /* Default to 16.5 MHz */ + uint8_t *spibar = get_spibar(); char *spispeed = extract_programmer_param("spispeed"); if (spispeed != NULL) { @@ -450,7 +464,7 @@ "Normal (up to 66 MHz)", /* 6 */ "Fast Read", /* 7 (Not defined in the Bolton datasheet.) */ }; - tmp = mmio_readl(sb600_spibar + 0x00); + tmp = mmio_readl(spibar + 0x00); uint8_t read_mode = ((tmp >> 28) & 0x6) | ((tmp >> 18) & 0x1); msg_pdbg("SpiReadMode=%s (%i)\n", spireadmodes[read_mode], read_mode); if (read_mode != 6) { @@ -463,11 +477,11 @@ } if (amd_gen >= CHIPSET_YANGTZE) { - tmp = mmio_readb(sb600_spibar + 0x20); + tmp = mmio_readb(spibar + 0x20); msg_pdbg("UseSpi100 is %sabled\n", (tmp & 0x1) ? "en" : "dis"); if ((tmp & 0x1) == 0) { - rmmio_writeb(tmp | 0x1, sb600_spibar + 0x20); - tmp = mmio_readb(sb600_spibar + 0x20) & 0x1; + rmmio_writeb(tmp | 0x1, spibar + 0x20); + tmp = mmio_readb(spibar + 0x20) & 0x1; if (tmp == 0) { msg_perr("Enabling Spi100 failed.\n"); return 1; @@ -475,7 +489,7 @@ msg_pdbg("Enabling Spi100 succeeded.\n"); } - tmp = mmio_readw(sb600_spibar + 0x22); /* SPI 100 Speed Config */ + tmp = mmio_readw(spibar + 0x22); /* SPI 100 Speed Config */ msg_pdbg("NormSpeedNew is %s\n", spispeeds[(tmp >> 12) & 0xf].name); msg_pdbg("FastSpeedNew is %s\n", spispeeds[(tmp >> 8) & 0xf].name); msg_pdbg("AltSpeedNew is %s\n", spispeeds[(tmp >> 4) & 0xf].name); @@ -483,15 +497,15 @@ } } else { if (amd_gen >= CHIPSET_SB89XX && amd_gen <= CHIPSET_HUDSON234) { - bool fast_read = (mmio_readl(sb600_spibar + 0x00) >> 18) & 0x1; + bool fast_read = (mmio_readl(spibar + 0x00) >> 18) & 0x1; msg_pdbg("Fast Reads are %sabled\n", fast_read ? "en" : "dis"); if (fast_read) { msg_pdbg("Disabling them temporarily.\n"); - rmmio_writel(mmio_readl(sb600_spibar + 0x00) & ~(0x1 << 18), - sb600_spibar + 0x00); + rmmio_writel(mmio_readl(spibar + 0x00) & ~(0x1 << 18), + spibar + 0x00); } } - tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; + tmp = (mmio_readb(spibar + 0xd) >> 4) & 0x3; msg_pdbg("NormSpeed is %s\n", spispeeds[tmp].name); } return set_speed(dev, amd_gen, &spispeeds[spispeed_idx]); @@ -581,14 +595,14 @@ return 0; /* Physical memory has to be mapped at page (4k) boundaries. */ - sb600_spibar = rphysmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); - if (sb600_spibar == ERROR_PTR) + g_sb600_spibar = rphysmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); + if (g_sb600_spibar == ERROR_PTR) return ERROR_FATAL; /* The low bits of the SPI base address are used as offset into * the mapped page. */ - sb600_spibar += tmp & 0xfff; + g_sb600_spibar += tmp & 0xfff; int amd_gen = determine_generation(dev); if (amd_gen < 0) @@ -649,7 +663,8 @@ * * <1> see handle_speed */ - tmp = mmio_readl(sb600_spibar + 0x00); + uint8_t *spibar = get_spibar(); + tmp = mmio_readl(spibar + 0x00); msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1); if (amd_gen >= CHIPSET_YANGTZE) msg_pdbg(", IllegalAccess=%i", (tmp >> 21) & 0x1); @@ -679,7 +694,7 @@ } if (amd_gen >= CHIPSET_SB89XX) { - tmp = mmio_readb(sb600_spibar + 0x1D); + tmp = mmio_readb(spibar + 0x1D); msg_pdbg("Using SPI_CS%d\n", tmp & 0x3); /* FIXME: Handle SpiProtect* configuration on Yangtze. */ } -- To view, visit https://review.coreboot.org/c/flashrom/+/36433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic26372b9c1baebb20716eea1db1e942239ed3e48 Gerrit-Change-Number: 36433 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: sb600spi.c: Remove 'amd_gen' out of global state.
by Edward O'Callaghan (Code Review) 25 Nov '20

25 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/36432 ) Change subject: sb600spi.c: Remove 'amd_gen' out of global state. ...................................................................... sb600spi.c: Remove 'amd_gen' out of global state. Have 'determine_generation()' explicitly return 'amd_gen' and then pass the state into what requires it. Thus making the code more pure, easier to read and more unit-testable. Change-Id: I99fbad9486123c6b921eab83756de54a53ddfa7a Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M sb600spi.c 1 file changed, 12 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/32/36432/1 diff --git a/sb600spi.c b/sb600spi.c index 8daaf03..23b36ee 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -51,7 +51,6 @@ CHIPSET_YANGTZE, CHIPSET_PROMONTORY, }; -static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; #define FIFO_SIZE_OLD 8 #define FIFO_SIZE_YANGTZE 71 @@ -110,7 +109,7 @@ /* Determine the chipset's version and identify the respective SMBUS device. */ static int determine_generation(struct pci_dev *dev) { - amd_gen = CHIPSET_AMD_UNKNOWN; + enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; msg_pdbg2("Trying to determine the generation of the SPI interface... "); if (dev->device_id == 0x438d) { amd_gen = CHIPSET_SB6XX; @@ -173,11 +172,10 @@ "Please report this to flashrom(a)flashrom.org and include this log and\n" "the output of lspci -nnvx, thanks!\n", __func__, dev->vendor_id, dev->device_id); - if (amd_gen == CHIPSET_AMD_UNKNOWN) { + if (amd_gen == CHIPSET_AMD_UNKNOWN) msg_perr("Could not determine chipset generation."); - return -1; - } - return 0; + + return amd_gen; } static void reset_internal_fifo_pointer(void) @@ -373,7 +371,7 @@ { "800 kHz", 0x07 }, }; -static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed) +static int set_speed(struct pci_dev *dev, enum amd_chipset amd_gen, const struct spispeed *spispeed) { bool success = false; uint8_t speed = spispeed->speed; @@ -407,7 +405,7 @@ return 0; } -static int handle_speed(struct pci_dev *dev) +static int handle_speed(struct pci_dev *dev, enum amd_chipset amd_gen) { uint32_t tmp; uint8_t spispeed_idx = 3; /* Default to 16.5 MHz */ @@ -496,10 +494,10 @@ tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; msg_pdbg("NormSpeed is %s\n", spispeeds[tmp].name); } - return set_speed(dev, &spispeeds[spispeed_idx]); + return set_speed(dev, amd_gen, &spispeeds[spispeed_idx]); } -static int handle_imc(struct pci_dev *dev) +static int handle_imc(struct pci_dev *dev, enum amd_chipset amd_gen) { /* Handle IMC everywhere but sb600 which does not have one. */ if (amd_gen == CHIPSET_SB6XX) @@ -592,7 +590,8 @@ */ sb600_spibar += tmp & 0xfff; - if (determine_generation(dev) < 0) + int amd_gen = determine_generation(dev); + if (amd_gen < 0) return ERROR_NONFATAL; /* How to read the following table and similar ones in this file: @@ -725,10 +724,10 @@ return 0; } - if (handle_speed(dev) != 0) + if (handle_speed(dev, amd_gen) != 0) return ERROR_FATAL; - if (handle_imc(dev) != 0) + if (handle_imc(dev, amd_gen) != 0) return ERROR_FATAL; /* Starting with Yangtze the SPI controller got a different interface with a much bigger buffer. */ -- To view, visit https://review.coreboot.org/c/flashrom/+/36432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I99fbad9486123c6b921eab83756de54a53ddfa7a Gerrit-Change-Number: 36432 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: tests/: [RFC]: Implement unit-testing using mtest
by Edward O'Callaghan (Code Review) 24 Nov '20

24 Nov '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38954 ) Change subject: tests/: [RFC]: Implement unit-testing using mtest ...................................................................... tests/: [RFC]: Implement unit-testing using mtest The following allows the use of a ultra minimal unit-testing framework and includes an example that exercises the libflashrom init self-check and tear-down. Some work is needed to get include paths into a healthy state so that inner logic can be instrumented however this sets the tone. Change-Id: I18d68d3ace32b5be264aae2988a8ed84c779be43 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M meson.build A tests/meson.build A tests/selfcheck.c 3 files changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/54/38954/1 diff --git a/meson.build b/meson.build index 375089c..8a998d0 100644 --- a/meson.build +++ b/meson.build @@ -402,3 +402,10 @@ ) subdir('util') + +# unit-test framework +munit_dep = dependency( + 'munit', + fallback: ['munit', 'munit_dep'] +) +subdir('tests') diff --git a/tests/meson.build b/tests/meson.build new file mode 100644 index 0000000..af65a81 --- /dev/null +++ b/tests/meson.build @@ -0,0 +1,12 @@ +root_includes = include_directories(['../', '../subprojects']) + +srcs = files('selfcheck.c') + +flashrom_tests = executable('flashrom_unit_tests', + srcs, + include_directories : root_includes, + dependencies : munit_dep, + link_with : flashrom +) + +test('munit test flashrom', flashrom_tests) diff --git a/tests/selfcheck.c b/tests/selfcheck.c new file mode 100644 index 0000000..abe88b1 --- /dev/null +++ b/tests/selfcheck.c @@ -0,0 +1,41 @@ +#include <stdlib.h> + +#include "munit/munit.h" + +#include "libflashrom.h" + + +MunitResult self_check_test(const MunitParameter params[], void* user_data_or_fixture) +{ + //Programmer table miscompilation! + munit_assert(flashrom_init(1 /*perform_selfcheck*/) == 0); + munit_assert(flashrom_shutdown() == 0); + + return MUNIT_OK; +} + +MunitTest tests[] = { + { + (char *)"/self_check", /* name */ + self_check_test, /* test */ + NULL, /* setup */ + NULL, /* tear_down */ + MUNIT_TEST_OPTION_NONE, /* options */ + NULL /* parameters */ + }, + /* Mark the end of the array with an entry where the test + * function is NULL */ + { NULL, NULL, NULL, NULL, MUNIT_TEST_OPTION_NONE, NULL } +}; + +static const MunitSuite suite = { + (char *)"/basic", /* name */ + tests, /* tests */ + NULL, /* suites */ + 1, /* iterations */ + MUNIT_SUITE_OPTION_NONE /* options */ +}; + +int main (int argc, char* argv[]) { + return munit_suite_main(&suite, (char*)"flashrom", argc, argv); +} -- To view, visit https://review.coreboot.org/c/flashrom/+/38954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I18d68d3ace32b5be264aae2988a8ed84c779be43 Gerrit-Change-Number: 38954 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashrom: Added Support for BoyaMicro BY25Q128AS
by Jack Olsen (Code Review) 20 Nov '20

20 Nov '20

Jack Olsen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44308 ) Change subject: flashrom: Added Support for BoyaMicro BY25Q128AS ...................................................................... flashrom: Added Support for BoyaMicro BY25Q128AS Tested on Buspirate Change-Id: I881ba86cfaa82e43c73360135d47c74d896cc191 --- M flashchips.c M flashchips.h 2 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/44308/1 diff --git a/flashchips.c b/flashchips.c index 09ac9b4..5c60b2c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -3442,6 +3442,44 @@ .voltage = {3000, 3600}, }, + { + .vendor = "Boya", + .name = "BY25Q128AS", + .bustype = BUS_SPI, + .manufacture_id = BOYA_ID, + .model_id = BOYA_BY25Q128AS, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect_at25fs040, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + { .vendor = "Bright", .name = "BM29F040", diff --git a/flashchips.h b/flashchips.h index 4ae6c07..9d19ef5 100644 --- a/flashchips.h +++ b/flashchips.h @@ -207,6 +207,10 @@ #define ATMEL_AT49F080 0x23 #define ATMEL_AT49F080T 0x27 +/* Boya Microelectronics Inc.*/ +#define BOYA_ID 0x68 +#define BOYA_BY25Q128AS 0x4018 + /* Bright Microelectronics has the same manufacturer ID as Hyundai... */ #define BRIGHT_ID 0xAD /* Bright Microelectronics */ #define BRIGHT_BM29F040 0x40 -- To view, visit https://review.coreboot.org/c/flashrom/+/44308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I881ba86cfaa82e43c73360135d47c74d896cc191 Gerrit-Change-Number: 44308 Gerrit-PatchSet: 1 Gerrit-Owner: Jack Olsen <omegasec(a)tutanota.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: test_build.sh: Move build test procedure to repository
by Patrick Georgi (Code Review) 03 Nov '20

03 Nov '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/46894 ) Change subject: test_build.sh: Move build test procedure to repository ...................................................................... test_build.sh: Move build test procedure to repository Instead of hard coding the test procedure on qa.coreboot.org, allow running a script in the repo instead. The server is already adapted to do that, so once there's a test_build.sh file in the toplevel directory, it's run in place of the default operation. The content of this change mirrors the default operation exactly so should serve as a good starting point. The script is executed in an encapsulate[0] context with the workspace, /tmp and $HOME/.ccache writable, everything else read-only and network disabled. It should return 0 on success, anything else on failure, as is normal for UNIX processes. [0] https://review.coreboot.org/cgit/encapsulate.git Change-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- A test_build.sh 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/46894/1 diff --git a/test_build.sh b/test_build.sh new file mode 100755 index 0000000..0e7f37a --- /dev/null +++ b/test_build.sh @@ -0,0 +1,8 @@ +#!/bin/sh +set -e + +make CONFIG_EVERYTHING=yes WARNERROR=yes + +meson -p out +(cd out && ninja) +(cd out && ninja test) -- To view, visit https://review.coreboot.org/c/flashrom/+/46894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95 Gerrit-Change-Number: 46894 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: spi25.c: Use JEDEC_CE consts in spi_simple_write_cmd() calls
by Edward O'Callaghan (Code Review) 31 Oct '20

31 Oct '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47005 ) Change subject: spi25.c: Use JEDEC_CE consts in spi_simple_write_cmd() calls ...................................................................... spi25.c: Use JEDEC_CE consts in spi_simple_write_cmd() calls Make use of the JEDEC_CE_{60,62,C7} defined constants of the op-codes in each of the spi_simple_write_cmd() calls to assist in readability. BUG=none BRANCH=none TEST=builds same object. Change-Id: I1876781672fe03302af4a6ff8d365f2e6c3b6f13 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M spi25.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/05/47005/1 diff --git a/spi25.c b/spi25.c index 1e797c8..15cca39 100644 --- a/spi25.c +++ b/spi25.c @@ -463,19 +463,19 @@ static int spi_chip_erase_60(struct flashctx *flash) { /* This usually takes 1-85s, so wait in 1s steps. */ - return spi_simple_write_cmd(flash, 0x60, 1000 * 1000); + return spi_simple_write_cmd(flash, JEDEC_CE_60, 1000 * 1000); } static int spi_chip_erase_62(struct flashctx *flash) { /* This usually takes 2-5s, so wait in 100ms steps. */ - return spi_simple_write_cmd(flash, 0x62, 100 * 1000); + return spi_simple_write_cmd(flash, JEDEC_CE_62, 100 * 1000); } static int spi_chip_erase_c7(struct flashctx *flash) { /* This usually takes 1-85s, so wait in 1s steps. */ - return spi_simple_write_cmd(flash, 0xc7, 1000 * 1000); + return spi_simple_write_cmd(flash, JEDEC_CE_C7, 1000 * 1000); } int spi_block_erase_52(struct flashctx *flash, unsigned int addr, -- To view, visit https://review.coreboot.org/c/flashrom/+/47005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1876781672fe03302af4a6ff8d365f2e6c3b6f13 Gerrit-Change-Number: 47005 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 6

Change in flashrom[master]: spi25.c: Use define const in spi_simple_write_cmd() fn
by Edward O'Callaghan (Code Review) 31 Oct '20

31 Oct '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47004 ) Change subject: spi25.c: Use define const in spi_simple_write_cmd() fn ...................................................................... spi25.c: Use define const in spi_simple_write_cmd() fn This uses the JEDEC_WREN_OUTSIZE define in the spi_simple_write_cmd() helper function to improve readability. BUG=none BRANCH=none TEST=builds same object Change-Id: I1b5ede4435ba014320fa8cf9490dc23cdfba4fd6 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M spi25.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/04/47004/1 diff --git a/spi25.c b/spi25.c index dd4543d..1e797c8 100644 --- a/spi25.c +++ b/spi25.c @@ -325,7 +325,7 @@ struct spi_command cmds[] = { { .readarr = 0, - .writecnt = 1, + .writecnt = JEDEC_WREN_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_WREN }, }, { .readarr = 0, -- To view, visit https://review.coreboot.org/c/flashrom/+/47004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1b5ede4435ba014320fa8cf9490dc23cdfba4fd6 Gerrit-Change-Number: 47004 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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