February 2018 - flashrom-gerrit

Change in flashrom[master]: NVIDIA Tegra2 SPI controller support
by build bot (Jenkins) (Code Review) 18 Feb '18

18 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23804 ) Change subject: NVIDIA Tegra2 SPI controller support ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/1148/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/966/ : SUCCESS -- To view, visit https://review.coreboot.org/23804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3bfaa4ee5035ff3dde92c42fda00785a86e569ee Gerrit-Change-Number: 23804 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 18 Feb 2018 11:47:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in flashrom[master]: NVIDIA Tegra2 SPI controller support
by Nico Huber (Code Review) 18 Feb '18

18 Feb '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/23804 Change subject: NVIDIA Tegra2 SPI controller support ...................................................................... NVIDIA Tegra2 SPI controller support On Tue, Jun 28, 2011 at 5:54 PM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2006(a)gmx.net> wrote: > 2-3-add_arm_isms.patch > Have you checked with an architecture guru that sync_primitive() can > really be empty, not only for that arch in general, but also for > accesses to a mmapped region the way flashrom does it? > Nope. Scattered resources/forum posts about ARMv7 suggest that peripheral memory is strongly ordered. Also, the U-Boot code doesn't have special handling for sync primitives AFAICT. I'm pretty new to ARM... Any advice from experts on this list would be appreciated. On Tue, Jun 28, 2011 at 5:54 PM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2006(a)gmx.net> wrote: > 3-3-add_tegra2_spi_controller.patch > Not your fault, but we really need a way to detect the target > architecture in the Makefile. The issues of which SPI masters to include > for internal exists on all architectures. Any ideas? I experimented with > uname calls in the past, but that checks the host arch, not the target > arch. Grepping the preprocessor output for the compiler might be an option. > echo|gcc -dM -E -|grep "whatever\|arch\|defines" > Or you try this pretty straightforward solution: > > Create a file arch.h with these contents: > #if defined (__i386__) > #define __FLASHROM_ARCH__ "x86" > #elif defined (__x86_64__) > #define __FLASHROM_ARCH__ "x86_64" > #elif defined (__mips) || defined (__mips__) || defined (_mips) || > defined (mips) > #define __FLASHROM_ARCH__ "mips" > #elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) > || defined(__ppc64__) > #define __FLASHROM_ARCH__ "ppc" > #endif > __FLASHROM_ARCH__ > > Then run > gcc -E arch.h|grep -v ^# > The result on my machine will be > "x86" > Side note: Such an arch.h file (with some extensions) might save us from > having to check every possible arch define everywhere we need to > differentiate between architectures. > > I will comment on the Tegra2 SPI driver later, we should get the > infrastructure questions addressed first. I've updated this patch set on top of the other patches you've been working on (autodetect target processor <http://patchwork.coreboot.org/patch/3256/> and the libpci hack <http://patchwork.coreboot.org/patch/3255/>). The difference between this patchset and the previous one is pretty minor. We can now discard the first patch which #ifdef'd out PCI code for ARM targets. The remaining differences are mostly centered around the Makefile and arch.h New patches are: Signed-off-by: David Hendricks <dhendrix(a)google.com> Change-Id: I3bfaa4ee5035ff3dde92c42fda00785a86e569ee --- M Makefile M processor_enable.c M programmer.h A tegra2_spi.c A tegra2_spi.h 5 files changed, 549 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/04/23804/1 diff --git a/Makefile b/Makefile index 26f978f..570dcc72 100644 --- a/Makefile +++ b/Makefile @@ -344,6 +344,10 @@ ifeq ($(ARCH),"x86") PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o else +ifeq ($(ARCH),"arm") +PROGRAMMER_OBJS += tegra2_spi.o +else +endif endif NEED_PCI := yes endif diff --git a/processor_enable.c b/processor_enable.c index d680f97..1d363e7 100644 --- a/processor_enable.c +++ b/processor_enable.c @@ -81,6 +81,48 @@ } #endif +#if defined(__arm__) +#include <stdio.h> +#include <string.h> +#include <ctype.h> + +/* Returns true if the /proc/cpuinfo contains a line: "CPU part *: *0xc09". + * TODO: need to extend in future for same SPI controller in chip family. + */ +static int is_tegra2(void) +{ + FILE *cpuinfo; + uint32_t impl = 0, architecture = 0, variant = 0, part = 0; + const char *name = "CPU part"; + const char *value = "0xc09"; + int ret = 0; + + cpuinfo = fopen("/proc/cpuinfo", "rb"); + if (!cpuinfo) + return 0; + while (!feof(cpuinfo)) { + char line[512], *ptr; + if (fgets(line, sizeof(line), cpuinfo) == NULL) + break; + ptr = line; + while (*ptr && isspace((unsigned char)*ptr)) + ptr++; + if (strncmp(ptr, name, strlen(name)) == 0) + ptr += strlen(name); + while (*ptr && isspace((unsigned char)*ptr)) + ptr++; + if (*ptr != ':') + continue; + ptr++; + while (*ptr && isspace((unsigned char)*ptr)) + ptr++; + ret = (strncmp(ptr, value, strlen(value)) == 0); + } + fclose(cpuinfo); + return ret; +} +#endif + int processor_flash_enable(void) { /* FIXME: detect loongson on FreeBSD and OpenBSD as well. */ @@ -90,6 +132,13 @@ return 0; } #endif + +#if defined (__arm__) + if (is_tegra2()) { + msg_pdbg("Detected NVIDIA Tegra 2.\n"); + return tegra2_spi_init(); + } +#endif /* Not implemented yet. Oh well. */ return 1; } diff --git a/programmer.h b/programmer.h index 6a28dbe..979f109 100644 --- a/programmer.h +++ b/programmer.h @@ -523,6 +523,9 @@ SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, #endif +#if defined(__arm__) + SPI_CONTROLLER_TEGRA2, +#endif #endif #if CONFIG_FT2232_SPI == 1 SPI_CONTROLLER_FT2232, @@ -588,6 +591,13 @@ /* sb600spi.c */ int sb600_probe_spi(struct pci_dev *dev); +/* tegra2_spi.c */ +int tegra2_spi_init(void); +int tegra2_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); +int tegra2_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int tegra2_spi_write(struct flashchip *flash, uint8_t *buf, int start, int len); + /* wbsio_spi.c */ int wbsio_check_for_spi(void); #endif diff --git a/tegra2_spi.c b/tegra2_spi.c new file mode 100644 index 0000000..8168b79 --- /dev/null +++ b/tegra2_spi.c @@ -0,0 +1,405 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 NVIDIA Corporation + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__arm__) +#include <assert.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +#include "flash.h" +#include "programmer.h" +#include "tegra2_spi.h" + +static void *gpio_base, *clkrst_base, *apbmisc_base, *spi_base; + +#define SPI_TIMEOUT 50000 /* 100ms = 50000 * 2us */ + +/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */ +#define UART_DISABLE_PORT 8 +#define UART_DISABLE_BIT 3 + +/* Config port:bit as GPIO, not SFPIO (default) */ +static void __set_config(unsigned port, unsigned bit, int type) +{ + u32 u; + + msg_pdbg("%s: port = %d, bit = %d, %s\n", __func__, + port, bit, type ? "GPIO" : "SFPIO"); + + u = mmio_readl(GPIO_CNF(port)); + if (type) /* GPIO */ + u |= 1 << bit; + else + u &= ~(1 << bit); + rmmio_writel(u, GPIO_CNF(port)); +} + +/* Config GPIO port:bit as input or output (OE) */ +static void __set_direction(unsigned port, unsigned bit, int output) +{ + u32 u; + + msg_pdbg("%s: port = %d, bit = %d, %s\n", __func__, + port, bit, output ? "OUT" : "IN"); + + u = mmio_readl(GPIO_OE(port)); + if (output) + u |= 1 << bit; + else + u &= ~(1 << bit); + rmmio_writel(u, GPIO_OE(port)); +} + +/* set GPIO OUT port:bit as 0 or 1 */ +static void __set_level(unsigned port, unsigned bit, int high) +{ + u32 u; + + msg_pdbg("%s: port = %d, bit %d == %d\n", __func__, + port, bit, high); + + u = mmio_readl(GPIO_OUT(port)); + if (high) + u |= 1 << bit; + else + u &= ~(1 << bit); + rmmio_writel(u, GPIO_OUT(port)); +} + +/* set GPIO port:bit as an output, with polarity 'value' */ +static int tg2_gpio_direction_output(unsigned port, unsigned bit, int value) +{ + msg_pdbg("%s: port = %d, bit = %d, value = %d\n", + __func__, port, bit, value); + + /* Configure as a GPIO */ + __set_config(port, bit, 1); + + /* Configure GPIO output value. */ + __set_level(port, bit, value); + + /* Configure GPIO direction as output. */ + __set_direction(port, bit, 1); + + return 0; +} + +static void spi_cs_activate(void) +{ + uint32_t *spi_cmd = (uint32_t *)spi_base; + + /* + * CS is negated on Tegra, so drive a 1 to get a 0 + */ + mmio_writel(mmio_readl(spi_cmd) | SPI_CMD_CS_VAL, spi_cmd); + msg_pspew("%s: CS driven %s\n", __func__, + (mmio_readl(spi_cmd) & SPI_CMD_CS_VAL) ? "LOW" : "HIGH"); +} + +static void spi_cs_deactivate(void) +{ + uint32_t *spi_cmd = (uint32_t *)spi_base; + + + /* + * CS is negated on Tegra, so drive a 0 to get a 1 + */ + mmio_writel(mmio_readl(spi_cmd) & ~SPI_CMD_CS_VAL, spi_cmd); + msg_pspew("%s: CS driven %s\n", __func__, + (mmio_readl(spi_cmd) & SPI_CMD_CS_VAL) ? "LOW" : "HIGH"); +} + +/* Helper function to calculate the clock cycle in this round. + * Also updates the byte count remaining to be used this round. + * + * For example, we want to write 6 bytes to SPI and then read 5 bytes back. + * + * +---+---+---+---+---+---+ + * | W | W | W | W | W | W | + * +---+---+---+---+---+---+---+---+---+---+---+ + * | R | R | R | R | R | + * +---+---+---+---+---+ + * |<-- round 0 -->| + * |<-- round 1 -->| + * |<-- round 2 -->| + * + * So that the continuous calling this function would get: + * + * round| RET| writecnt readcnt bits to_write to_read + * -----+----+--------------------------------------------- + * INIT | | 6 5 + * 0 | 1 | 2 5 32 4 0 + * 1 | 1 | 0 3 32 2 2 + * 2 | 1 | 0 0 24 0 3 + * 3 | 0 | - - - - - + * + */ +int next4Bytes(uint32_t *writecnt, uint32_t *readcnt, int *num_bits, + uint32_t *to_write, uint32_t *to_read) { + assert(writecnt); + assert(readcnt); + assert(num_bits); + assert(to_write); + assert(to_read); + + *to_write = min(*writecnt, 4); + *to_read = min(*readcnt, 4 - *to_write); + + *writecnt -= *to_write; + *readcnt -= *to_read; + + *num_bits = (*to_write + *to_read) * 8; + + if (*num_bits) + return 1; /* need to be called again. */ + else + return 0; /* handled write and read requests. */ +} + +/* + * Tegra2 FIFO design is ... interesting. For example, you want to Tx 2 bytes: + * + * +---+---+ + * writearr[]: | 0 | 1 | + * +---+---+ + * \ \ + * \ \ + * \ \ + * \ \ + * \ \ + * 31 +---+---+---+---+ 0 + * tmp(32-bits): | X | X | 0 | 1 | + * +---+---+---+---+ LSB + * + * It is neither little or big endian. The first bit for SPI controller to + * transfer is the bit 15 in FIFO, neither bit 31 or bit 0, because the transfer + * length is 16 bits (2 bytes). + * + * Rx follows the similar rule. First bit comes at bit 0, and the whole FIFO + * left-shifts 1 bit for every bit comes in. Hence, after reading 3 bytes, + * the first coming bit will reside in bit 23. + */ +int tegra2_spi_send_command(unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + int retval = 0; + uint8_t *delayed_msg = NULL; /* for UART is disabled. */ + uint32_t *spi_cmd = (uint32_t *)spi_base; + uint32_t *spi_sts = (uint32_t *)(spi_base + 0x04); + uint32_t *tx_fifo = (uint32_t *)(spi_base + 0x10); + uint32_t *rx_fifo = (uint32_t *)(spi_base + 0x20); + uint32_t status; + uint32_t to_write, to_read; /* byte counts to fill FIFO. */ + uint32_t bits; /* bit count to tell SPI controller. */ + + mmio_writel(mmio_readl(spi_sts), spi_sts); + mmio_writel(mmio_readl(spi_cmd) | SPI_CMD_TXEN | SPI_CMD_RXEN, spi_cmd); + spi_cs_activate(); + + while (next4Bytes(&writecnt, &readcnt, &bits, &to_write, &to_read)) { + int i; + uint32_t tmp; + uint32_t tm; /* timeout counter */ + + /* prepare Tx FIFO */ + for (tmp = 0, i = 0; i < to_write; ++i) { + tmp |= (*writearr++) << ((bits / 8 - 1 - i) * 8); + } + mmio_writel(tmp, tx_fifo); + + /* Kick the SCLK running: Shift out TX FIFO, and receive RX. */ + mmio_writel(mmio_readl(spi_cmd) & ~SPI_CMD_BIT_LENGTH_MASK, + spi_cmd); + mmio_writel(mmio_readl(spi_cmd) | (bits - 1), + spi_cmd); + mmio_writel(mmio_readl(spi_cmd) | SPI_CMD_GO, spi_cmd); + + /* Wait for controller completes the task. */ + for (tm = 0; tm < SPI_TIMEOUT; ++tm) { + if (((status = mmio_readl(spi_sts)) & + (SPI_STAT_BSY | SPI_STAT_RDY)) == SPI_STAT_RDY) + break; + /* We setup clock to 6MHz, so that we shall come back + * after: 1 / (6MHz) * 8 bits = 1.333us + */ + programmer_delay(2); + } + mmio_writel(mmio_readl(spi_sts) | SPI_STAT_RDY, spi_sts); + + /* Since the UART is disabled here, we delay printing the + * message until spi_cs_deactivate() is called. + */ + if (tm >= SPI_TIMEOUT) { + static uint8_t err[256]; + retval = -1; + snprintf(err, sizeof(err), + "%s():%d BSY&RDY timeout, status = 0x%08x\n", + __func__, __LINE__, status); + delayed_msg = err; + break; + } + + /* read RX FIFO */ + tmp = mmio_readl(rx_fifo); + for (i = 0; i < to_read; ++i) { + *readarr++ = (tmp >> ((to_read - 1 - i) * 8)) & 0xFF; + } + } + + mmio_writel(status = mmio_readl(spi_sts), spi_sts); + + spi_cs_deactivate(); + if (delayed_msg) { + msg_perr("%s\n", delayed_msg); + } + + return retval; +} + +int tegra2_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + return spi_read_chunked(flash, buf, start, len, + spi_programmer->max_data_read); +} + +int tegra2_spi_write(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + return spi_write_chunked(flash, buf, start, len, + spi_programmer->max_data_write); +} + +/* Unmap register spaces */ +int tegra2_spi_shutdown(void *data) +{ + physunmap(gpio_base, 4096); + physunmap(clkrst_base, 4096); + physunmap(apbmisc_base, 4096); + physunmap(spi_base - 0x380, 4096); + return 0; +} + +static const struct spi_programmer spi_programmer_tegra2 = { + .type = SPI_CONTROLLER_TEGRA2, + /* FIFO depth is 32, packets can be up to 32-bits in length. */ + .max_data_read = 128, + .max_data_write = 128, + .command = tegra2_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = tegra2_spi_read, + .write_256 = tegra2_spi_write, +}; + +/* Map register spaces */ +int tegra2_spi_init(void) +{ + u32 val; + uint32_t *spi_cmd; + uint32_t *spi_sts; + + buses_supported = CHIP_BUSTYPE_SPI; + register_spi_programmer(&spi_programmer_tegra2); + + gpio_base = physmap("GPIO", TEGRA2_GPIO_BASE, 4096); + clkrst_base = physmap("CLK/RST", NV_ADDRESS_MAP_PPSB_CLK_RST_BASE, + 4096); + apbmisc_base = physmap("APB MISC", NV_ADDRESS_MAP_APB_MISC_BASE, 4096); + /* non-page offset */ + spi_base = physmap("SPI", TEGRA2_SPI_BASE - 0x380, 4096) + 0x380; + + register_shutdown(tegra2_spi_shutdown, NULL); + + flashbase = 0; /* FIXME: to make sanity check happy. */ + + /* Init variables */ + spi_cmd = (uint32_t *)spi_base; + spi_sts = (uint32_t *)(spi_base + 0x04); + + /* + * SPI reset/clocks init - reset SPI, set clocks, release from reset + */ + + /* SWE_SPI1_RST: Hold SPI controller 1 in reset */ + val = mmio_readl(clkrst_base + 0x08) | 0x800; + rmmio_writel(val, (clkrst_base + 0x08)); + msg_pdbg("%s: ClkRst = %08x\n", __func__, val); + + /* CLK_ENB_SPI1: Enable clock to SPI 1 Controller */ + val = mmio_readl(clkrst_base + 0x14) | 0x800; + rmmio_writel(val, (clkrst_base + 0x14)); + msg_pdbg("%s: ClkEnable = %08x\n", __func__, val); + + /* Change default SPI clock from 12MHz to 6MHz, same as BootROM */ + val = mmio_readl(clkrst_base + 0x114) | 0x2; + rmmio_writel(val, (clkrst_base + 0x114)); + msg_pdbg("%s: ClkSrc = %08x\n", __func__, val); + + /* SWE_SPI1_RST: Clear SPI1 reset bit (take it out of reset), + * use regular mmio_writel (restore callback already registered) */ + val = mmio_readl(clkrst_base + 0x08) & 0xFFFFF7FF; + mmio_writel(val, (clkrst_base + 0x08)); + msg_pdbg("%s: ClkRst final = %08x\n", __func__, val); + + /* Clear stale status here */ + mmio_writel(SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | + SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF, spi_sts); + msg_pdbg("%s: STATUS = %08x\n", __func__, mmio_readl(spi_sts)); + + /* + * Use sw-controlled CS, so we can clock in data after ReadID, etc. + */ + mmio_writel(mmio_readl(spi_cmd) | SPI_CMD_CS_SOFT, spi_cmd); + msg_pdbg("%s: COMMAND = %08x\n", __func__, mmio_readl(spi_cmd)); + + /* + * SPI pins on Tegra2 are muxed - change pinmux last due to UART issue + */ + val = mmio_readl(apbmisc_base + 0x88) | 0xC0000000; + rmmio_writel(val, (apbmisc_base + 0x88)); + msg_pdbg("%s: PinMuxRegC = %08x\n", __func__, val); + + /* Set Z_LSPI to non-tristate mode */ + val = mmio_readl(apbmisc_base + 0x20) & 0xFFFFFFFE; + rmmio_writel(val, (apbmisc_base + 0x20)); + msg_pdbg("%s: TriStateReg = %08x\n", __func__, val); + + /* delay 100ms so that all chars in buffer (1KB) can be flushed. */ + programmer_delay(100000); + + /* + * We need to dynamically change the pinmux, shared w/UART RXD/CTS! + */ + val = mmio_readl(apbmisc_base + 0x84) | 0x0000000C; /* 3 = SFLASH */ + rmmio_writel(val, (apbmisc_base + 0x84)); + msg_pdbg("%s: PinMuxRegB = %08x\n", __func__, val); + + /* On Seaboard, MOSI/MISO are shared w/UART. + * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity. + * Enable UART later (cs_deactivate) so we can use it for U-Boot comms. + */ + msg_pdbg("%s: DISABLING UART!\n", __func__); + tg2_gpio_direction_output(UART_DISABLE_PORT, UART_DISABLE_BIT, 1); + + return 0; +} +#endif diff --git a/tegra2_spi.h b/tegra2_spi.h new file mode 100644 index 0000000..0ab8f01 --- /dev/null +++ b/tegra2_spi.h @@ -0,0 +1,81 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 NVIDIA Corporation + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __TEGRA2_SPI_H__ +#define __TEGRA2_SPI_H__ + +// *************************************************************************** +// Hardware BARs + +#define TEGRA2_GPIO_BASE 0x6000D000 +#define TEGRA2_SPI_BASE 0x7000C380 +#define NV_ADDRESS_MAP_PPSB_CLK_RST_BASE 0x60006000 +#define NV_ADDRESS_MAP_APB_MISC_BASE 0x70000000 + +// *************************************************************************** +// Clock/reset controller +#define CLK_RST_ENB_H_0_OFFSET 0x14 +#define CLK_RST_ENB_H_0_SPI1 (1 << 11) + +// *************************************************************************** +// GPIO controller + +#define GPIO_OFF(port) (((port / 4) * 128) + ((port % 4) * 4)) +#define GPIO_CNF(port) (gpio_base + GPIO_OFF(port) + 0x00) +#define GPIO_OE(port) (gpio_base + GPIO_OFF(port) + 0x10) +#define GPIO_OUT(port) (gpio_base + GPIO_OFF(port) + 0x20) +#define GPIO_IN(port) (gpio_base + GPIO_OFF(port) + 0x30) +#define GPIO_INT_STA(port) (gpio_base + GPIO_OFF(port) + 0x40) +#define GPIO_INT_ENB(port) (gpio_base + GPIO_OFF(port) + 0x50) +#define GPIO_INT_LVL(port) (gpio_base + GPIO_OFF(port) + 0x60) +#define GPIO_INT_CLR(port) (gpio_base + GPIO_OFF(port) + 0x70) + +#define SPI_CMD_GO (1 << 30) +#define SPI_CMD_ACTIVE_SCLK (1 << 26) +#define SPI_CMD_CK_SDA (1 << 21) +#define SPI_CMD_ACTIVE_SDA (1 << 18) +#define SPI_CMD_CS_POL (1 << 16) +#define SPI_CMD_TXEN (1 << 15) +#define SPI_CMD_RXEN (1 << 14) +#define SPI_CMD_CS_VAL (1 << 13) +#define SPI_CMD_CS_SOFT (1 << 12) +#define SPI_CMD_CS_DELAY (1 << 9) +#define SPI_CMD_CS3_EN (1 << 8) +#define SPI_CMD_CS2_EN (1 << 7) +#define SPI_CMD_CS1_EN (1 << 6) +#define SPI_CMD_CS0_EN (1 << 5) +#define SPI_CMD_BIT_LENGTH (1 << 4) +#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F + +#define SPI_STAT_BSY (1 << 31) +#define SPI_STAT_RDY (1 << 30) +#define SPI_STAT_RXF_FLUSH (1 << 29) +#define SPI_STAT_TXF_FLUSH (1 << 28) +#define SPI_STAT_RXF_UNR (1 << 27) +#define SPI_STAT_TXF_OVF (1 << 26) +#define SPI_STAT_RXF_EMPTY (1 << 25) +#define SPI_STAT_RXF_FULL (1 << 24) +#define SPI_STAT_TXF_EMPTY (1 << 23) +#define SPI_STAT_TXF_FULL (1 << 22) +#define SPI_STAT_SEL_TXRX_N (1 << 16) +#define SPI_STAT_CUR_BLKCNT (1 << 15) + +#endif /* __TEGRA2_SPI_H__ */ -- To view, visit https://review.coreboot.org/23804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3bfaa4ee5035ff3dde92c42fda00785a86e569ee Gerrit-Change-Number: 23804 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[master]: dmi: Don't print dmidecode shell error
by build bot (Jenkins) (Code Review) 17 Feb '18

17 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23802 ) Change subject: dmi: Don't print dmidecode shell error ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/1147/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/965/ : SUCCESS -- To view, visit https://review.coreboot.org/23802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3ded8e1bad14b5e809185a79c4e3a17329b1ecb9 Gerrit-Change-Number: 23802 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Feb 2018 14:41:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in flashrom[master]: dmi: Don't print dmidecode shell error
by Nico Huber (Code Review) 17 Feb '18

17 Feb '18

Hello Stefan Reinauer, I'd like you to do a code review. Please visit https://review.coreboot.org/23802 to review the following change. Change subject: dmi: Don't print dmidecode shell error ...................................................................... dmi: Don't print dmidecode shell error Don't print the error "sh: dmidecode: not found" if dmidecode is not there. Uses stderr redirection to /dev/null (or NUL on win32). Change-Id: I3ded8e1bad14b5e809185a79c4e3a17329b1ecb9 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- M dmi.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/02/23802/1 diff --git a/dmi.c b/dmi.c index 729cdb1..69b1d89 100644 --- a/dmi.c +++ b/dmi.c @@ -292,7 +292,11 @@ #else /* CONFIG_INTERNAL_DMI */ #define DMI_COMMAND_LEN_MAX 300 -static const char *dmidecode_command = "dmidecode"; +#if defined (_WIN32) +static const char *dmidecode_command = "dmidecode.exe 2>NUL"; +#else +static const char *dmidecode_command = "dmidecode 2>/dev/null"; +#endif static char *get_dmi_string(const char *string_name) { -- To view, visit https://review.coreboot.org/23802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3ded8e1bad14b5e809185a79c4e3a17329b1ecb9 Gerrit-Change-Number: 23802 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org>

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Change in flashrom[master]: flashchips: Add ZD25D20
by Nico Huber (Code Review) 17 Feb '18

17 Feb '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/23702 ) Change subject: flashchips: Add ZD25D20 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/23702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idf805252647be44e28296a161d2e6160710bcc71 Gerrit-Change-Number: 23702 Gerrit-PatchSet: 3 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Feb 2018 14:11:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in flashrom[master]: flashchips: Add Zettadevice ZD25D40
by Nico Huber (Code Review) 17 Feb '18

17 Feb '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/23701 ) Change subject: flashchips: Add Zettadevice ZD25D40 ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/23701/2/flashchips.h File flashchips.h: https://review.coreboot.org/#/c/23701/2/flashchips.h@960 PS2, Line 960: #define ZETTADEVICE_ID 0x9F /* Zetta Device */ 0xba says the datasheet (0x9f is the rdid instruction?) -- To view, visit https://review.coreboot.org/23701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0400b059ddacdf166d1b77f619becec3a250cece Gerrit-Change-Number: 23701 Gerrit-PatchSet: 2 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Feb 2018 14:10:00 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in flashrom[master]: flashchips: Add Winbond W25P80/16/32 support
by Nico Huber (Code Review) 17 Feb '18

17 Feb '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/23700 ) Change subject: flashchips: Add Winbond W25P80/16/32 support ...................................................................... Patch Set 2: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/23700/2/flashchips.h File flashchips.h: https://review.coreboot.org/#/c/23700/2/flashchips.h@916 PS2, Line 916: #define WINBOND_NEX_W25P32 0x2016 Should be placed above, i.e. keep sorted by id? -- To view, visit https://review.coreboot.org/23700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie09ba8e28fee35c42e17ca05219dc673413de93b Gerrit-Change-Number: 23700 Gerrit-PatchSet: 2 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Feb 2018 13:57:05 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in flashrom[master]: board_enable: Whitelist several ThinkPad laptops
by Nico Huber (Code Review) 15 Feb '18

15 Feb '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/23781 ) Change subject: board_enable: Whitelist several ThinkPad laptops ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/23781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I772f8e109c56a5fd40f6b1aff0f592b915669c17 Gerrit-Change-Number: 23781 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Feb 2018 16:09:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in flashrom[master]: board_enable: Whitelist several ThinkPad laptops
by build bot (Jenkins) (Code Review) 15 Feb '18

15 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23781 ) Change subject: board_enable: Whitelist several ThinkPad laptops ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/1146/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/964/ : SUCCESS -- To view, visit https://review.coreboot.org/23781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I772f8e109c56a5fd40f6b1aff0f592b915669c17 Gerrit-Change-Number: 23781 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Feb 2018 16:08:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in flashrom[master]: board_enable: Whitelist several ThinkPad laptops
by Nico Huber (Code Review) 15 Feb '18

15 Feb '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/23781 Change subject: board_enable: Whitelist several ThinkPad laptops ...................................................................... board_enable: Whitelist several ThinkPad laptops Newly whitelisted laptops include: * ThinkPad R400 * ThinkPad T500 * ThinkPad W500 * Libiquity Taurinus X200 Change-Id: I772f8e109c56a5fd40f6b1aff0f592b915669c17 Signed-off-by: Leah Rowe <leah(a)libreboot.org> --- M board_enable.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/23781/1 diff --git a/board_enable.c b/board_enable.c index b6e17ef..f2952c7 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2428,14 +2428,18 @@ {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, + {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad R400", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad R400", 0, OK, p2_whitelist_laptop}, {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad T400", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T400", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad T500", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T500", 0, OK, p2_whitelist_laptop}, {0x8086, 0x1E22, 0x17AA, 0x21F6, 0x8086, 0x1E55, 0x17AA, 0x21F6, "^ThinkPad T530", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T530", 0, OK, p2_whitelist_laptop}, {0x8086, 0x27a0, 0x17aa, 0x2015, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60", 0, OK, p2_whitelist_laptop}, {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60(s)", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad W500", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad W500", 0, OK, p2_whitelist_laptop}, {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad X200", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X200", 0, OK, p2_whitelist_laptop}, {0x8086, 0x3B07, 0x17AA, 0x2166, 0x8086, 0x3B30, 0x17AA, 0x2167, "^Lenovo X201", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X201", 0, OK, p2_whitelist_laptop}, {0x8086, 0x1E22, 0x17AA, 0x21FA, 0x8086, 0x1E55, 0x17AA, 0x21FA, "^ThinkPad X230", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X230", 0, OK, p2_whitelist_laptop}, {0x8086, 0x27A0, 0x17AA, 0x2017, 0x8086, 0x27B9, 0x17AA, 0x2009, "^ThinkPad X60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X60(s)", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^Taurinus X200", "Libiquity", "Taurinus X200", P2, "Libiquity", "ThinkPad X200", 0, OK, p2_whitelist_laptop}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, {0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0, 0, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise}, -- To view, visit https://review.coreboot.org/23781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I772f8e109c56a5fd40f6b1aff0f592b915669c17 Gerrit-Change-Number: 23781 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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flashrom-gerrit February 2018